drivers/spi/spi-mpc52xx-psc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC52xx PSC in SPI mode driver.
0004  *
0005  * Maintainer: Dragos Carp
0006  *
0007  * Copyright (C) 2006 TOPTICA Photonics AG.
0008  */
0009
0010 #include <linux/module.h>
0011 #include <linux/types.h>
0012 #include <linux/errno.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/workqueue.h>
0017 #include <linux/completion.h>
0018 #include <linux/io.h>
0019 #include <linux/delay.h>
0020 #include <linux/spi/spi.h>
0021 #include <linux/fsl_devices.h>
0022 #include <linux/slab.h>
0023 #include <linux/of_irq.h>
0024
0025 #include <asm/mpc52xx.h>
0026 #include <asm/mpc52xx_psc.h>
0027
0028 #define MCLK 20000000 /* PSC port MClk in hz */
0029
0030 struct mpc52xx_psc_spi {
0031     /* fsl_spi_platform data */
0032     void (*cs_control)(struct spi_device *spi, bool on);
0033     u32 sysclk;
0034
0035     /* driver internal data */
0036     struct mpc52xx_psc __iomem *psc;
0037     struct mpc52xx_psc_fifo __iomem *fifo;
0038     unsigned int irq;
0039     u8 bits_per_word;
0040
0041     struct completion done;
0042 };
0043
0044 /* controller state */
0045 struct mpc52xx_psc_spi_cs {
0046     int bits_per_word;
0047     int speed_hz;
0048 };
0049
0050 /* set clock freq, clock ramp, bits per work
0051  * if t is NULL then reset the values to the default values
0052  */
0053 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
0054         struct spi_transfer *t)
0055 {
0056     struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
0057
0058     cs->speed_hz = (t && t->speed_hz)
0059             ? t->speed_hz : spi->max_speed_hz;
0060     cs->bits_per_word = (t && t->bits_per_word)
0061             ? t->bits_per_word : spi->bits_per_word;
0062     cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
0063     return 0;
0064 }
0065
0066 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
0067 {
0068     struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
0069     struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
0070     struct mpc52xx_psc __iomem *psc = mps->psc;
0071     u32 sicr;
0072     u16 ccr;
0073
0074     sicr = in_be32(&psc->sicr);
0075
0076     /* Set clock phase and polarity */
0077     if (spi->mode & SPI_CPHA)
0078         sicr |= 0x00001000;
0079     else
0080         sicr &= ~0x00001000;
0081     if (spi->mode & SPI_CPOL)
0082         sicr |= 0x00002000;
0083     else
0084         sicr &= ~0x00002000;
0085
0086     if (spi->mode & SPI_LSB_FIRST)
0087         sicr |= 0x10000000;
0088     else
0089         sicr &= ~0x10000000;
0090     out_be32(&psc->sicr, sicr);
0091
0092     /* Set clock frequency and bits per word
0093      * Because psc->ccr is defined as 16bit register instead of 32bit
0094      * just set the lower byte of BitClkDiv
0095      */
0096     ccr = in_be16((u16 __iomem *)&psc->ccr);
0097     ccr &= 0xFF00;
0098     if (cs->speed_hz)
0099         ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
0100     else /* by default SPI Clk 1MHz */
0101         ccr |= (MCLK / 1000000 - 1) & 0xFF;
0102     out_be16((u16 __iomem *)&psc->ccr, ccr);
0103     mps->bits_per_word = cs->bits_per_word;
0104
0105     if (mps->cs_control)
0106         mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
0107 }
0108
0109 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
0110 {
0111     struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
0112
0113     if (mps->cs_control)
0114         mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
0115 }
0116
0117 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
0118 /* wake up when 80% fifo full */
0119 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
0120
0121 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
0122                         struct spi_transfer *t)
0123 {
0124     struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
0125     struct mpc52xx_psc __iomem *psc = mps->psc;
0126     struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
0127     unsigned rb = 0;    /* number of bytes receieved */
0128     unsigned sb = 0;    /* number of bytes sent */
0129     unsigned char *rx_buf = (unsigned char *)t->rx_buf;
0130     unsigned char *tx_buf = (unsigned char *)t->tx_buf;
0131     unsigned rfalarm;
0132     unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
0133     unsigned recv_at_once;
0134     int last_block = 0;
0135
0136     if (!t->tx_buf && !t->rx_buf && t->len)
0137         return -EINVAL;
0138
0139     /* enable transmiter/receiver */
0140     out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
0141     while (rb < t->len) {
0142         if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
0143             rfalarm = MPC52xx_PSC_RFALARM;
0144             last_block = 0;
0145         } else {
0146             send_at_once = t->len - sb;
0147             rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
0148             last_block = 1;
0149         }
0150
0151         dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
0152         for (; send_at_once; sb++, send_at_once--) {
0153             /* set EOF flag before the last word is sent */
0154             if (send_at_once == 1 && last_block)
0155                 out_8(&psc->ircr2, 0x01);
0156
0157             if (tx_buf)
0158                 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
0159             else
0160                 out_8(&psc->mpc52xx_psc_buffer_8, 0);
0161         }
0162
0163
0164         /* enable interrupts and wait for wake up
0165          * if just one byte is expected the Rx FIFO genererates no
0166          * FFULL interrupt, so activate the RxRDY interrupt
0167          */
0168         out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
0169         if (t->len - rb == 1) {
0170             out_8(&psc->mode, 0);
0171         } else {
0172             out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
0173             out_be16(&fifo->rfalarm, rfalarm);
0174         }
0175         out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
0176         wait_for_completion(&mps->done);
0177         recv_at_once = in_be16(&fifo->rfnum);
0178         dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
0179
0180         send_at_once = recv_at_once;
0181         if (rx_buf) {
0182             for (; recv_at_once; rb++, recv_at_once--)
0183                 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
0184         } else {
0185             for (; recv_at_once; rb++, recv_at_once--)
0186                 in_8(&psc->mpc52xx_psc_buffer_8);
0187         }
0188     }
0189     /* disable transmiter/receiver */
0190     out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
0191
0192     return 0;
0193 }
0194
0195 int mpc52xx_psc_spi_transfer_one_message(struct spi_controller *ctlr,
0196                      struct spi_message *m)
0197 {
0198     struct spi_device *spi;
0199     struct spi_transfer *t = NULL;
0200     unsigned cs_change;
0201     int status;
0202
0203     spi = m->spi;
0204     cs_change = 1;
0205     status = 0;
0206     list_for_each_entry (t, &m->transfers, transfer_list) {
0207         if (t->bits_per_word || t->speed_hz) {
0208             status = mpc52xx_psc_spi_transfer_setup(spi, t);
0209             if (status < 0)
0210                 break;
0211         }
0212
0213         if (cs_change)
0214             mpc52xx_psc_spi_activate_cs(spi);
0215         cs_change = t->cs_change;
0216
0217         status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
0218         if (status)
0219             break;
0220         m->actual_length += t->len;
0221
0222         spi_transfer_delay_exec(t);
0223
0224         if (cs_change)
0225             mpc52xx_psc_spi_deactivate_cs(spi);
0226     }
0227
0228     m->status = status;
0229     if (status || !cs_change)
0230         mpc52xx_psc_spi_deactivate_cs(spi);
0231
0232     mpc52xx_psc_spi_transfer_setup(spi, NULL);
0233
0234     spi_finalize_current_message(ctlr);
0235
0236     return 0;
0237 }
0238
0239 static int mpc52xx_psc_spi_setup(struct spi_device *spi)
0240 {
0241     struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
0242
0243     if (spi->bits_per_word%8)
0244         return -EINVAL;
0245
0246     if (!cs) {
0247         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
0248         if (!cs)
0249             return -ENOMEM;
0250         spi->controller_state = cs;
0251     }
0252
0253     cs->bits_per_word = spi->bits_per_word;
0254     cs->speed_hz = spi->max_speed_hz;
0255
0256     return 0;
0257 }
0258
0259 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
0260 {
0261     kfree(spi->controller_state);
0262 }
0263
0264 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
0265 {
0266     struct mpc52xx_psc __iomem *psc = mps->psc;
0267     struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
0268     u32 mclken_div;
0269     int ret;
0270
0271     /* default sysclk is 512MHz */
0272     mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
0273     ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
0274     if (ret)
0275         return ret;
0276
0277     /* Reset the PSC into a known state */
0278     out_8(&psc->command, MPC52xx_PSC_RST_RX);
0279     out_8(&psc->command, MPC52xx_PSC_RST_TX);
0280     out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
0281
0282     /* Disable interrupts, interrupts are based on alarm level */
0283     out_be16(&psc->mpc52xx_psc_imr, 0);
0284     out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
0285     out_8(&fifo->rfcntl, 0);
0286     out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
0287
0288     /* Configure 8bit codec mode as a SPI master and use EOF flags */
0289     /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
0290     out_be32(&psc->sicr, 0x0180C800);
0291     out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
0292
0293     /* Set 2ms DTL delay */
0294     out_8(&psc->ctur, 0x00);
0295     out_8(&psc->ctlr, 0x84);
0296
0297     mps->bits_per_word = 8;
0298
0299     return 0;
0300 }
0301
0302 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
0303 {
0304     struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
0305     struct mpc52xx_psc __iomem *psc = mps->psc;
0306
0307     /* disable interrupt and wake up the work queue */
0308     if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
0309         out_be16(&psc->mpc52xx_psc_imr, 0);
0310         complete(&mps->done);
0311         return IRQ_HANDLED;
0312     }
0313     return IRQ_NONE;
0314 }
0315
0316 /* bus_num is used only for the case dev->platform_data == NULL */
0317 static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
0318                 u32 size, unsigned int irq, s16 bus_num)
0319 {
0320     struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0321     struct mpc52xx_psc_spi *mps;
0322     struct spi_master *master;
0323     int ret;
0324
0325     master = spi_alloc_master(dev, sizeof(*mps));
0326     if (master == NULL)
0327         return -ENOMEM;
0328
0329     dev_set_drvdata(dev, master);
0330     mps = spi_master_get_devdata(master);
0331
0332     /* the spi->mode bits understood by this driver: */
0333     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
0334
0335     mps->irq = irq;
0336     if (pdata == NULL) {
0337         dev_warn(dev,
0338              "probe called without platform data, no cs_control function will be called\n");
0339         mps->cs_control = NULL;
0340         mps->sysclk = 0;
0341         master->bus_num = bus_num;
0342         master->num_chipselect = 255;
0343     } else {
0344         mps->cs_control = pdata->cs_control;
0345         mps->sysclk = pdata->sysclk;
0346         master->bus_num = pdata->bus_num;
0347         master->num_chipselect = pdata->max_chipselect;
0348     }
0349     master->setup = mpc52xx_psc_spi_setup;
0350     master->transfer_one_message = mpc52xx_psc_spi_transfer_one_message;
0351     master->cleanup = mpc52xx_psc_spi_cleanup;
0352     master->dev.of_node = dev->of_node;
0353
0354     mps->psc = ioremap(regaddr, size);
0355     if (!mps->psc) {
0356         dev_err(dev, "could not ioremap I/O port range\n");
0357         ret = -EFAULT;
0358         goto free_master;
0359     }
0360     /* On the 5200, fifo regs are immediately ajacent to the psc regs */
0361     mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
0362
0363     ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
0364                 mps);
0365     if (ret)
0366         goto free_master;
0367
0368     ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
0369     if (ret < 0) {
0370         dev_err(dev, "can't configure PSC! Is it capable of SPI?\n");
0371         goto free_irq;
0372     }
0373
0374     init_completion(&mps->done);
0375
0376     ret = spi_register_master(master);
0377     if (ret < 0)
0378         goto free_irq;
0379
0380     return ret;
0381
0382 free_irq:
0383     free_irq(mps->irq, mps);
0384 free_master:
0385     if (mps->psc)
0386         iounmap(mps->psc);
0387     spi_master_put(master);
0388
0389     return ret;
0390 }
0391
0392 static int mpc52xx_psc_spi_of_probe(struct platform_device *op)
0393 {
0394     const u32 *regaddr_p;
0395     u64 regaddr64, size64;
0396     s16 id = -1;
0397
0398     regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
0399     if (!regaddr_p) {
0400         dev_err(&op->dev, "Invalid PSC address\n");
0401         return -EINVAL;
0402     }
0403     regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
0404
0405     /* get PSC id (1..6, used by port_config) */
0406     if (op->dev.platform_data == NULL) {
0407         const u32 *psc_nump;
0408
0409         psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL);
0410         if (!psc_nump || *psc_nump > 5) {
0411             dev_err(&op->dev, "Invalid cell-index property\n");
0412             return -EINVAL;
0413         }
0414         id = *psc_nump + 1;
0415     }
0416
0417     return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
0418                 irq_of_parse_and_map(op->dev.of_node, 0), id);
0419 }
0420
0421 static int mpc52xx_psc_spi_of_remove(struct platform_device *op)
0422 {
0423     struct spi_master *master = spi_master_get(platform_get_drvdata(op));
0424     struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
0425
0426     spi_unregister_master(master);
0427     free_irq(mps->irq, mps);
0428     if (mps->psc)
0429         iounmap(mps->psc);
0430     spi_master_put(master);
0431
0432     return 0;
0433 }
0434
0435 static const struct of_device_id mpc52xx_psc_spi_of_match[] = {
0436     { .compatible = "fsl,mpc5200-psc-spi", },
0437     { .compatible = "mpc5200-psc-spi", }, /* old */
0438     {}
0439 };
0440
0441 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
0442
0443 static struct platform_driver mpc52xx_psc_spi_of_driver = {
0444     .probe = mpc52xx_psc_spi_of_probe,
0445     .remove = mpc52xx_psc_spi_of_remove,
0446     .driver = {
0447         .name = "mpc52xx-psc-spi",
0448         .of_match_table = mpc52xx_psc_spi_of_match,
0449     },
0450 };
0451 module_platform_driver(mpc52xx_psc_spi_of_driver);
0452
0453 MODULE_AUTHOR("Dragos Carp");
0454 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
0455 MODULE_LICENSE("GPL");