drivers/spi/spi-mpc512x-psc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC512x PSC in SPI mode driver.
0004  *
0005  * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
0006  * Original port from 52xx driver:
0007  *  Hongjun Chen <hong-jun.chen@freescale.com>
0008  *
0009  * Fork of mpc52xx_psc_spi.c:
0010  *  Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
0011  */
0012
0013 #include <linux/module.h>
0014 #include <linux/kernel.h>
0015 #include <linux/errno.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/completion.h>
0021 #include <linux/io.h>
0022 #include <linux/delay.h>
0023 #include <linux/clk.h>
0024 #include <linux/spi/spi.h>
0025 #include <linux/fsl_devices.h>
0026 #include <asm/mpc52xx_psc.h>
0027
0028 enum {
0029     TYPE_MPC5121,
0030     TYPE_MPC5125,
0031 };
0032
0033 /*
0034  * This macro abstracts the differences in the PSC register layout between
0035  * MPC5121 (which uses a struct mpc52xx_psc) and MPC5125 (using mpc5125_psc).
0036  */
0037 #define psc_addr(mps, regname) ({                   \
0038     void *__ret = NULL;                     \
0039     switch (mps->type) {                        \
0040     case TYPE_MPC5121: {                        \
0041             struct mpc52xx_psc __iomem *psc = mps->psc; \
0042             __ret = &psc->regname;              \
0043         };                          \
0044         break;                          \
0045     case TYPE_MPC5125: {                        \
0046             struct mpc5125_psc __iomem *psc = mps->psc; \
0047             __ret = &psc->regname;              \
0048         };                          \
0049         break;                          \
0050     }                               \
0051     __ret; })
0052
0053 struct mpc512x_psc_spi {
0054     void (*cs_control)(struct spi_device *spi, bool on);
0055
0056     /* driver internal data */
0057     int type;
0058     void __iomem *psc;
0059     struct mpc512x_psc_fifo __iomem *fifo;
0060     unsigned int irq;
0061     u8 bits_per_word;
0062     struct clk *clk_mclk;
0063     struct clk *clk_ipg;
0064     u32 mclk_rate;
0065
0066     struct completion txisrdone;
0067 };
0068
0069 /* controller state */
0070 struct mpc512x_psc_spi_cs {
0071     int bits_per_word;
0072     int speed_hz;
0073 };
0074
0075 /* set clock freq, clock ramp, bits per work
0076  * if t is NULL then reset the values to the default values
0077  */
0078 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
0079                       struct spi_transfer *t)
0080 {
0081     struct mpc512x_psc_spi_cs *cs = spi->controller_state;
0082
0083     cs->speed_hz = (t && t->speed_hz)
0084         ? t->speed_hz : spi->max_speed_hz;
0085     cs->bits_per_word = (t && t->bits_per_word)
0086         ? t->bits_per_word : spi->bits_per_word;
0087     cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
0088     return 0;
0089 }
0090
0091 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
0092 {
0093     struct mpc512x_psc_spi_cs *cs = spi->controller_state;
0094     struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
0095     u32 sicr;
0096     u32 ccr;
0097     int speed;
0098     u16 bclkdiv;
0099
0100     sicr = in_be32(psc_addr(mps, sicr));
0101
0102     /* Set clock phase and polarity */
0103     if (spi->mode & SPI_CPHA)
0104         sicr |= 0x00001000;
0105     else
0106         sicr &= ~0x00001000;
0107
0108     if (spi->mode & SPI_CPOL)
0109         sicr |= 0x00002000;
0110     else
0111         sicr &= ~0x00002000;
0112
0113     if (spi->mode & SPI_LSB_FIRST)
0114         sicr |= 0x10000000;
0115     else
0116         sicr &= ~0x10000000;
0117     out_be32(psc_addr(mps, sicr), sicr);
0118
0119     ccr = in_be32(psc_addr(mps, ccr));
0120     ccr &= 0xFF000000;
0121     speed = cs->speed_hz;
0122     if (!speed)
0123         speed = 1000000;    /* default 1MHz */
0124     bclkdiv = (mps->mclk_rate / speed) - 1;
0125
0126     ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
0127     out_be32(psc_addr(mps, ccr), ccr);
0128     mps->bits_per_word = cs->bits_per_word;
0129
0130     if (spi->cs_gpiod) {
0131         if (mps->cs_control)
0132             /* boardfile override */
0133             mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
0134         else
0135             /* gpiolib will deal with the inversion */
0136             gpiod_set_value(spi->cs_gpiod, 1);
0137     }
0138 }
0139
0140 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
0141 {
0142     struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
0143
0144     if (spi->cs_gpiod) {
0145         if (mps->cs_control)
0146             /* boardfile override */
0147             mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
0148         else
0149             /* gpiolib will deal with the inversion */
0150             gpiod_set_value(spi->cs_gpiod, 0);
0151     }
0152 }
0153
0154 /* extract and scale size field in txsz or rxsz */
0155 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
0156
0157 #define EOFBYTE 1
0158
0159 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
0160                      struct spi_transfer *t)
0161 {
0162     struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
0163     struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
0164     size_t tx_len = t->len;
0165     size_t rx_len = t->len;
0166     u8 *tx_buf = (u8 *)t->tx_buf;
0167     u8 *rx_buf = (u8 *)t->rx_buf;
0168
0169     if (!tx_buf && !rx_buf && t->len)
0170         return -EINVAL;
0171
0172     while (rx_len || tx_len) {
0173         size_t txcount;
0174         u8 data;
0175         size_t fifosz;
0176         size_t rxcount;
0177         int rxtries;
0178
0179         /*
0180          * send the TX bytes in as large a chunk as possible
0181          * but neither exceed the TX nor the RX FIFOs
0182          */
0183         fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
0184         txcount = min(fifosz, tx_len);
0185         fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
0186         fifosz -= in_be32(&fifo->rxcnt) + 1;
0187         txcount = min(fifosz, txcount);
0188         if (txcount) {
0189
0190             /* fill the TX FIFO */
0191             while (txcount-- > 0) {
0192                 data = tx_buf ? *tx_buf++ : 0;
0193                 if (tx_len == EOFBYTE && t->cs_change)
0194                     setbits32(&fifo->txcmd,
0195                           MPC512x_PSC_FIFO_EOF);
0196                 out_8(&fifo->txdata_8, data);
0197                 tx_len--;
0198             }
0199
0200             /* have the ISR trigger when the TX FIFO is empty */
0201             reinit_completion(&mps->txisrdone);
0202             out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
0203             out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
0204             wait_for_completion(&mps->txisrdone);
0205         }
0206
0207         /*
0208          * consume as much RX data as the FIFO holds, while we
0209          * iterate over the transfer's TX data length
0210          *
0211          * only insist in draining all the remaining RX bytes
0212          * when the TX bytes were exhausted (that's at the very
0213          * end of this transfer, not when still iterating over
0214          * the transfer's chunks)
0215          */
0216         rxtries = 50;
0217         do {
0218
0219             /*
0220              * grab whatever was in the FIFO when we started
0221              * looking, don't bother fetching what was added to
0222              * the FIFO while we read from it -- we'll return
0223              * here eventually and prefer sending out remaining
0224              * TX data
0225              */
0226             fifosz = in_be32(&fifo->rxcnt);
0227             rxcount = min(fifosz, rx_len);
0228             while (rxcount-- > 0) {
0229                 data = in_8(&fifo->rxdata_8);
0230                 if (rx_buf)
0231                     *rx_buf++ = data;
0232                 rx_len--;
0233             }
0234
0235             /*
0236              * come back later if there still is TX data to send,
0237              * bail out of the RX drain loop if all of the TX data
0238              * was sent and all of the RX data was received (i.e.
0239              * when the transmission has completed)
0240              */
0241             if (tx_len)
0242                 break;
0243             if (!rx_len)
0244                 break;
0245
0246             /*
0247              * TX data transmission has completed while RX data
0248              * is still pending -- that's a transient situation
0249              * which depends on wire speed and specific
0250              * hardware implementation details (buffering) yet
0251              * should resolve very quickly
0252              *
0253              * just yield for a moment to not hog the CPU for
0254              * too long when running SPI at low speed
0255              *
0256              * the timeout range is rather arbitrary and tries
0257              * to balance throughput against system load; the
0258              * chosen values result in a minimal timeout of 50
0259              * times 10us and thus work at speeds as low as
0260              * some 20kbps, while the maximum timeout at the
0261              * transfer's end could be 5ms _if_ nothing else
0262              * ticks in the system _and_ RX data still wasn't
0263              * received, which only occurs in situations that
0264              * are exceptional; removing the unpredictability
0265              * of the timeout either decreases throughput
0266              * (longer timeouts), or puts more load on the
0267              * system (fixed short timeouts) or requires the
0268              * use of a timeout API instead of a counter and an
0269              * unknown inner delay
0270              */
0271             usleep_range(10, 100);
0272
0273         } while (--rxtries > 0);
0274         if (!tx_len && rx_len && !rxtries) {
0275             /*
0276              * not enough RX bytes even after several retries
0277              * and the resulting rather long timeout?
0278              */
0279             rxcount = in_be32(&fifo->rxcnt);
0280             dev_warn(&spi->dev,
0281                  "short xfer, missing %zd RX bytes, FIFO level %zd\n",
0282                  rx_len, rxcount);
0283         }
0284
0285         /*
0286          * drain and drop RX data which "should not be there" in
0287          * the first place, for undisturbed transmission this turns
0288          * into a NOP (except for the FIFO level fetch)
0289          */
0290         if (!tx_len && !rx_len) {
0291             while (in_be32(&fifo->rxcnt))
0292                 in_8(&fifo->rxdata_8);
0293         }
0294
0295     }
0296     return 0;
0297 }
0298
0299 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
0300                     struct spi_message *m)
0301 {
0302     struct spi_device *spi;
0303     unsigned cs_change;
0304     int status;
0305     struct spi_transfer *t;
0306
0307     spi = m->spi;
0308     cs_change = 1;
0309     status = 0;
0310     list_for_each_entry(t, &m->transfers, transfer_list) {
0311         status = mpc512x_psc_spi_transfer_setup(spi, t);
0312         if (status < 0)
0313             break;
0314
0315         if (cs_change)
0316             mpc512x_psc_spi_activate_cs(spi);
0317         cs_change = t->cs_change;
0318
0319         status = mpc512x_psc_spi_transfer_rxtx(spi, t);
0320         if (status)
0321             break;
0322         m->actual_length += t->len;
0323
0324         spi_transfer_delay_exec(t);
0325
0326         if (cs_change)
0327             mpc512x_psc_spi_deactivate_cs(spi);
0328     }
0329
0330     m->status = status;
0331     if (m->complete)
0332         m->complete(m->context);
0333
0334     if (status || !cs_change)
0335         mpc512x_psc_spi_deactivate_cs(spi);
0336
0337     mpc512x_psc_spi_transfer_setup(spi, NULL);
0338
0339     spi_finalize_current_message(master);
0340     return status;
0341 }
0342
0343 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
0344 {
0345     struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
0346
0347     dev_dbg(&master->dev, "%s()\n", __func__);
0348
0349     /* Zero MR2 */
0350     in_8(psc_addr(mps, mr2));
0351     out_8(psc_addr(mps, mr2), 0x0);
0352
0353     /* enable transmitter/receiver */
0354     out_8(psc_addr(mps, command), MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
0355
0356     return 0;
0357 }
0358
0359 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
0360 {
0361     struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
0362     struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
0363
0364     dev_dbg(&master->dev, "%s()\n", __func__);
0365
0366     /* disable transmitter/receiver and fifo interrupt */
0367     out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
0368     out_be32(&fifo->tximr, 0);
0369
0370     return 0;
0371 }
0372
0373 static int mpc512x_psc_spi_setup(struct spi_device *spi)
0374 {
0375     struct mpc512x_psc_spi_cs *cs = spi->controller_state;
0376
0377     if (spi->bits_per_word % 8)
0378         return -EINVAL;
0379
0380     if (!cs) {
0381         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
0382         if (!cs)
0383             return -ENOMEM;
0384
0385         spi->controller_state = cs;
0386     }
0387
0388     cs->bits_per_word = spi->bits_per_word;
0389     cs->speed_hz = spi->max_speed_hz;
0390
0391     return 0;
0392 }
0393
0394 static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
0395 {
0396     kfree(spi->controller_state);
0397 }
0398
0399 static int mpc512x_psc_spi_port_config(struct spi_master *master,
0400                        struct mpc512x_psc_spi *mps)
0401 {
0402     struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
0403     u32 sicr;
0404     u32 ccr;
0405     int speed;
0406     u16 bclkdiv;
0407
0408     /* Reset the PSC into a known state */
0409     out_8(psc_addr(mps, command), MPC52xx_PSC_RST_RX);
0410     out_8(psc_addr(mps, command), MPC52xx_PSC_RST_TX);
0411     out_8(psc_addr(mps, command), MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
0412
0413     /* Disable psc interrupts all useful interrupts are in fifo */
0414     out_be16(psc_addr(mps, isr_imr.imr), 0);
0415
0416     /* Disable fifo interrupts, will be enabled later */
0417     out_be32(&fifo->tximr, 0);
0418     out_be32(&fifo->rximr, 0);
0419
0420     /* Setup fifo slice address and size */
0421     /*out_be32(&fifo->txsz, 0x0fe00004);*/
0422     /*out_be32(&fifo->rxsz, 0x0ff00004);*/
0423
0424     sicr =  0x01000000 |    /* SIM = 0001 -- 8 bit */
0425         0x00800000 |    /* GenClk = 1 -- internal clk */
0426         0x00008000 |    /* SPI = 1 */
0427         0x00004000 |    /* MSTR = 1   -- SPI master */
0428         0x00000800; /* UseEOF = 1 -- SS low until EOF */
0429
0430     out_be32(psc_addr(mps, sicr), sicr);
0431
0432     ccr = in_be32(psc_addr(mps, ccr));
0433     ccr &= 0xFF000000;
0434     speed = 1000000;    /* default 1MHz */
0435     bclkdiv = (mps->mclk_rate / speed) - 1;
0436     ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
0437     out_be32(psc_addr(mps, ccr), ccr);
0438
0439     /* Set 2ms DTL delay */
0440     out_8(psc_addr(mps, ctur), 0x00);
0441     out_8(psc_addr(mps, ctlr), 0x82);
0442
0443     /* we don't use the alarms */
0444     out_be32(&fifo->rxalarm, 0xfff);
0445     out_be32(&fifo->txalarm, 0);
0446
0447     /* Enable FIFO slices for Rx/Tx */
0448     out_be32(&fifo->rxcmd,
0449          MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
0450     out_be32(&fifo->txcmd,
0451          MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
0452
0453     mps->bits_per_word = 8;
0454
0455     return 0;
0456 }
0457
0458 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
0459 {
0460     struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
0461     struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
0462
0463     /* clear interrupt and wake up the rx/tx routine */
0464     if (in_be32(&fifo->txisr) &
0465         in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
0466         out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
0467         out_be32(&fifo->tximr, 0);
0468         complete(&mps->txisrdone);
0469         return IRQ_HANDLED;
0470     }
0471     return IRQ_NONE;
0472 }
0473
0474 static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
0475                           u32 size, unsigned int irq)
0476 {
0477     struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0478     struct mpc512x_psc_spi *mps;
0479     struct spi_master *master;
0480     int ret;
0481     void *tempp;
0482     struct clk *clk;
0483
0484     master = spi_alloc_master(dev, sizeof(*mps));
0485     if (master == NULL)
0486         return -ENOMEM;
0487
0488     dev_set_drvdata(dev, master);
0489     mps = spi_master_get_devdata(master);
0490     mps->type = (int)of_device_get_match_data(dev);
0491     mps->irq = irq;
0492
0493     if (pdata) {
0494         mps->cs_control = pdata->cs_control;
0495         master->bus_num = pdata->bus_num;
0496         master->num_chipselect = pdata->max_chipselect;
0497     }
0498
0499     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
0500     master->setup = mpc512x_psc_spi_setup;
0501     master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
0502     master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
0503     master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
0504     master->use_gpio_descriptors = true;
0505     master->cleanup = mpc512x_psc_spi_cleanup;
0506     master->dev.of_node = dev->of_node;
0507
0508     tempp = devm_ioremap(dev, regaddr, size);
0509     if (!tempp) {
0510         dev_err(dev, "could not ioremap I/O port range\n");
0511         ret = -EFAULT;
0512         goto free_master;
0513     }
0514     mps->psc = tempp;
0515     mps->fifo =
0516         (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
0517     ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
0518                 "mpc512x-psc-spi", mps);
0519     if (ret)
0520         goto free_master;
0521     init_completion(&mps->txisrdone);
0522
0523     clk = devm_clk_get(dev, "mclk");
0524     if (IS_ERR(clk)) {
0525         ret = PTR_ERR(clk);
0526         goto free_master;
0527     }
0528     ret = clk_prepare_enable(clk);
0529     if (ret)
0530         goto free_master;
0531     mps->clk_mclk = clk;
0532     mps->mclk_rate = clk_get_rate(clk);
0533
0534     clk = devm_clk_get(dev, "ipg");
0535     if (IS_ERR(clk)) {
0536         ret = PTR_ERR(clk);
0537         goto free_mclk_clock;
0538     }
0539     ret = clk_prepare_enable(clk);
0540     if (ret)
0541         goto free_mclk_clock;
0542     mps->clk_ipg = clk;
0543
0544     ret = mpc512x_psc_spi_port_config(master, mps);
0545     if (ret < 0)
0546         goto free_ipg_clock;
0547
0548     ret = devm_spi_register_master(dev, master);
0549     if (ret < 0)
0550         goto free_ipg_clock;
0551
0552     return ret;
0553
0554 free_ipg_clock:
0555     clk_disable_unprepare(mps->clk_ipg);
0556 free_mclk_clock:
0557     clk_disable_unprepare(mps->clk_mclk);
0558 free_master:
0559     spi_master_put(master);
0560
0561     return ret;
0562 }
0563
0564 static int mpc512x_psc_spi_do_remove(struct device *dev)
0565 {
0566     struct spi_master *master = dev_get_drvdata(dev);
0567     struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
0568
0569     clk_disable_unprepare(mps->clk_mclk);
0570     clk_disable_unprepare(mps->clk_ipg);
0571
0572     return 0;
0573 }
0574
0575 static int mpc512x_psc_spi_of_probe(struct platform_device *op)
0576 {
0577     const u32 *regaddr_p;
0578     u64 regaddr64, size64;
0579
0580     regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
0581     if (!regaddr_p) {
0582         dev_err(&op->dev, "Invalid PSC address\n");
0583         return -EINVAL;
0584     }
0585     regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
0586
0587     return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
0588                 irq_of_parse_and_map(op->dev.of_node, 0));
0589 }
0590
0591 static int mpc512x_psc_spi_of_remove(struct platform_device *op)
0592 {
0593     return mpc512x_psc_spi_do_remove(&op->dev);
0594 }
0595
0596 static const struct of_device_id mpc512x_psc_spi_of_match[] = {
0597     { .compatible = "fsl,mpc5121-psc-spi", .data = (void *)TYPE_MPC5121 },
0598     { .compatible = "fsl,mpc5125-psc-spi", .data = (void *)TYPE_MPC5125 },
0599     {},
0600 };
0601
0602 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
0603
0604 static struct platform_driver mpc512x_psc_spi_of_driver = {
0605     .probe = mpc512x_psc_spi_of_probe,
0606     .remove = mpc512x_psc_spi_of_remove,
0607     .driver = {
0608         .name = "mpc512x-psc-spi",
0609         .of_match_table = mpc512x_psc_spi_of_match,
0610     },
0611 };
0612 module_platform_driver(mpc512x_psc_spi_of_driver);
0613
0614 MODULE_AUTHOR("John Rigby");
0615 MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
0616 MODULE_LICENSE("GPL");