drivers/spi/spi-meson-spicc.c

0001 /*
0002  * Driver for Amlogic Meson SPI communication controller (SPICC)
0003  *
0004  * Copyright (C) BayLibre, SAS
0005  * Author: Neil Armstrong <narmstrong@baylibre.com>
0006  *
0007  * SPDX-License-Identifier: GPL-2.0+
0008  */
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/device.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/spi/spi.h>
0021 #include <linux/types.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/reset.h>
0024
0025 /*
0026  * The Meson SPICC controller could support DMA based transfers, but is not
0027  * implemented by the vendor code, and while having the registers documentation
0028  * it has never worked on the GXL Hardware.
0029  * The PIO mode is the only mode implemented, and due to badly designed HW :
0030  * - all transfers are cutted in 16 words burst because the FIFO hangs on
0031  *   TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
0032  *   FIFO max size chunk only
0033  * - CS management is dumb, and goes UP between every burst, so is really a
0034  *   "Data Valid" signal than a Chip Select, GPIO link should be used instead
0035  *   to have a CS go down over the full transfer
0036  */
0037
0038 #define SPICC_MAX_BURST 128
0039
0040 /* Register Map */
0041 #define SPICC_RXDATA    0x00
0042
0043 #define SPICC_TXDATA    0x04
0044
0045 #define SPICC_CONREG    0x08
0046 #define SPICC_ENABLE        BIT(0)
0047 #define SPICC_MODE_MASTER   BIT(1)
0048 #define SPICC_XCH       BIT(2)
0049 #define SPICC_SMC       BIT(3)
0050 #define SPICC_POL       BIT(4)
0051 #define SPICC_PHA       BIT(5)
0052 #define SPICC_SSCTL     BIT(6)
0053 #define SPICC_SSPOL     BIT(7)
0054 #define SPICC_DRCTL_MASK    GENMASK(9, 8)
0055 #define SPICC_DRCTL_IGNORE  0
0056 #define SPICC_DRCTL_FALLING 1
0057 #define SPICC_DRCTL_LOWLEVEL    2
0058 #define SPICC_CS_MASK       GENMASK(13, 12)
0059 #define SPICC_DATARATE_MASK GENMASK(18, 16)
0060 #define SPICC_DATARATE_DIV4 0
0061 #define SPICC_DATARATE_DIV8 1
0062 #define SPICC_DATARATE_DIV16    2
0063 #define SPICC_DATARATE_DIV32    3
0064 #define SPICC_BITLENGTH_MASK    GENMASK(24, 19)
0065 #define SPICC_BURSTLENGTH_MASK  GENMASK(31, 25)
0066
0067 #define SPICC_INTREG    0x0c
0068 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
0069 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
0070 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
0071 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
0072 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
0073 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
0074 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
0075 #define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */
0076
0077 #define SPICC_DMAREG    0x10
0078 #define SPICC_DMA_ENABLE        BIT(0)
0079 #define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)
0080 #define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)
0081 #define SPICC_READ_BURST_MASK       GENMASK(14, 11)
0082 #define SPICC_WRITE_BURST_MASK      GENMASK(18, 15)
0083 #define SPICC_DMA_URGENT        BIT(19)
0084 #define SPICC_DMA_THREADID_MASK     GENMASK(25, 20)
0085 #define SPICC_DMA_BURSTNUM_MASK     GENMASK(31, 26)
0086
0087 #define SPICC_STATREG   0x14
0088 #define SPICC_TE    BIT(0) /* TX FIFO Empty Interrupt */
0089 #define SPICC_TH    BIT(1) /* TX FIFO Half-Full Interrupt */
0090 #define SPICC_TF    BIT(2) /* TX FIFO Full Interrupt */
0091 #define SPICC_RR    BIT(3) /* RX FIFO Ready Interrupt */
0092 #define SPICC_RH    BIT(4) /* RX FIFO Half-Full Interrupt */
0093 #define SPICC_RF    BIT(5) /* RX FIFO Full Interrupt */
0094 #define SPICC_RO    BIT(6) /* RX FIFO Overflow Interrupt */
0095 #define SPICC_TC    BIT(7) /* Transfert Complete Interrupt */
0096
0097 #define SPICC_PERIODREG 0x18
0098 #define SPICC_PERIOD    GENMASK(14, 0)  /* Wait cycles */
0099
0100 #define SPICC_TESTREG   0x1c
0101 #define SPICC_TXCNT_MASK    GENMASK(4, 0)   /* TX FIFO Counter */
0102 #define SPICC_RXCNT_MASK    GENMASK(9, 5)   /* RX FIFO Counter */
0103 #define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */
0104 #define SPICC_LBC_RO        BIT(13) /* Loop Back Control Read-Only */
0105 #define SPICC_LBC_W1        BIT(14) /* Loop Back Control Write-Only */
0106 #define SPICC_SWAP_RO       BIT(14) /* RX FIFO Data Swap Read-Only */
0107 #define SPICC_SWAP_W1       BIT(15) /* RX FIFO Data Swap Write-Only */
0108 #define SPICC_DLYCTL_RO_MASK    GENMASK(20, 15) /* Delay Control Read-Only */
0109 #define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */
0110 #define SPICC_MO_NO_DELAY   0
0111 #define SPICC_MO_DELAY_1_CYCLE  1
0112 #define SPICC_MO_DELAY_2_CYCLE  2
0113 #define SPICC_MO_DELAY_3_CYCLE  3
0114 #define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */
0115 #define SPICC_MI_NO_DELAY   0
0116 #define SPICC_MI_DELAY_1_CYCLE  1
0117 #define SPICC_MI_DELAY_2_CYCLE  2
0118 #define SPICC_MI_DELAY_3_CYCLE  3
0119 #define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */
0120 #define SPICC_CAP_AHEAD_2_CYCLE 0
0121 #define SPICC_CAP_AHEAD_1_CYCLE 1
0122 #define SPICC_CAP_NO_DELAY  2
0123 #define SPICC_CAP_DELAY_1_CYCLE 3
0124 #define SPICC_FIFORST_RO_MASK   GENMASK(22, 21) /* FIFO Softreset Read-Only */
0125 #define SPICC_FIFORST_W1_MASK   GENMASK(23, 22) /* FIFO Softreset Write-Only */
0126
0127 #define SPICC_DRADDR    0x20    /* Read Address of DMA */
0128
0129 #define SPICC_DWADDR    0x24    /* Write Address of DMA */
0130
0131 #define SPICC_ENH_CTL0  0x38    /* Enhanced Feature */
0132 #define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)
0133 #define SPICC_ENH_DATARATE_MASK     GENMASK(23, 16)
0134 #define SPICC_ENH_DATARATE_EN       BIT(24)
0135 #define SPICC_ENH_MOSI_OEN      BIT(25)
0136 #define SPICC_ENH_CLK_OEN       BIT(26)
0137 #define SPICC_ENH_CS_OEN        BIT(27)
0138 #define SPICC_ENH_CLK_CS_DELAY_EN   BIT(28)
0139 #define SPICC_ENH_MAIN_CLK_AO       BIT(29)
0140
0141 #define writel_bits_relaxed(mask, val, addr) \
0142     writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
0143
0144 struct meson_spicc_data {
0145     unsigned int            max_speed_hz;
0146     unsigned int            min_speed_hz;
0147     unsigned int            fifo_size;
0148     bool                has_oen;
0149     bool                has_enhance_clk_div;
0150     bool                has_pclk;
0151 };
0152
0153 struct meson_spicc_device {
0154     struct spi_master       *master;
0155     struct platform_device      *pdev;
0156     void __iomem            *base;
0157     struct clk          *core;
0158     struct clk          *pclk;
0159     struct clk_divider      pow2_div;
0160     struct clk          *clk;
0161     struct spi_message      *message;
0162     struct spi_transfer     *xfer;
0163     const struct meson_spicc_data   *data;
0164     u8              *tx_buf;
0165     u8              *rx_buf;
0166     unsigned int            bytes_per_word;
0167     unsigned long           tx_remain;
0168     unsigned long           rx_remain;
0169     unsigned long           xfer_remain;
0170 };
0171
0172 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)
0173
0174 static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
0175 {
0176     u32 conf;
0177
0178     if (!spicc->data->has_oen)
0179         return;
0180
0181     conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
0182         SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
0183
0184     writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
0185 }
0186
0187 static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
0188 {
0189     return !!FIELD_GET(SPICC_TF,
0190                readl_relaxed(spicc->base + SPICC_STATREG));
0191 }
0192
0193 static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)
0194 {
0195     return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,
0196              readl_relaxed(spicc->base + SPICC_STATREG));
0197 }
0198
0199 static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)
0200 {
0201     unsigned int bytes = spicc->bytes_per_word;
0202     unsigned int byte_shift = 0;
0203     u32 data = 0;
0204     u8 byte;
0205
0206     while (bytes--) {
0207         byte = *spicc->tx_buf++;
0208         data |= (byte & 0xff) << byte_shift;
0209         byte_shift += 8;
0210     }
0211
0212     spicc->tx_remain--;
0213     return data;
0214 }
0215
0216 static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,
0217                      u32 data)
0218 {
0219     unsigned int bytes = spicc->bytes_per_word;
0220     unsigned int byte_shift = 0;
0221     u8 byte;
0222
0223     while (bytes--) {
0224         byte = (data >> byte_shift) & 0xff;
0225         *spicc->rx_buf++ = byte;
0226         byte_shift += 8;
0227     }
0228
0229     spicc->rx_remain--;
0230 }
0231
0232 static inline void meson_spicc_rx(struct meson_spicc_device *spicc)
0233 {
0234     /* Empty RX FIFO */
0235     while (spicc->rx_remain &&
0236            meson_spicc_rxready(spicc))
0237         meson_spicc_push_data(spicc,
0238                 readl_relaxed(spicc->base + SPICC_RXDATA));
0239 }
0240
0241 static inline void meson_spicc_tx(struct meson_spicc_device *spicc)
0242 {
0243     /* Fill Up TX FIFO */
0244     while (spicc->tx_remain &&
0245            !meson_spicc_txfull(spicc))
0246         writel_relaxed(meson_spicc_pull_data(spicc),
0247                    spicc->base + SPICC_TXDATA);
0248 }
0249
0250 static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)
0251 {
0252
0253     unsigned int burst_len = min_t(unsigned int,
0254                        spicc->xfer_remain /
0255                        spicc->bytes_per_word,
0256                        spicc->data->fifo_size);
0257     /* Setup Xfer variables */
0258     spicc->tx_remain = burst_len;
0259     spicc->rx_remain = burst_len;
0260     spicc->xfer_remain -= burst_len * spicc->bytes_per_word;
0261
0262     /* Setup burst length */
0263     writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,
0264             FIELD_PREP(SPICC_BURSTLENGTH_MASK,
0265                 burst_len - 1),
0266             spicc->base + SPICC_CONREG);
0267
0268     /* Fill TX FIFO */
0269     meson_spicc_tx(spicc);
0270 }
0271
0272 static irqreturn_t meson_spicc_irq(int irq, void *data)
0273 {
0274     struct meson_spicc_device *spicc = (void *) data;
0275
0276     writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);
0277
0278     /* Empty RX FIFO */
0279     meson_spicc_rx(spicc);
0280
0281     if (!spicc->xfer_remain) {
0282         /* Disable all IRQs */
0283         writel(0, spicc->base + SPICC_INTREG);
0284
0285         spi_finalize_current_transfer(spicc->master);
0286
0287         return IRQ_HANDLED;
0288     }
0289
0290     /* Setup burst */
0291     meson_spicc_setup_burst(spicc);
0292
0293     /* Start burst */
0294     writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
0295
0296     return IRQ_HANDLED;
0297 }
0298
0299 static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)
0300 {
0301     u32 div, hz;
0302     u32 mi_delay, cap_delay;
0303     u32 conf;
0304
0305     if (spicc->data->has_enhance_clk_div) {
0306         div = FIELD_GET(SPICC_ENH_DATARATE_MASK,
0307                 readl_relaxed(spicc->base + SPICC_ENH_CTL0));
0308         div++;
0309         div <<= 1;
0310     } else {
0311         div = FIELD_GET(SPICC_DATARATE_MASK,
0312                 readl_relaxed(spicc->base + SPICC_CONREG));
0313         div += 2;
0314         div = 1 << div;
0315     }
0316
0317     mi_delay = SPICC_MI_NO_DELAY;
0318     cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
0319     hz = clk_get_rate(spicc->clk);
0320
0321     if (hz >= 100000000)
0322         cap_delay = SPICC_CAP_DELAY_1_CYCLE;
0323     else if (hz >= 80000000)
0324         cap_delay = SPICC_CAP_NO_DELAY;
0325     else if (hz >= 40000000)
0326         cap_delay = SPICC_CAP_AHEAD_1_CYCLE;
0327     else if (div >= 16)
0328         mi_delay = SPICC_MI_DELAY_3_CYCLE;
0329     else if (div >= 8)
0330         mi_delay = SPICC_MI_DELAY_2_CYCLE;
0331     else if (div >= 6)
0332         mi_delay = SPICC_MI_DELAY_1_CYCLE;
0333
0334     conf = readl_relaxed(spicc->base + SPICC_TESTREG);
0335     conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK
0336           | SPICC_MI_CAP_DELAY_MASK);
0337     conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);
0338     conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);
0339     writel_relaxed(conf, spicc->base + SPICC_TESTREG);
0340 }
0341
0342 static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,
0343                    struct spi_transfer *xfer)
0344 {
0345     u32 conf, conf_orig;
0346
0347     /* Read original configuration */
0348     conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);
0349
0350     /* Setup word width */
0351     conf &= ~SPICC_BITLENGTH_MASK;
0352     conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,
0353                (spicc->bytes_per_word << 3) - 1);
0354
0355     /* Ignore if unchanged */
0356     if (conf != conf_orig)
0357         writel_relaxed(conf, spicc->base + SPICC_CONREG);
0358
0359     clk_set_rate(spicc->clk, xfer->speed_hz);
0360
0361     meson_spicc_auto_io_delay(spicc);
0362
0363     writel_relaxed(0, spicc->base + SPICC_DMAREG);
0364 }
0365
0366 static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)
0367 {
0368     if (spicc->data->has_oen)
0369         writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,
0370                     SPICC_ENH_MAIN_CLK_AO,
0371                     spicc->base + SPICC_ENH_CTL0);
0372
0373     writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,
0374                 spicc->base + SPICC_TESTREG);
0375
0376     while (meson_spicc_rxready(spicc))
0377         readl_relaxed(spicc->base + SPICC_RXDATA);
0378
0379     if (spicc->data->has_oen)
0380         writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,
0381                     spicc->base + SPICC_ENH_CTL0);
0382 }
0383
0384 static int meson_spicc_transfer_one(struct spi_master *master,
0385                     struct spi_device *spi,
0386                     struct spi_transfer *xfer)
0387 {
0388     struct meson_spicc_device *spicc = spi_master_get_devdata(master);
0389
0390     /* Store current transfer */
0391     spicc->xfer = xfer;
0392
0393     /* Setup transfer parameters */
0394     spicc->tx_buf = (u8 *)xfer->tx_buf;
0395     spicc->rx_buf = (u8 *)xfer->rx_buf;
0396     spicc->xfer_remain = xfer->len;
0397
0398     /* Pre-calculate word size */
0399     spicc->bytes_per_word =
0400        DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);
0401
0402     if (xfer->len % spicc->bytes_per_word)
0403         return -EINVAL;
0404
0405     /* Setup transfer parameters */
0406     meson_spicc_setup_xfer(spicc, xfer);
0407
0408     meson_spicc_reset_fifo(spicc);
0409
0410     /* Setup burst */
0411     meson_spicc_setup_burst(spicc);
0412
0413     /* Start burst */
0414     writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);
0415
0416     /* Enable interrupts */
0417     writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);
0418
0419     return 1;
0420 }
0421
0422 static int meson_spicc_prepare_message(struct spi_master *master,
0423                        struct spi_message *message)
0424 {
0425     struct meson_spicc_device *spicc = spi_master_get_devdata(master);
0426     struct spi_device *spi = message->spi;
0427     u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
0428
0429     /* Store current message */
0430     spicc->message = message;
0431
0432     /* Enable Master */
0433     conf |= SPICC_ENABLE;
0434     conf |= SPICC_MODE_MASTER;
0435
0436     /* SMC = 0 */
0437
0438     /* Setup transfer mode */
0439     if (spi->mode & SPI_CPOL)
0440         conf |= SPICC_POL;
0441     else
0442         conf &= ~SPICC_POL;
0443
0444     if (spi->mode & SPI_CPHA)
0445         conf |= SPICC_PHA;
0446     else
0447         conf &= ~SPICC_PHA;
0448
0449     /* SSCTL = 0 */
0450
0451     if (spi->mode & SPI_CS_HIGH)
0452         conf |= SPICC_SSPOL;
0453     else
0454         conf &= ~SPICC_SSPOL;
0455
0456     if (spi->mode & SPI_READY)
0457         conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);
0458     else
0459         conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);
0460
0461     /* Select CS */
0462     conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select);
0463
0464     /* Default 8bit word */
0465     conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);
0466
0467     writel_relaxed(conf, spicc->base + SPICC_CONREG);
0468
0469     /* Setup no wait cycles by default */
0470     writel_relaxed(0, spicc->base + SPICC_PERIODREG);
0471
0472     writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG);
0473
0474     return 0;
0475 }
0476
0477 static int meson_spicc_unprepare_transfer(struct spi_master *master)
0478 {
0479     struct meson_spicc_device *spicc = spi_master_get_devdata(master);
0480     u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;
0481
0482     /* Disable all IRQs */
0483     writel(0, spicc->base + SPICC_INTREG);
0484
0485     device_reset_optional(&spicc->pdev->dev);
0486
0487     /* Set default configuration, keeping datarate field */
0488     writel_relaxed(conf, spicc->base + SPICC_CONREG);
0489
0490     return 0;
0491 }
0492
0493 static int meson_spicc_setup(struct spi_device *spi)
0494 {
0495     if (!spi->controller_state)
0496         spi->controller_state = spi_master_get_devdata(spi->master);
0497
0498     return 0;
0499 }
0500
0501 static void meson_spicc_cleanup(struct spi_device *spi)
0502 {
0503     spi->controller_state = NULL;
0504 }
0505
0506 /*
0507  * The Clock Mux
0508  *            x-----------------x   x------------x    x------\
0509  *        |---| pow2 fixed div  |---| pow2 div   |----|      |
0510  *        |   x-----------------x   x------------x    |      |
0511  * src ---|                                           | mux  |-- out
0512  *        |   x-----------------x   x------------x    |      |
0513  *        |---| enh fixed div   |---| enh div    |0---|      |
0514  *            x-----------------x   x------------x    x------/
0515  *
0516  * Clk path for GX series:
0517  *    src -> pow2 fixed div -> pow2 div -> out
0518  *
0519  * Clk path for AXG series:
0520  *    src -> pow2 fixed div -> pow2 div -> mux -> out
0521  *    src -> enh fixed div -> enh div -> mux -> out
0522  *
0523  * Clk path for G12A series:
0524  *    pclk -> pow2 fixed div -> pow2 div -> mux -> out
0525  *    pclk -> enh fixed div -> enh div -> mux -> out
0526  *
0527  * The pow2 divider is tied to the controller HW state, and the
0528  * divider is only valid when the controller is initialized.
0529  *
0530  * A set of clock ops is added to make sure we don't read/set this
0531  * clock rate while the controller is in an unknown state.
0532  */
0533
0534 static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,
0535                           unsigned long parent_rate)
0536 {
0537     struct clk_divider *divider = to_clk_divider(hw);
0538     struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
0539
0540     if (!spicc->master->cur_msg || !spicc->master->busy)
0541         return 0;
0542
0543     return clk_divider_ops.recalc_rate(hw, parent_rate);
0544 }
0545
0546 static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,
0547                        struct clk_rate_request *req)
0548 {
0549     struct clk_divider *divider = to_clk_divider(hw);
0550     struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
0551
0552     if (!spicc->master->cur_msg || !spicc->master->busy)
0553         return -EINVAL;
0554
0555     return clk_divider_ops.determine_rate(hw, req);
0556 }
0557
0558 static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,
0559                      unsigned long parent_rate)
0560 {
0561     struct clk_divider *divider = to_clk_divider(hw);
0562     struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
0563
0564     if (!spicc->master->cur_msg || !spicc->master->busy)
0565         return -EINVAL;
0566
0567     return clk_divider_ops.set_rate(hw, rate, parent_rate);
0568 }
0569
0570 const struct clk_ops meson_spicc_pow2_clk_ops = {
0571     .recalc_rate = meson_spicc_pow2_recalc_rate,
0572     .determine_rate = meson_spicc_pow2_determine_rate,
0573     .set_rate = meson_spicc_pow2_set_rate,
0574 };
0575
0576 static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)
0577 {
0578     struct device *dev = &spicc->pdev->dev;
0579     struct clk_fixed_factor *pow2_fixed_div;
0580     struct clk_init_data init;
0581     struct clk *clk;
0582     struct clk_parent_data parent_data[2];
0583     char name[64];
0584
0585     memset(&init, 0, sizeof(init));
0586     memset(&parent_data, 0, sizeof(parent_data));
0587
0588     init.parent_data = parent_data;
0589
0590     /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */
0591
0592     pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);
0593     if (!pow2_fixed_div)
0594         return -ENOMEM;
0595
0596     snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));
0597     init.name = name;
0598     init.ops = &clk_fixed_factor_ops;
0599     init.flags = 0;
0600     if (spicc->data->has_pclk)
0601         parent_data[0].hw = __clk_get_hw(spicc->pclk);
0602     else
0603         parent_data[0].hw = __clk_get_hw(spicc->core);
0604     init.num_parents = 1;
0605
0606     pow2_fixed_div->mult = 1,
0607     pow2_fixed_div->div = 4,
0608     pow2_fixed_div->hw.init = &init;
0609
0610     clk = devm_clk_register(dev, &pow2_fixed_div->hw);
0611     if (WARN_ON(IS_ERR(clk)))
0612         return PTR_ERR(clk);
0613
0614     snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));
0615     init.name = name;
0616     init.ops = &meson_spicc_pow2_clk_ops;
0617     /*
0618      * Set NOCACHE here to make sure we read the actual HW value
0619      * since we reset the HW after each transfer.
0620      */
0621     init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
0622     parent_data[0].hw = &pow2_fixed_div->hw;
0623     init.num_parents = 1;
0624
0625     spicc->pow2_div.shift = 16,
0626     spicc->pow2_div.width = 3,
0627     spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO,
0628     spicc->pow2_div.reg = spicc->base + SPICC_CONREG;
0629     spicc->pow2_div.hw.init = &init;
0630
0631     spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);
0632     if (WARN_ON(IS_ERR(spicc->clk)))
0633         return PTR_ERR(spicc->clk);
0634
0635     return 0;
0636 }
0637
0638 static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)
0639 {
0640     struct device *dev = &spicc->pdev->dev;
0641     struct clk_fixed_factor *enh_fixed_div;
0642     struct clk_divider *enh_div;
0643     struct clk_mux *mux;
0644     struct clk_init_data init;
0645     struct clk *clk;
0646     struct clk_parent_data parent_data[2];
0647     char name[64];
0648
0649     memset(&init, 0, sizeof(init));
0650     memset(&parent_data, 0, sizeof(parent_data));
0651
0652     init.parent_data = parent_data;
0653
0654     /* algorithm for enh div: rate = freq / 2 / (N + 1) */
0655
0656     enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);
0657     if (!enh_fixed_div)
0658         return -ENOMEM;
0659
0660     snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));
0661     init.name = name;
0662     init.ops = &clk_fixed_factor_ops;
0663     init.flags = 0;
0664     if (spicc->data->has_pclk)
0665         parent_data[0].hw = __clk_get_hw(spicc->pclk);
0666     else
0667         parent_data[0].hw = __clk_get_hw(spicc->core);
0668     init.num_parents = 1;
0669
0670     enh_fixed_div->mult = 1,
0671     enh_fixed_div->div = 2,
0672     enh_fixed_div->hw.init = &init;
0673
0674     clk = devm_clk_register(dev, &enh_fixed_div->hw);
0675     if (WARN_ON(IS_ERR(clk)))
0676         return PTR_ERR(clk);
0677
0678     enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);
0679     if (!enh_div)
0680         return -ENOMEM;
0681
0682     snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));
0683     init.name = name;
0684     init.ops = &clk_divider_ops;
0685     init.flags = CLK_SET_RATE_PARENT;
0686     parent_data[0].hw = &enh_fixed_div->hw;
0687     init.num_parents = 1;
0688
0689     enh_div->shift  = 16,
0690     enh_div->width  = 8,
0691     enh_div->reg = spicc->base + SPICC_ENH_CTL0;
0692     enh_div->hw.init = &init;
0693
0694     clk = devm_clk_register(dev, &enh_div->hw);
0695     if (WARN_ON(IS_ERR(clk)))
0696         return PTR_ERR(clk);
0697
0698     mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
0699     if (!mux)
0700         return -ENOMEM;
0701
0702     snprintf(name, sizeof(name), "%s#sel", dev_name(dev));
0703     init.name = name;
0704     init.ops = &clk_mux_ops;
0705     parent_data[0].hw = &spicc->pow2_div.hw;
0706     parent_data[1].hw = &enh_div->hw;
0707     init.num_parents = 2;
0708     init.flags = CLK_SET_RATE_PARENT;
0709
0710     mux->mask = 0x1,
0711     mux->shift = 24,
0712     mux->reg = spicc->base + SPICC_ENH_CTL0;
0713     mux->hw.init = &init;
0714
0715     spicc->clk = devm_clk_register(dev, &mux->hw);
0716     if (WARN_ON(IS_ERR(spicc->clk)))
0717         return PTR_ERR(spicc->clk);
0718
0719     return 0;
0720 }
0721
0722 static int meson_spicc_probe(struct platform_device *pdev)
0723 {
0724     struct spi_master *master;
0725     struct meson_spicc_device *spicc;
0726     int ret, irq;
0727
0728     master = spi_alloc_master(&pdev->dev, sizeof(*spicc));
0729     if (!master) {
0730         dev_err(&pdev->dev, "master allocation failed\n");
0731         return -ENOMEM;
0732     }
0733     spicc = spi_master_get_devdata(master);
0734     spicc->master = master;
0735
0736     spicc->data = of_device_get_match_data(&pdev->dev);
0737     if (!spicc->data) {
0738         dev_err(&pdev->dev, "failed to get match data\n");
0739         ret = -EINVAL;
0740         goto out_master;
0741     }
0742
0743     spicc->pdev = pdev;
0744     platform_set_drvdata(pdev, spicc);
0745
0746     spicc->base = devm_platform_ioremap_resource(pdev, 0);
0747     if (IS_ERR(spicc->base)) {
0748         dev_err(&pdev->dev, "io resource mapping failed\n");
0749         ret = PTR_ERR(spicc->base);
0750         goto out_master;
0751     }
0752
0753     /* Set master mode and enable controller */
0754     writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,
0755                spicc->base + SPICC_CONREG);
0756
0757     /* Disable all IRQs */
0758     writel_relaxed(0, spicc->base + SPICC_INTREG);
0759
0760     irq = platform_get_irq(pdev, 0);
0761     if (irq < 0) {
0762         ret = irq;
0763         goto out_master;
0764     }
0765
0766     ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,
0767                    0, NULL, spicc);
0768     if (ret) {
0769         dev_err(&pdev->dev, "irq request failed\n");
0770         goto out_master;
0771     }
0772
0773     spicc->core = devm_clk_get(&pdev->dev, "core");
0774     if (IS_ERR(spicc->core)) {
0775         dev_err(&pdev->dev, "core clock request failed\n");
0776         ret = PTR_ERR(spicc->core);
0777         goto out_master;
0778     }
0779
0780     if (spicc->data->has_pclk) {
0781         spicc->pclk = devm_clk_get(&pdev->dev, "pclk");
0782         if (IS_ERR(spicc->pclk)) {
0783             dev_err(&pdev->dev, "pclk clock request failed\n");
0784             ret = PTR_ERR(spicc->pclk);
0785             goto out_master;
0786         }
0787     }
0788
0789     ret = clk_prepare_enable(spicc->core);
0790     if (ret) {
0791         dev_err(&pdev->dev, "core clock enable failed\n");
0792         goto out_master;
0793     }
0794
0795     ret = clk_prepare_enable(spicc->pclk);
0796     if (ret) {
0797         dev_err(&pdev->dev, "pclk clock enable failed\n");
0798         goto out_core_clk;
0799     }
0800
0801     device_reset_optional(&pdev->dev);
0802
0803     master->num_chipselect = 4;
0804     master->dev.of_node = pdev->dev.of_node;
0805     master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH;
0806     master->bits_per_word_mask = SPI_BPW_MASK(32) |
0807                      SPI_BPW_MASK(24) |
0808                      SPI_BPW_MASK(16) |
0809                      SPI_BPW_MASK(8);
0810     master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
0811     master->min_speed_hz = spicc->data->min_speed_hz;
0812     master->max_speed_hz = spicc->data->max_speed_hz;
0813     master->setup = meson_spicc_setup;
0814     master->cleanup = meson_spicc_cleanup;
0815     master->prepare_message = meson_spicc_prepare_message;
0816     master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;
0817     master->transfer_one = meson_spicc_transfer_one;
0818     master->use_gpio_descriptors = true;
0819
0820     meson_spicc_oen_enable(spicc);
0821
0822     ret = meson_spicc_pow2_clk_init(spicc);
0823     if (ret) {
0824         dev_err(&pdev->dev, "pow2 clock registration failed\n");
0825         goto out_clk;
0826     }
0827
0828     if (spicc->data->has_enhance_clk_div) {
0829         ret = meson_spicc_enh_clk_init(spicc);
0830         if (ret) {
0831             dev_err(&pdev->dev, "clock registration failed\n");
0832             goto out_clk;
0833         }
0834     }
0835
0836     ret = devm_spi_register_master(&pdev->dev, master);
0837     if (ret) {
0838         dev_err(&pdev->dev, "spi master registration failed\n");
0839         goto out_clk;
0840     }
0841
0842     return 0;
0843
0844 out_clk:
0845     clk_disable_unprepare(spicc->pclk);
0846
0847 out_core_clk:
0848     clk_disable_unprepare(spicc->core);
0849
0850 out_master:
0851     spi_master_put(master);
0852
0853     return ret;
0854 }
0855
0856 static int meson_spicc_remove(struct platform_device *pdev)
0857 {
0858     struct meson_spicc_device *spicc = platform_get_drvdata(pdev);
0859
0860     /* Disable SPI */
0861     writel(0, spicc->base + SPICC_CONREG);
0862
0863     clk_disable_unprepare(spicc->core);
0864     clk_disable_unprepare(spicc->pclk);
0865
0866     spi_master_put(spicc->master);
0867
0868     return 0;
0869 }
0870
0871 static const struct meson_spicc_data meson_spicc_gx_data = {
0872     .max_speed_hz       = 30000000,
0873     .min_speed_hz       = 325000,
0874     .fifo_size      = 16,
0875 };
0876
0877 static const struct meson_spicc_data meson_spicc_axg_data = {
0878     .max_speed_hz       = 80000000,
0879     .min_speed_hz       = 325000,
0880     .fifo_size      = 16,
0881     .has_oen        = true,
0882     .has_enhance_clk_div    = true,
0883 };
0884
0885 static const struct meson_spicc_data meson_spicc_g12a_data = {
0886     .max_speed_hz       = 166666666,
0887     .min_speed_hz       = 50000,
0888     .fifo_size      = 15,
0889     .has_oen        = true,
0890     .has_enhance_clk_div    = true,
0891     .has_pclk       = true,
0892 };
0893
0894 static const struct of_device_id meson_spicc_of_match[] = {
0895     {
0896         .compatible = "amlogic,meson-gx-spicc",
0897         .data       = &meson_spicc_gx_data,
0898     },
0899     {
0900         .compatible = "amlogic,meson-axg-spicc",
0901         .data       = &meson_spicc_axg_data,
0902     },
0903     {
0904         .compatible = "amlogic,meson-g12a-spicc",
0905         .data       = &meson_spicc_g12a_data,
0906     },
0907     { /* sentinel */ }
0908 };
0909 MODULE_DEVICE_TABLE(of, meson_spicc_of_match);
0910
0911 static struct platform_driver meson_spicc_driver = {
0912     .probe   = meson_spicc_probe,
0913     .remove  = meson_spicc_remove,
0914     .driver  = {
0915         .name = "meson-spicc",
0916         .of_match_table = of_match_ptr(meson_spicc_of_match),
0917     },
0918 };
0919
0920 module_platform_driver(meson_spicc_driver);
0921
0922 MODULE_DESCRIPTION("Meson SPI Communication Controller driver");
0923 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
0924 MODULE_LICENSE("GPL");