drivers/spi/spi-jcore.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * J-Core SPI controller driver
0004  *
0005  * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
0006  *
0007  * Current version by Rich Felker
0008  * Based loosely on initial version by Oleksandr G Zhadan
0009  *
0010  */
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/errno.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/clk.h>
0018 #include <linux/err.h>
0019 #include <linux/io.h>
0020 #include <linux/of.h>
0021 #include <linux/delay.h>
0022
0023 #define DRV_NAME    "jcore_spi"
0024
0025 #define CTRL_REG    0x0
0026 #define DATA_REG    0x4
0027
0028 #define JCORE_SPI_CTRL_XMIT     0x02
0029 #define JCORE_SPI_STAT_BUSY     0x02
0030 #define JCORE_SPI_CTRL_LOOP     0x08
0031 #define JCORE_SPI_CTRL_CS_BITS      0x15
0032
0033 #define JCORE_SPI_WAIT_RDY_MAX_LOOP 2000000
0034
0035 struct jcore_spi {
0036     struct spi_master *master;
0037     void __iomem *base;
0038     unsigned int cs_reg;
0039     unsigned int speed_reg;
0040     unsigned int speed_hz;
0041     unsigned int clock_freq;
0042 };
0043
0044 static int jcore_spi_wait(void __iomem *ctrl_reg)
0045 {
0046     unsigned timeout = JCORE_SPI_WAIT_RDY_MAX_LOOP;
0047
0048     do {
0049         if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY))
0050             return 0;
0051         cpu_relax();
0052     } while (--timeout);
0053
0054     return -EBUSY;
0055 }
0056
0057 static void jcore_spi_program(struct jcore_spi *hw)
0058 {
0059     void __iomem *ctrl_reg = hw->base + CTRL_REG;
0060
0061     if (jcore_spi_wait(ctrl_reg))
0062         dev_err(hw->master->dev.parent,
0063             "timeout waiting to program ctrl reg.\n");
0064
0065     writel(hw->cs_reg | hw->speed_reg, ctrl_reg);
0066 }
0067
0068 static void jcore_spi_chipsel(struct spi_device *spi, bool value)
0069 {
0070     struct jcore_spi *hw = spi_master_get_devdata(spi->master);
0071     u32 csbit = 1U << (2 * spi->chip_select);
0072
0073     dev_dbg(hw->master->dev.parent, "chipselect %d\n", spi->chip_select);
0074
0075     if (value)
0076         hw->cs_reg |= csbit;
0077     else
0078         hw->cs_reg &= ~csbit;
0079
0080     jcore_spi_program(hw);
0081 }
0082
0083 static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
0084 {
0085     if (speed == hw->speed_hz)
0086         return;
0087     hw->speed_hz = speed;
0088     if (speed >= hw->clock_freq / 2)
0089         hw->speed_reg = 0;
0090     else
0091         hw->speed_reg = ((hw->clock_freq / 2 / speed) - 1) << 27;
0092     jcore_spi_program(hw);
0093     dev_dbg(hw->master->dev.parent, "speed=%d reg=0x%x\n",
0094         speed, hw->speed_reg);
0095 }
0096
0097 static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
0098               struct spi_transfer *t)
0099 {
0100     struct jcore_spi *hw = spi_master_get_devdata(master);
0101
0102     void __iomem *ctrl_reg = hw->base + CTRL_REG;
0103     void __iomem *data_reg = hw->base + DATA_REG;
0104     u32 xmit;
0105
0106     /* data buffers */
0107     const unsigned char *tx;
0108     unsigned char *rx;
0109     unsigned int len;
0110     unsigned int count;
0111
0112     jcore_spi_baudrate(hw, t->speed_hz);
0113
0114     xmit = hw->cs_reg | hw->speed_reg | JCORE_SPI_CTRL_XMIT;
0115     tx = t->tx_buf;
0116     rx = t->rx_buf;
0117     len = t->len;
0118
0119     for (count = 0; count < len; count++) {
0120         if (jcore_spi_wait(ctrl_reg))
0121             break;
0122
0123         writel(tx ? *tx++ : 0, data_reg);
0124         writel(xmit, ctrl_reg);
0125
0126         if (jcore_spi_wait(ctrl_reg))
0127             break;
0128
0129         if (rx)
0130             *rx++ = readl(data_reg);
0131     }
0132
0133     spi_finalize_current_transfer(master);
0134
0135     if (count < len)
0136         return -EREMOTEIO;
0137
0138     return 0;
0139 }
0140
0141 static int jcore_spi_probe(struct platform_device *pdev)
0142 {
0143     struct device_node *node = pdev->dev.of_node;
0144     struct jcore_spi *hw;
0145     struct spi_master *master;
0146     struct resource *res;
0147     u32 clock_freq;
0148     struct clk *clk;
0149     int err = -ENODEV;
0150
0151     master = spi_alloc_master(&pdev->dev, sizeof(struct jcore_spi));
0152     if (!master)
0153         return err;
0154
0155     /* Setup the master state. */
0156     master->num_chipselect = 3;
0157     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
0158     master->transfer_one = jcore_spi_txrx;
0159     master->set_cs = jcore_spi_chipsel;
0160     master->dev.of_node = node;
0161     master->bus_num = pdev->id;
0162
0163     hw = spi_master_get_devdata(master);
0164     hw->master = master;
0165     platform_set_drvdata(pdev, hw);
0166
0167     /* Find and map our resources */
0168     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0169     if (!res)
0170         goto exit_busy;
0171     if (!devm_request_mem_region(&pdev->dev, res->start,
0172                      resource_size(res), pdev->name))
0173         goto exit_busy;
0174     hw->base = devm_ioremap(&pdev->dev, res->start,
0175                     resource_size(res));
0176     if (!hw->base)
0177         goto exit_busy;
0178
0179     /*
0180      * The SPI clock rate controlled via a configurable clock divider
0181      * which is applied to the reference clock. A 50 MHz reference is
0182      * most suitable for obtaining standard SPI clock rates, but some
0183      * designs may have a different reference clock, and the DT must
0184      * make the driver aware so that it can properly program the
0185      * requested rate. If the clock is omitted, 50 MHz is assumed.
0186      */
0187     clock_freq = 50000000;
0188     clk = devm_clk_get(&pdev->dev, "ref_clk");
0189     if (!IS_ERR(clk)) {
0190         if (clk_prepare_enable(clk) == 0) {
0191             clock_freq = clk_get_rate(clk);
0192             clk_disable_unprepare(clk);
0193         } else
0194             dev_warn(&pdev->dev, "could not enable ref_clk\n");
0195     }
0196     hw->clock_freq = clock_freq;
0197
0198     /* Initialize all CS bits to high. */
0199     hw->cs_reg = JCORE_SPI_CTRL_CS_BITS;
0200     jcore_spi_baudrate(hw, 400000);
0201
0202     /* Register our spi controller */
0203     err = devm_spi_register_master(&pdev->dev, master);
0204     if (err)
0205         goto exit;
0206
0207     return 0;
0208
0209 exit_busy:
0210     err = -EBUSY;
0211 exit:
0212     spi_master_put(master);
0213     return err;
0214 }
0215
0216 static const struct of_device_id jcore_spi_of_match[] = {
0217     { .compatible = "jcore,spi2" },
0218     {},
0219 };
0220 MODULE_DEVICE_TABLE(of, jcore_spi_of_match);
0221
0222 static struct platform_driver jcore_spi_driver = {
0223     .probe = jcore_spi_probe,
0224     .driver = {
0225         .name = DRV_NAME,
0226         .of_match_table = jcore_spi_of_match,
0227     },
0228 };
0229
0230 module_platform_driver(jcore_spi_driver);
0231
0232 MODULE_DESCRIPTION("J-Core SPI driver");
0233 MODULE_AUTHOR("Rich Felker <dalias@libc.org>");
0234 MODULE_LICENSE("GPL");
0235 MODULE_ALIAS("platform:" DRV_NAME);