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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SPI bus driver for the Ingenic SoCs
0004  * Copyright (c) 2017-2021 Artur Rojek <contact@artur-rojek.eu>
0005  * Copyright (c) 2017-2021 Paul Cercueil <paul@crapouillou.net>
0006  * Copyright (c) 2022 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/module.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/regmap.h>
0018 #include <linux/spi/spi.h>
0019 
0020 #define REG_SSIDR   0x0
0021 #define REG_SSICR0  0x4
0022 #define REG_SSICR1  0x8
0023 #define REG_SSISR   0xc
0024 #define REG_SSIGR   0x18
0025 
0026 #define REG_SSICR0_TENDIAN_LSB      BIT(19)
0027 #define REG_SSICR0_RENDIAN_LSB      BIT(17)
0028 #define REG_SSICR0_SSIE         BIT(15)
0029 #define REG_SSICR0_LOOP         BIT(10)
0030 #define REG_SSICR0_EACLRUN      BIT(7)
0031 #define REG_SSICR0_FSEL         BIT(6)
0032 #define REG_SSICR0_TFLUSH       BIT(2)
0033 #define REG_SSICR0_RFLUSH       BIT(1)
0034 
0035 #define REG_SSICR1_FRMHL_MASK       (BIT(31) | BIT(30))
0036 #define REG_SSICR1_FRMHL        BIT(30)
0037 #define REG_SSICR1_LFST         BIT(25)
0038 #define REG_SSICR1_UNFIN        BIT(23)
0039 #define REG_SSICR1_PHA          BIT(1)
0040 #define REG_SSICR1_POL          BIT(0)
0041 
0042 #define REG_SSISR_END           BIT(7)
0043 #define REG_SSISR_BUSY          BIT(6)
0044 #define REG_SSISR_TFF           BIT(5)
0045 #define REG_SSISR_RFE           BIT(4)
0046 #define REG_SSISR_RFHF          BIT(2)
0047 #define REG_SSISR_UNDR          BIT(1)
0048 #define REG_SSISR_OVER          BIT(0)
0049 
0050 #define SPI_INGENIC_FIFO_SIZE       128u
0051 
0052 struct jz_soc_info {
0053     u32 bits_per_word_mask;
0054     struct reg_field flen_field;
0055     bool has_trendian;
0056 
0057     unsigned int max_speed_hz;
0058     unsigned int max_native_cs;
0059 };
0060 
0061 struct ingenic_spi {
0062     const struct jz_soc_info *soc_info;
0063     struct clk *clk;
0064     struct resource *mem_res;
0065 
0066     struct regmap *map;
0067     struct regmap_field *flen_field;
0068 };
0069 
0070 static int spi_ingenic_wait(struct ingenic_spi *priv,
0071                 unsigned long mask,
0072                 bool condition)
0073 {
0074     unsigned int val;
0075 
0076     return regmap_read_poll_timeout(priv->map, REG_SSISR, val,
0077                     !!(val & mask) == condition,
0078                     100, 10000);
0079 }
0080 
0081 static void spi_ingenic_set_cs(struct spi_device *spi, bool disable)
0082 {
0083     struct ingenic_spi *priv = spi_controller_get_devdata(spi->controller);
0084 
0085     if (disable) {
0086         regmap_clear_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
0087         regmap_clear_bits(priv->map, REG_SSISR,
0088                   REG_SSISR_UNDR | REG_SSISR_OVER);
0089 
0090         spi_ingenic_wait(priv, REG_SSISR_END, true);
0091     } else {
0092         regmap_set_bits(priv->map, REG_SSICR1, REG_SSICR1_UNFIN);
0093     }
0094 
0095     regmap_set_bits(priv->map, REG_SSICR0,
0096             REG_SSICR0_RFLUSH | REG_SSICR0_TFLUSH);
0097 }
0098 
0099 static void spi_ingenic_prepare_transfer(struct ingenic_spi *priv,
0100                      struct spi_device *spi,
0101                      struct spi_transfer *xfer)
0102 {
0103     unsigned long clk_hz = clk_get_rate(priv->clk);
0104     u32 cdiv, speed_hz = xfer->speed_hz ?: spi->max_speed_hz,
0105         bits_per_word = xfer->bits_per_word ?: spi->bits_per_word;
0106 
0107     cdiv = clk_hz / (speed_hz * 2);
0108     cdiv = clamp(cdiv, 1u, 0x100u) - 1;
0109 
0110     regmap_write(priv->map, REG_SSIGR, cdiv);
0111 
0112     regmap_field_write(priv->flen_field, bits_per_word - 2);
0113 }
0114 
0115 static void spi_ingenic_finalize_transfer(void *controller)
0116 {
0117     spi_finalize_current_transfer(controller);
0118 }
0119 
0120 static struct dma_async_tx_descriptor *
0121 spi_ingenic_prepare_dma(struct spi_controller *ctlr, struct dma_chan *chan,
0122             struct sg_table *sg, enum dma_transfer_direction dir,
0123             unsigned int bits)
0124 {
0125     struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
0126     struct dma_slave_config cfg = {
0127         .direction = dir,
0128         .src_addr = priv->mem_res->start + REG_SSIDR,
0129         .dst_addr = priv->mem_res->start + REG_SSIDR,
0130     };
0131     struct dma_async_tx_descriptor *desc;
0132     dma_cookie_t cookie;
0133     int ret;
0134 
0135     if (bits > 16) {
0136         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0137         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0138         cfg.src_maxburst = cfg.dst_maxburst = 4;
0139     } else if (bits > 8) {
0140         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0141         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0142         cfg.src_maxburst = cfg.dst_maxburst = 2;
0143     } else {
0144         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0145         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0146         cfg.src_maxburst = cfg.dst_maxburst = 1;
0147     }
0148 
0149     ret = dmaengine_slave_config(chan, &cfg);
0150     if (ret)
0151         return ERR_PTR(ret);
0152 
0153     desc = dmaengine_prep_slave_sg(chan, sg->sgl, sg->nents, dir,
0154                        DMA_PREP_INTERRUPT);
0155     if (!desc)
0156         return ERR_PTR(-ENOMEM);
0157 
0158     if (dir == DMA_DEV_TO_MEM) {
0159         desc->callback = spi_ingenic_finalize_transfer;
0160         desc->callback_param = ctlr;
0161     }
0162 
0163     cookie = dmaengine_submit(desc);
0164 
0165     ret = dma_submit_error(cookie);
0166     if (ret) {
0167         dmaengine_desc_free(desc);
0168         return ERR_PTR(ret);
0169     }
0170 
0171     return desc;
0172 }
0173 
0174 static int spi_ingenic_dma_tx(struct spi_controller *ctlr,
0175                   struct spi_transfer *xfer, unsigned int bits)
0176 {
0177     struct dma_async_tx_descriptor *rx_desc, *tx_desc;
0178 
0179     rx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_rx,
0180                       &xfer->rx_sg, DMA_DEV_TO_MEM, bits);
0181     if (IS_ERR(rx_desc))
0182         return PTR_ERR(rx_desc);
0183 
0184     tx_desc = spi_ingenic_prepare_dma(ctlr, ctlr->dma_tx,
0185                       &xfer->tx_sg, DMA_MEM_TO_DEV, bits);
0186     if (IS_ERR(tx_desc)) {
0187         dmaengine_terminate_async(ctlr->dma_rx);
0188         dmaengine_desc_free(rx_desc);
0189         return PTR_ERR(tx_desc);
0190     }
0191 
0192     dma_async_issue_pending(ctlr->dma_rx);
0193     dma_async_issue_pending(ctlr->dma_tx);
0194 
0195     return 1;
0196 }
0197 
0198 #define SPI_INGENIC_TX(x)                           \
0199 static int spi_ingenic_tx##x(struct ingenic_spi *priv,              \
0200                  struct spi_transfer *xfer)             \
0201 {                                       \
0202     unsigned int count = xfer->len / (x / 8);               \
0203     unsigned int prefill = min(count, SPI_INGENIC_FIFO_SIZE);       \
0204     const u##x *tx_buf = xfer->tx_buf;                  \
0205     u##x *rx_buf = xfer->rx_buf;                        \
0206     unsigned int i, val;                            \
0207     int err;                                \
0208                                         \
0209     /* Fill up the TX fifo */                       \
0210     for (i = 0; i < prefill; i++) {                     \
0211         val = tx_buf ? tx_buf[i] : 0;                   \
0212                                         \
0213         regmap_write(priv->map, REG_SSIDR, val);            \
0214     }                                   \
0215                                         \
0216     for (i = 0; i < count; i++) {                       \
0217         err = spi_ingenic_wait(priv, REG_SSISR_RFE, false);     \
0218         if (err)                            \
0219             return err;                     \
0220                                         \
0221         regmap_read(priv->map, REG_SSIDR, &val);            \
0222         if (rx_buf)                         \
0223             rx_buf[i] = val;                    \
0224                                         \
0225         if (i < count - prefill) {                  \
0226             val = tx_buf ? tx_buf[i + prefill] : 0;         \
0227                                         \
0228             regmap_write(priv->map, REG_SSIDR, val);        \
0229         }                               \
0230     }                                   \
0231                                         \
0232     return 0;                               \
0233 }
0234 SPI_INGENIC_TX(8)
0235 SPI_INGENIC_TX(16)
0236 SPI_INGENIC_TX(32)
0237 #undef SPI_INGENIC_TX
0238 
0239 static int spi_ingenic_transfer_one(struct spi_controller *ctlr,
0240                     struct spi_device *spi,
0241                     struct spi_transfer *xfer)
0242 {
0243     struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
0244     unsigned int bits = xfer->bits_per_word ?: spi->bits_per_word;
0245     bool can_dma = ctlr->can_dma && ctlr->can_dma(ctlr, spi, xfer);
0246 
0247     spi_ingenic_prepare_transfer(priv, spi, xfer);
0248 
0249     if (ctlr->cur_msg_mapped && can_dma)
0250         return spi_ingenic_dma_tx(ctlr, xfer, bits);
0251 
0252     if (bits > 16)
0253         return spi_ingenic_tx32(priv, xfer);
0254 
0255     if (bits > 8)
0256         return spi_ingenic_tx16(priv, xfer);
0257 
0258     return spi_ingenic_tx8(priv, xfer);
0259 }
0260 
0261 static int spi_ingenic_prepare_message(struct spi_controller *ctlr,
0262                        struct spi_message *message)
0263 {
0264     struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
0265     struct spi_device *spi = message->spi;
0266     unsigned int cs = REG_SSICR1_FRMHL << spi->chip_select;
0267     unsigned int ssicr0_mask = REG_SSICR0_LOOP | REG_SSICR0_FSEL;
0268     unsigned int ssicr1_mask = REG_SSICR1_PHA | REG_SSICR1_POL | cs;
0269     unsigned int ssicr0 = 0, ssicr1 = 0;
0270 
0271     if (priv->soc_info->has_trendian) {
0272         ssicr0_mask |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
0273 
0274         if (spi->mode & SPI_LSB_FIRST)
0275             ssicr0 |= REG_SSICR0_RENDIAN_LSB | REG_SSICR0_TENDIAN_LSB;
0276     } else {
0277         ssicr1_mask |= REG_SSICR1_LFST;
0278 
0279         if (spi->mode & SPI_LSB_FIRST)
0280             ssicr1 |= REG_SSICR1_LFST;
0281     }
0282 
0283     if (spi->mode & SPI_LOOP)
0284         ssicr0 |= REG_SSICR0_LOOP;
0285     if (spi->chip_select)
0286         ssicr0 |= REG_SSICR0_FSEL;
0287 
0288     if (spi->mode & SPI_CPHA)
0289         ssicr1 |= REG_SSICR1_PHA;
0290     if (spi->mode & SPI_CPOL)
0291         ssicr1 |= REG_SSICR1_POL;
0292     if (spi->mode & SPI_CS_HIGH)
0293         ssicr1 |= cs;
0294 
0295     regmap_update_bits(priv->map, REG_SSICR0, ssicr0_mask, ssicr0);
0296     regmap_update_bits(priv->map, REG_SSICR1, ssicr1_mask, ssicr1);
0297 
0298     return 0;
0299 }
0300 
0301 static int spi_ingenic_prepare_hardware(struct spi_controller *ctlr)
0302 {
0303     struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
0304     int ret;
0305 
0306     ret = clk_prepare_enable(priv->clk);
0307     if (ret)
0308         return ret;
0309 
0310     regmap_write(priv->map, REG_SSICR0, REG_SSICR0_EACLRUN);
0311     regmap_write(priv->map, REG_SSICR1, 0);
0312     regmap_write(priv->map, REG_SSISR, 0);
0313     regmap_set_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
0314 
0315     return 0;
0316 }
0317 
0318 static int spi_ingenic_unprepare_hardware(struct spi_controller *ctlr)
0319 {
0320     struct ingenic_spi *priv = spi_controller_get_devdata(ctlr);
0321 
0322     regmap_clear_bits(priv->map, REG_SSICR0, REG_SSICR0_SSIE);
0323 
0324     clk_disable_unprepare(priv->clk);
0325 
0326     return 0;
0327 }
0328 
0329 static bool spi_ingenic_can_dma(struct spi_controller *ctlr,
0330                 struct spi_device *spi,
0331                 struct spi_transfer *xfer)
0332 {
0333     struct dma_slave_caps caps;
0334     int ret;
0335 
0336     ret = dma_get_slave_caps(ctlr->dma_tx, &caps);
0337     if (ret) {
0338         dev_err(&spi->dev, "Unable to get slave caps: %d\n", ret);
0339         return false;
0340     }
0341 
0342     return !caps.max_sg_burst ||
0343         xfer->len <= caps.max_sg_burst * SPI_INGENIC_FIFO_SIZE;
0344 }
0345 
0346 static int spi_ingenic_request_dma(struct spi_controller *ctlr,
0347                    struct device *dev)
0348 {
0349     ctlr->dma_tx = dma_request_slave_channel(dev, "tx");
0350     if (!ctlr->dma_tx)
0351         return -ENODEV;
0352 
0353     ctlr->dma_rx = dma_request_slave_channel(dev, "rx");
0354 
0355     if (!ctlr->dma_rx)
0356         return -ENODEV;
0357 
0358     ctlr->can_dma = spi_ingenic_can_dma;
0359 
0360     return 0;
0361 }
0362 
0363 static void spi_ingenic_release_dma(void *data)
0364 {
0365     struct spi_controller *ctlr = data;
0366 
0367     if (ctlr->dma_tx)
0368         dma_release_channel(ctlr->dma_tx);
0369     if (ctlr->dma_rx)
0370         dma_release_channel(ctlr->dma_rx);
0371 }
0372 
0373 static const struct regmap_config spi_ingenic_regmap_config = {
0374     .reg_bits = 32,
0375     .val_bits = 32,
0376     .reg_stride = 4,
0377     .max_register = REG_SSIGR,
0378 };
0379 
0380 static int spi_ingenic_probe(struct platform_device *pdev)
0381 {
0382     const struct jz_soc_info *pdata;
0383     struct device *dev = &pdev->dev;
0384     struct spi_controller *ctlr;
0385     struct ingenic_spi *priv;
0386     void __iomem *base;
0387     int num_cs, ret;
0388 
0389     pdata = of_device_get_match_data(dev);
0390     if (!pdata) {
0391         dev_err(dev, "Missing platform data.\n");
0392         return -EINVAL;
0393     }
0394 
0395     ctlr = devm_spi_alloc_master(dev, sizeof(*priv));
0396     if (!ctlr) {
0397         dev_err(dev, "Unable to allocate SPI controller.\n");
0398         return -ENOMEM;
0399     }
0400 
0401     priv = spi_controller_get_devdata(ctlr);
0402     priv->soc_info = pdata;
0403 
0404     priv->clk = devm_clk_get(dev, NULL);
0405     if (IS_ERR(priv->clk)) {
0406         return dev_err_probe(dev, PTR_ERR(priv->clk),
0407                      "Unable to get clock.\n");
0408     }
0409 
0410     base = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->mem_res);
0411     if (IS_ERR(base))
0412         return PTR_ERR(base);
0413 
0414     priv->map = devm_regmap_init_mmio(dev, base, &spi_ingenic_regmap_config);
0415     if (IS_ERR(priv->map))
0416         return PTR_ERR(priv->map);
0417 
0418     priv->flen_field = devm_regmap_field_alloc(dev, priv->map,
0419                            pdata->flen_field);
0420     if (IS_ERR(priv->flen_field))
0421         return PTR_ERR(priv->flen_field);
0422 
0423     if (device_property_read_u32(dev, "num-cs", &num_cs))
0424         num_cs = pdata->max_native_cs;
0425 
0426     platform_set_drvdata(pdev, ctlr);
0427 
0428     ctlr->prepare_transfer_hardware = spi_ingenic_prepare_hardware;
0429     ctlr->unprepare_transfer_hardware = spi_ingenic_unprepare_hardware;
0430     ctlr->prepare_message = spi_ingenic_prepare_message;
0431     ctlr->set_cs = spi_ingenic_set_cs;
0432     ctlr->transfer_one = spi_ingenic_transfer_one;
0433     ctlr->mode_bits = SPI_MODE_3 | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_HIGH;
0434     ctlr->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX;
0435     ctlr->max_dma_len = SPI_INGENIC_FIFO_SIZE;
0436     ctlr->bits_per_word_mask = pdata->bits_per_word_mask;
0437     ctlr->min_speed_hz = 7200;
0438     ctlr->max_speed_hz = pdata->max_speed_hz;
0439     ctlr->use_gpio_descriptors = true;
0440     ctlr->max_native_cs = pdata->max_native_cs;
0441     ctlr->num_chipselect = num_cs;
0442     ctlr->dev.of_node = pdev->dev.of_node;
0443 
0444     if (spi_ingenic_request_dma(ctlr, dev))
0445         dev_warn(dev, "DMA not available.\n");
0446 
0447     ret = devm_add_action_or_reset(dev, spi_ingenic_release_dma, ctlr);
0448     if (ret) {
0449         dev_err(dev, "Unable to add action.\n");
0450         return ret;
0451     }
0452 
0453     ret = devm_spi_register_controller(dev, ctlr);
0454     if (ret)
0455         dev_err(dev, "Unable to register SPI controller.\n");
0456 
0457     return ret;
0458 }
0459 
0460 static const struct jz_soc_info jz4750_soc_info = {
0461     .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 17),
0462     .flen_field = REG_FIELD(REG_SSICR1, 4, 7),
0463     .has_trendian = false,
0464 
0465     .max_speed_hz = 54000000,
0466     .max_native_cs = 2,
0467 };
0468 
0469 static const struct jz_soc_info jz4780_soc_info = {
0470     .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
0471     .flen_field = REG_FIELD(REG_SSICR1, 3, 7),
0472     .has_trendian = true,
0473 
0474     .max_speed_hz = 54000000,
0475     .max_native_cs = 2,
0476 };
0477 
0478 static const struct jz_soc_info x1000_soc_info = {
0479     .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
0480     .flen_field = REG_FIELD(REG_SSICR1, 3, 7),
0481     .has_trendian = true,
0482 
0483     .max_speed_hz = 50000000,
0484     .max_native_cs = 2,
0485 };
0486 
0487 static const struct jz_soc_info x2000_soc_info = {
0488     .bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 32),
0489     .flen_field = REG_FIELD(REG_SSICR1, 3, 7),
0490     .has_trendian = true,
0491 
0492     .max_speed_hz = 50000000,
0493     .max_native_cs = 1,
0494 };
0495 
0496 static const struct of_device_id spi_ingenic_of_match[] = {
0497     { .compatible = "ingenic,jz4750-spi", .data = &jz4750_soc_info },
0498     { .compatible = "ingenic,jz4775-spi", .data = &jz4780_soc_info },
0499     { .compatible = "ingenic,jz4780-spi", .data = &jz4780_soc_info },
0500     { .compatible = "ingenic,x1000-spi", .data = &x1000_soc_info },
0501     { .compatible = "ingenic,x2000-spi", .data = &x2000_soc_info },
0502     {}
0503 };
0504 MODULE_DEVICE_TABLE(of, spi_ingenic_of_match);
0505 
0506 static struct platform_driver spi_ingenic_driver = {
0507     .driver = {
0508         .name = "spi-ingenic",
0509         .of_match_table = spi_ingenic_of_match,
0510     },
0511     .probe = spi_ingenic_probe,
0512 };
0513 
0514 module_platform_driver(spi_ingenic_driver);
0515 MODULE_DESCRIPTION("SPI bus driver for the Ingenic SoCs");
0516 MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>");
0517 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
0518 MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
0519 MODULE_LICENSE("GPL");
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