Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // HiSilicon SPI Controller Driver for Kunpeng SoCs
0004 //
0005 // Copyright (c) 2021 HiSilicon Technologies Co., Ltd.
0006 // Author: Jay Fang <f.fangjian@huawei.com>
0007 //
0008 // This code is based on spi-dw-core.c.
0009 
0010 #include <linux/acpi.h>
0011 #include <linux/bitfield.h>
0012 #include <linux/debugfs.h>
0013 #include <linux/delay.h>
0014 #include <linux/err.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/module.h>
0017 #include <linux/property.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/slab.h>
0020 #include <linux/spi/spi.h>
0021 
0022 /* Register offsets */
0023 #define HISI_SPI_CSCR       0x00    /* cs control register */
0024 #define HISI_SPI_CR     0x04    /* spi common control register */
0025 #define HISI_SPI_ENR        0x08    /* spi enable register */
0026 #define HISI_SPI_FIFOC      0x0c    /* fifo level control register */
0027 #define HISI_SPI_IMR        0x10    /* interrupt mask register */
0028 #define HISI_SPI_DIN        0x14    /* data in register */
0029 #define HISI_SPI_DOUT       0x18    /* data out register */
0030 #define HISI_SPI_SR     0x1c    /* status register */
0031 #define HISI_SPI_RISR       0x20    /* raw interrupt status register */
0032 #define HISI_SPI_ISR        0x24    /* interrupt status register */
0033 #define HISI_SPI_ICR        0x28    /* interrupt clear register */
0034 #define HISI_SPI_VERSION    0xe0    /* version register */
0035 
0036 /* Bit fields in HISI_SPI_CR */
0037 #define CR_LOOP_MASK        GENMASK(1, 1)
0038 #define CR_CPOL_MASK        GENMASK(2, 2)
0039 #define CR_CPHA_MASK        GENMASK(3, 3)
0040 #define CR_DIV_PRE_MASK     GENMASK(11, 4)
0041 #define CR_DIV_POST_MASK    GENMASK(19, 12)
0042 #define CR_BPW_MASK     GENMASK(24, 20)
0043 #define CR_SPD_MODE_MASK    GENMASK(25, 25)
0044 
0045 /* Bit fields in HISI_SPI_FIFOC */
0046 #define FIFOC_TX_MASK       GENMASK(5, 3)
0047 #define FIFOC_RX_MASK       GENMASK(11, 9)
0048 
0049 /* Bit fields in HISI_SPI_IMR, 4 bits */
0050 #define IMR_RXOF        BIT(0)      /* Receive Overflow */
0051 #define IMR_RXTO        BIT(1)      /* Receive Timeout */
0052 #define IMR_RX          BIT(2)      /* Receive */
0053 #define IMR_TX          BIT(3)      /* Transmit */
0054 #define IMR_MASK        (IMR_RXOF | IMR_RXTO | IMR_RX | IMR_TX)
0055 
0056 /* Bit fields in HISI_SPI_SR, 5 bits */
0057 #define SR_TXE          BIT(0)      /* Transmit FIFO empty */
0058 #define SR_TXNF         BIT(1)      /* Transmit FIFO not full */
0059 #define SR_RXNE         BIT(2)      /* Receive FIFO not empty */
0060 #define SR_RXF          BIT(3)      /* Receive FIFO full */
0061 #define SR_BUSY         BIT(4)      /* Busy Flag */
0062 
0063 /* Bit fields in HISI_SPI_ISR, 4 bits */
0064 #define ISR_RXOF        BIT(0)      /* Receive Overflow */
0065 #define ISR_RXTO        BIT(1)      /* Receive Timeout */
0066 #define ISR_RX          BIT(2)      /* Receive */
0067 #define ISR_TX          BIT(3)      /* Transmit */
0068 #define ISR_MASK        (ISR_RXOF | ISR_RXTO | ISR_RX | ISR_TX)
0069 
0070 /* Bit fields in HISI_SPI_ICR, 2 bits */
0071 #define ICR_RXOF        BIT(0)      /* Receive Overflow */
0072 #define ICR_RXTO        BIT(1)      /* Receive Timeout */
0073 #define ICR_MASK        (ICR_RXOF | ICR_RXTO)
0074 
0075 #define DIV_POST_MAX        0xFF
0076 #define DIV_POST_MIN        0x00
0077 #define DIV_PRE_MAX     0xFE
0078 #define DIV_PRE_MIN     0x02
0079 #define CLK_DIV_MAX     ((1 + DIV_POST_MAX) * DIV_PRE_MAX)
0080 #define CLK_DIV_MIN     ((1 + DIV_POST_MIN) * DIV_PRE_MIN)
0081 
0082 #define DEFAULT_NUM_CS      1
0083 
0084 #define HISI_SPI_WAIT_TIMEOUT_MS    10UL
0085 
0086 enum hisi_spi_rx_level_trig {
0087     HISI_SPI_RX_1,
0088     HISI_SPI_RX_4,
0089     HISI_SPI_RX_8,
0090     HISI_SPI_RX_16,
0091     HISI_SPI_RX_32,
0092     HISI_SPI_RX_64,
0093     HISI_SPI_RX_128
0094 };
0095 
0096 enum hisi_spi_tx_level_trig {
0097     HISI_SPI_TX_1_OR_LESS,
0098     HISI_SPI_TX_4_OR_LESS,
0099     HISI_SPI_TX_8_OR_LESS,
0100     HISI_SPI_TX_16_OR_LESS,
0101     HISI_SPI_TX_32_OR_LESS,
0102     HISI_SPI_TX_64_OR_LESS,
0103     HISI_SPI_TX_128_OR_LESS
0104 };
0105 
0106 enum hisi_spi_frame_n_bytes {
0107     HISI_SPI_N_BYTES_NULL,
0108     HISI_SPI_N_BYTES_U8,
0109     HISI_SPI_N_BYTES_U16,
0110     HISI_SPI_N_BYTES_U32 = 4
0111 };
0112 
0113 /* Slave spi_dev related */
0114 struct hisi_chip_data {
0115     u32 cr;
0116     u32 speed_hz;   /* baud rate */
0117     u16 clk_div;    /* baud rate divider */
0118 
0119     /* clk_div = (1 + div_post) * div_pre */
0120     u8 div_post;    /* value from 0 to 255 */
0121     u8 div_pre; /* value from 2 to 254 (even only!) */
0122 };
0123 
0124 struct hisi_spi {
0125     struct device       *dev;
0126 
0127     void __iomem        *regs;
0128     int         irq;
0129     u32         fifo_len; /* depth of the FIFO buffer */
0130 
0131     /* Current message transfer state info */
0132     const void      *tx;
0133     unsigned int        tx_len;
0134     void            *rx;
0135     unsigned int        rx_len;
0136     u8          n_bytes; /* current is a 1/2/4 bytes op */
0137 
0138     struct dentry *debugfs;
0139     struct debugfs_regset32 regset;
0140 };
0141 
0142 #define HISI_SPI_DBGFS_REG(_name, _off) \
0143 {                   \
0144     .name = _name,          \
0145     .offset = _off,         \
0146 }
0147 
0148 static const struct debugfs_reg32 hisi_spi_regs[] = {
0149     HISI_SPI_DBGFS_REG("CSCR", HISI_SPI_CSCR),
0150     HISI_SPI_DBGFS_REG("CR", HISI_SPI_CR),
0151     HISI_SPI_DBGFS_REG("ENR", HISI_SPI_ENR),
0152     HISI_SPI_DBGFS_REG("FIFOC", HISI_SPI_FIFOC),
0153     HISI_SPI_DBGFS_REG("IMR", HISI_SPI_IMR),
0154     HISI_SPI_DBGFS_REG("DIN", HISI_SPI_DIN),
0155     HISI_SPI_DBGFS_REG("DOUT", HISI_SPI_DOUT),
0156     HISI_SPI_DBGFS_REG("SR", HISI_SPI_SR),
0157     HISI_SPI_DBGFS_REG("RISR", HISI_SPI_RISR),
0158     HISI_SPI_DBGFS_REG("ISR", HISI_SPI_ISR),
0159     HISI_SPI_DBGFS_REG("ICR", HISI_SPI_ICR),
0160     HISI_SPI_DBGFS_REG("VERSION", HISI_SPI_VERSION),
0161 };
0162 
0163 static int hisi_spi_debugfs_init(struct hisi_spi *hs)
0164 {
0165     char name[32];
0166 
0167     struct spi_controller *master;
0168 
0169     master = container_of(hs->dev, struct spi_controller, dev);
0170     snprintf(name, 32, "hisi_spi%d", master->bus_num);
0171     hs->debugfs = debugfs_create_dir(name, NULL);
0172     if (!hs->debugfs)
0173         return -ENOMEM;
0174 
0175     hs->regset.regs = hisi_spi_regs;
0176     hs->regset.nregs = ARRAY_SIZE(hisi_spi_regs);
0177     hs->regset.base = hs->regs;
0178     debugfs_create_regset32("registers", 0400, hs->debugfs, &hs->regset);
0179 
0180     return 0;
0181 }
0182 
0183 static u32 hisi_spi_busy(struct hisi_spi *hs)
0184 {
0185     return readl(hs->regs + HISI_SPI_SR) & SR_BUSY;
0186 }
0187 
0188 static u32 hisi_spi_rx_not_empty(struct hisi_spi *hs)
0189 {
0190     return readl(hs->regs + HISI_SPI_SR) & SR_RXNE;
0191 }
0192 
0193 static u32 hisi_spi_tx_not_full(struct hisi_spi *hs)
0194 {
0195     return readl(hs->regs + HISI_SPI_SR) & SR_TXNF;
0196 }
0197 
0198 static void hisi_spi_flush_fifo(struct hisi_spi *hs)
0199 {
0200     unsigned long limit = loops_per_jiffy << 1;
0201 
0202     do {
0203         while (hisi_spi_rx_not_empty(hs))
0204             readl(hs->regs + HISI_SPI_DOUT);
0205     } while (hisi_spi_busy(hs) && limit--);
0206 }
0207 
0208 /* Disable the controller and all interrupts */
0209 static void hisi_spi_disable(struct hisi_spi *hs)
0210 {
0211     writel(0, hs->regs + HISI_SPI_ENR);
0212     writel(IMR_MASK, hs->regs + HISI_SPI_IMR);
0213     writel(ICR_MASK, hs->regs + HISI_SPI_ICR);
0214 }
0215 
0216 static u8 hisi_spi_n_bytes(struct spi_transfer *transfer)
0217 {
0218     if (transfer->bits_per_word <= 8)
0219         return HISI_SPI_N_BYTES_U8;
0220     else if (transfer->bits_per_word <= 16)
0221         return HISI_SPI_N_BYTES_U16;
0222     else
0223         return HISI_SPI_N_BYTES_U32;
0224 }
0225 
0226 static void hisi_spi_reader(struct hisi_spi *hs)
0227 {
0228     u32 max = min_t(u32, hs->rx_len, hs->fifo_len);
0229     u32 rxw;
0230 
0231     while (hisi_spi_rx_not_empty(hs) && max--) {
0232         rxw = readl(hs->regs + HISI_SPI_DOUT);
0233         /* Check the transfer's original "rx" is not null */
0234         if (hs->rx) {
0235             switch (hs->n_bytes) {
0236             case HISI_SPI_N_BYTES_U8:
0237                 *(u8 *)(hs->rx) = rxw;
0238                 break;
0239             case HISI_SPI_N_BYTES_U16:
0240                 *(u16 *)(hs->rx) = rxw;
0241                 break;
0242             case HISI_SPI_N_BYTES_U32:
0243                 *(u32 *)(hs->rx) = rxw;
0244                 break;
0245             }
0246             hs->rx += hs->n_bytes;
0247         }
0248         --hs->rx_len;
0249     }
0250 }
0251 
0252 static void hisi_spi_writer(struct hisi_spi *hs)
0253 {
0254     u32 max = min_t(u32, hs->tx_len, hs->fifo_len);
0255     u32 txw = 0;
0256 
0257     while (hisi_spi_tx_not_full(hs) && max--) {
0258         /* Check the transfer's original "tx" is not null */
0259         if (hs->tx) {
0260             switch (hs->n_bytes) {
0261             case HISI_SPI_N_BYTES_U8:
0262                 txw = *(u8 *)(hs->tx);
0263                 break;
0264             case HISI_SPI_N_BYTES_U16:
0265                 txw = *(u16 *)(hs->tx);
0266                 break;
0267             case HISI_SPI_N_BYTES_U32:
0268                 txw = *(u32 *)(hs->tx);
0269                 break;
0270             }
0271             hs->tx += hs->n_bytes;
0272         }
0273         writel(txw, hs->regs + HISI_SPI_DIN);
0274         --hs->tx_len;
0275     }
0276 }
0277 
0278 static void __hisi_calc_div_reg(struct hisi_chip_data *chip)
0279 {
0280     chip->div_pre = DIV_PRE_MAX;
0281     while (chip->div_pre >= DIV_PRE_MIN) {
0282         if (chip->clk_div % chip->div_pre == 0)
0283             break;
0284 
0285         chip->div_pre -= 2;
0286     }
0287 
0288     if (chip->div_pre > chip->clk_div)
0289         chip->div_pre = chip->clk_div;
0290 
0291     chip->div_post = (chip->clk_div / chip->div_pre) - 1;
0292 }
0293 
0294 static u32 hisi_calc_effective_speed(struct spi_controller *master,
0295             struct hisi_chip_data *chip, u32 speed_hz)
0296 {
0297     u32 effective_speed;
0298 
0299     /* Note clock divider doesn't support odd numbers */
0300     chip->clk_div = DIV_ROUND_UP(master->max_speed_hz, speed_hz) + 1;
0301     chip->clk_div &= 0xfffe;
0302     if (chip->clk_div > CLK_DIV_MAX)
0303         chip->clk_div = CLK_DIV_MAX;
0304 
0305     effective_speed = master->max_speed_hz / chip->clk_div;
0306     if (chip->speed_hz != effective_speed) {
0307         __hisi_calc_div_reg(chip);
0308         chip->speed_hz = effective_speed;
0309     }
0310 
0311     return effective_speed;
0312 }
0313 
0314 static u32 hisi_spi_prepare_cr(struct spi_device *spi)
0315 {
0316     u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1);
0317 
0318     cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0);
0319     cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0);
0320     cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0);
0321 
0322     return cr;
0323 }
0324 
0325 static void hisi_spi_hw_init(struct hisi_spi *hs)
0326 {
0327     hisi_spi_disable(hs);
0328 
0329     /* FIFO default config */
0330     writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) |
0331         FIELD_PREP(FIFOC_RX_MASK, HISI_SPI_RX_16),
0332         hs->regs + HISI_SPI_FIFOC);
0333 
0334     hs->fifo_len = 256;
0335 }
0336 
0337 static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
0338 {
0339     struct spi_controller *master = dev_id;
0340     struct hisi_spi *hs = spi_controller_get_devdata(master);
0341     u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;
0342 
0343     if (!irq_status)
0344         return IRQ_NONE;
0345 
0346     if (!master->cur_msg)
0347         return IRQ_HANDLED;
0348 
0349     /* Error handling */
0350     if (irq_status & ISR_RXOF) {
0351         dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");
0352         master->cur_msg->status = -EIO;
0353         goto finalize_transfer;
0354     }
0355 
0356     /*
0357      * Read data from the Rx FIFO every time. If there is
0358      * nothing left to receive, finalize the transfer.
0359      */
0360     hisi_spi_reader(hs);
0361     if (!hs->rx_len)
0362         goto finalize_transfer;
0363 
0364     /* Send data out when Tx FIFO IRQ triggered */
0365     if (irq_status & ISR_TX)
0366         hisi_spi_writer(hs);
0367 
0368     return IRQ_HANDLED;
0369 
0370 finalize_transfer:
0371     hisi_spi_disable(hs);
0372     spi_finalize_current_transfer(master);
0373     return IRQ_HANDLED;
0374 }
0375 
0376 static int hisi_spi_transfer_one(struct spi_controller *master,
0377         struct spi_device *spi, struct spi_transfer *transfer)
0378 {
0379     struct hisi_spi *hs = spi_controller_get_devdata(master);
0380     struct hisi_chip_data *chip = spi_get_ctldata(spi);
0381     u32 cr = chip->cr;
0382 
0383     /* Update per transfer options for speed and bpw */
0384     transfer->effective_speed_hz =
0385         hisi_calc_effective_speed(master, chip, transfer->speed_hz);
0386     cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);
0387     cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);
0388     cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
0389     writel(cr, hs->regs + HISI_SPI_CR);
0390 
0391     hisi_spi_flush_fifo(hs);
0392 
0393     hs->n_bytes = hisi_spi_n_bytes(transfer);
0394     hs->tx = transfer->tx_buf;
0395     hs->tx_len = transfer->len / hs->n_bytes;
0396     hs->rx = transfer->rx_buf;
0397     hs->rx_len = hs->tx_len;
0398 
0399     /*
0400      * Ensure that the transfer data above has been updated
0401      * before the interrupt to start.
0402      */
0403     smp_mb();
0404 
0405     /* Enable all interrupts and the controller */
0406     writel(~(u32)IMR_MASK, hs->regs + HISI_SPI_IMR);
0407     writel(1, hs->regs + HISI_SPI_ENR);
0408 
0409     return 1;
0410 }
0411 
0412 static void hisi_spi_handle_err(struct spi_controller *master,
0413         struct spi_message *msg)
0414 {
0415     struct hisi_spi *hs = spi_controller_get_devdata(master);
0416 
0417     hisi_spi_disable(hs);
0418 
0419     /*
0420      * Wait for interrupt handler that is
0421      * already in timeout to complete.
0422      */
0423     msleep(HISI_SPI_WAIT_TIMEOUT_MS);
0424 }
0425 
0426 static int hisi_spi_setup(struct spi_device *spi)
0427 {
0428     struct hisi_chip_data *chip;
0429 
0430     /* Only alloc on first setup */
0431     chip = spi_get_ctldata(spi);
0432     if (!chip) {
0433         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
0434         if (!chip)
0435             return -ENOMEM;
0436         spi_set_ctldata(spi, chip);
0437     }
0438 
0439     chip->cr = hisi_spi_prepare_cr(spi);
0440 
0441     return 0;
0442 }
0443 
0444 static void hisi_spi_cleanup(struct spi_device *spi)
0445 {
0446     struct hisi_chip_data *chip = spi_get_ctldata(spi);
0447 
0448     kfree(chip);
0449     spi_set_ctldata(spi, NULL);
0450 }
0451 
0452 static int hisi_spi_probe(struct platform_device *pdev)
0453 {
0454     struct device *dev = &pdev->dev;
0455     struct spi_controller *master;
0456     struct hisi_spi *hs;
0457     int ret, irq;
0458 
0459     irq = platform_get_irq(pdev, 0);
0460     if (irq < 0)
0461         return irq;
0462 
0463     master = devm_spi_alloc_master(dev, sizeof(*hs));
0464     if (!master)
0465         return -ENOMEM;
0466 
0467     platform_set_drvdata(pdev, master);
0468 
0469     hs = spi_controller_get_devdata(master);
0470     hs->dev = dev;
0471     hs->irq = irq;
0472 
0473     hs->regs = devm_platform_ioremap_resource(pdev, 0);
0474     if (IS_ERR(hs->regs))
0475         return PTR_ERR(hs->regs);
0476 
0477     /* Specify maximum SPI clocking speed (master only) by firmware */
0478     ret = device_property_read_u32(dev, "spi-max-frequency",
0479                     &master->max_speed_hz);
0480     if (ret) {
0481         dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",
0482             ret);
0483         return -EINVAL;
0484     }
0485 
0486     ret = device_property_read_u16(dev, "num-cs",
0487                     &master->num_chipselect);
0488     if (ret)
0489         master->num_chipselect = DEFAULT_NUM_CS;
0490 
0491     master->use_gpio_descriptors = true;
0492     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
0493     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
0494     master->bus_num = pdev->id;
0495     master->setup = hisi_spi_setup;
0496     master->cleanup = hisi_spi_cleanup;
0497     master->transfer_one = hisi_spi_transfer_one;
0498     master->handle_err = hisi_spi_handle_err;
0499     master->dev.fwnode = dev->fwnode;
0500 
0501     hisi_spi_hw_init(hs);
0502 
0503     ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),
0504             master);
0505     if (ret < 0) {
0506         dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);
0507         return ret;
0508     }
0509 
0510     ret = spi_register_controller(master);
0511     if (ret) {
0512         dev_err(dev, "failed to register spi master, ret=%d\n", ret);
0513         return ret;
0514     }
0515 
0516     if (hisi_spi_debugfs_init(hs))
0517         dev_info(dev, "failed to create debugfs dir\n");
0518 
0519     dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",
0520         readl(hs->regs + HISI_SPI_VERSION),
0521         master->max_speed_hz / 1000);
0522 
0523     return 0;
0524 }
0525 
0526 static int hisi_spi_remove(struct platform_device *pdev)
0527 {
0528     struct spi_controller *master = platform_get_drvdata(pdev);
0529     struct hisi_spi *hs = spi_controller_get_devdata(master);
0530 
0531     debugfs_remove_recursive(hs->debugfs);
0532     spi_unregister_controller(master);
0533 
0534     return 0;
0535 }
0536 
0537 static const struct acpi_device_id hisi_spi_acpi_match[] = {
0538     {"HISI03E1", 0},
0539     {}
0540 };
0541 MODULE_DEVICE_TABLE(acpi, hisi_spi_acpi_match);
0542 
0543 static struct platform_driver hisi_spi_driver = {
0544     .probe      = hisi_spi_probe,
0545     .remove     = hisi_spi_remove,
0546     .driver     = {
0547         .name   = "hisi-kunpeng-spi",
0548         .acpi_match_table = hisi_spi_acpi_match,
0549     },
0550 };
0551 module_platform_driver(hisi_spi_driver);
0552 
0553 MODULE_AUTHOR("Jay Fang <f.fangjian@huawei.com>");
0554 MODULE_DESCRIPTION("HiSilicon SPI Controller Driver for Kunpeng SoCs");
0555 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!