drivers/spi/spi-fsl-spi.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Freescale SPI controller driver.
0004  *
0005  * Maintainer: Kumar Gala
0006  *
0007  * Copyright (C) 2006 Polycom, Inc.
0008  * Copyright 2010 Freescale Semiconductor, Inc.
0009  *
0010  * CPM SPI and QE buffer descriptors mode support:
0011  * Copyright (c) 2009  MontaVista Software, Inc.
0012  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0013  *
0014  * GRLIB support:
0015  * Copyright (c) 2012 Aeroflex Gaisler AB.
0016  * Author: Andreas Larsson <andreas@gaisler.com>
0017  */
0018
0019 #ifndef __SPI_FSL_SPI_H__
0020 #define __SPI_FSL_SPI_H__
0021
0022 /* SPI Controller registers */
0023 struct fsl_spi_reg {
0024     __be32 cap; /* TYPE_GRLIB specific */
0025     u8 res1[0x1C];
0026     __be32 mode;
0027     __be32 event;
0028     __be32 mask;
0029     __be32 command;
0030     __be32 transmit;
0031     __be32 receive;
0032     __be32 slvsel; /* TYPE_GRLIB specific */
0033 };
0034
0035 /* SPI Controller mode register definitions */
0036 #define SPMODE_LOOP     (1 << 30)
0037 #define SPMODE_CI_INACTIVEHIGH  (1 << 29)
0038 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
0039 #define SPMODE_DIV16        (1 << 27)
0040 #define SPMODE_REV      (1 << 26)
0041 #define SPMODE_MS       (1 << 25)
0042 #define SPMODE_ENABLE       (1 << 24)
0043 #define SPMODE_LEN(x)       ((x) << 20)
0044 #define SPMODE_PM(x)        ((x) << 16)
0045 #define SPMODE_OP       (1 << 14)
0046 #define SPMODE_CG(x)        ((x) << 7)
0047
0048 /* TYPE_GRLIB SPI Controller capability register definitions */
0049 #define SPCAP_SSEN(x)       (((x) >> 16) & 0x1)
0050 #define SPCAP_SSSZ(x)       (((x) >> 24) & 0xff)
0051 #define SPCAP_MAXWLEN(x)    (((x) >> 20) & 0xf)
0052
0053 /*
0054  * Default for SPI Mode:
0055  *  SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
0056  */
0057 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
0058              SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
0059
0060 /* SPIE register values */
0061 #define SPIE_NE     0x00000200  /* Not empty */
0062 #define SPIE_NF     0x00000100  /* Not full */
0063
0064 /* SPIM register values */
0065 #define SPIM_NE     0x00000200  /* Not empty */
0066 #define SPIM_NF     0x00000100  /* Not full */
0067
0068 #endif /* __SPI_FSL_SPI_H__ */