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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale SPI controller driver.
0004  *
0005  * Maintainer: Kumar Gala
0006  *
0007  * Copyright (C) 2006 Polycom, Inc.
0008  * Copyright 2010 Freescale Semiconductor, Inc.
0009  *
0010  * CPM SPI and QE buffer descriptors mode support:
0011  * Copyright (c) 2009  MontaVista Software, Inc.
0012  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0013  *
0014  * GRLIB support:
0015  * Copyright (c) 2012 Aeroflex Gaisler AB.
0016  * Author: Andreas Larsson <andreas@gaisler.com>
0017  */
0018 #include <linux/delay.h>
0019 #include <linux/dma-mapping.h>
0020 #include <linux/fsl_devices.h>
0021 #include <linux/gpio/consumer.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/irq.h>
0024 #include <linux/kernel.h>
0025 #include <linux/mm.h>
0026 #include <linux/module.h>
0027 #include <linux/mutex.h>
0028 #include <linux/of.h>
0029 #include <linux/of_address.h>
0030 #include <linux/of_irq.h>
0031 #include <linux/of_platform.h>
0032 #include <linux/platform_device.h>
0033 #include <linux/spi/spi.h>
0034 #include <linux/spi/spi_bitbang.h>
0035 #include <linux/types.h>
0036 
0037 #ifdef CONFIG_FSL_SOC
0038 #include <sysdev/fsl_soc.h>
0039 #endif
0040 
0041 /* Specific to the MPC8306/MPC8309 */
0042 #define IMMR_SPI_CS_OFFSET 0x14c
0043 #define SPI_BOOT_SEL_BIT   0x80000000
0044 
0045 #include "spi-fsl-lib.h"
0046 #include "spi-fsl-cpm.h"
0047 #include "spi-fsl-spi.h"
0048 
0049 #define TYPE_FSL    0
0050 #define TYPE_GRLIB  1
0051 
0052 struct fsl_spi_match_data {
0053     int type;
0054 };
0055 
0056 static struct fsl_spi_match_data of_fsl_spi_fsl_config = {
0057     .type = TYPE_FSL,
0058 };
0059 
0060 static struct fsl_spi_match_data of_fsl_spi_grlib_config = {
0061     .type = TYPE_GRLIB,
0062 };
0063 
0064 static const struct of_device_id of_fsl_spi_match[] = {
0065     {
0066         .compatible = "fsl,spi",
0067         .data = &of_fsl_spi_fsl_config,
0068     },
0069     {
0070         .compatible = "aeroflexgaisler,spictrl",
0071         .data = &of_fsl_spi_grlib_config,
0072     },
0073     {}
0074 };
0075 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
0076 
0077 static int fsl_spi_get_type(struct device *dev)
0078 {
0079     const struct of_device_id *match;
0080 
0081     if (dev->of_node) {
0082         match = of_match_node(of_fsl_spi_match, dev->of_node);
0083         if (match && match->data)
0084             return ((struct fsl_spi_match_data *)match->data)->type;
0085     }
0086     return TYPE_FSL;
0087 }
0088 
0089 static void fsl_spi_change_mode(struct spi_device *spi)
0090 {
0091     struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
0092     struct spi_mpc8xxx_cs *cs = spi->controller_state;
0093     struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
0094     __be32 __iomem *mode = &reg_base->mode;
0095     unsigned long flags;
0096 
0097     if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
0098         return;
0099 
0100     /* Turn off IRQs locally to minimize time that SPI is disabled. */
0101     local_irq_save(flags);
0102 
0103     /* Turn off SPI unit prior changing mode */
0104     mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
0105 
0106     /* When in CPM mode, we need to reinit tx and rx. */
0107     if (mspi->flags & SPI_CPM_MODE) {
0108         fsl_spi_cpm_reinit_txrx(mspi);
0109     }
0110     mpc8xxx_spi_write_reg(mode, cs->hw_mode);
0111     local_irq_restore(flags);
0112 }
0113 
0114 static void fsl_spi_chipselect(struct spi_device *spi, int value)
0115 {
0116     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
0117     struct fsl_spi_platform_data *pdata;
0118     struct spi_mpc8xxx_cs   *cs = spi->controller_state;
0119 
0120     pdata = spi->dev.parent->parent->platform_data;
0121 
0122     if (value == BITBANG_CS_INACTIVE) {
0123         if (pdata->cs_control)
0124             pdata->cs_control(spi, false);
0125     }
0126 
0127     if (value == BITBANG_CS_ACTIVE) {
0128         mpc8xxx_spi->rx_shift = cs->rx_shift;
0129         mpc8xxx_spi->tx_shift = cs->tx_shift;
0130         mpc8xxx_spi->get_rx = cs->get_rx;
0131         mpc8xxx_spi->get_tx = cs->get_tx;
0132 
0133         fsl_spi_change_mode(spi);
0134 
0135         if (pdata->cs_control)
0136             pdata->cs_control(spi, true);
0137     }
0138 }
0139 
0140 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
0141                       int bits_per_word, int msb_first)
0142 {
0143     *rx_shift = 0;
0144     *tx_shift = 0;
0145     if (msb_first) {
0146         if (bits_per_word <= 8) {
0147             *rx_shift = 16;
0148             *tx_shift = 24;
0149         } else if (bits_per_word <= 16) {
0150             *rx_shift = 16;
0151             *tx_shift = 16;
0152         }
0153     } else {
0154         if (bits_per_word <= 8)
0155             *rx_shift = 8;
0156     }
0157 }
0158 
0159 static void fsl_spi_grlib_set_shifts(u32 *rx_shift, u32 *tx_shift,
0160                      int bits_per_word, int msb_first)
0161 {
0162     *rx_shift = 0;
0163     *tx_shift = 0;
0164     if (bits_per_word <= 16) {
0165         if (msb_first) {
0166             *rx_shift = 16; /* LSB in bit 16 */
0167             *tx_shift = 32 - bits_per_word; /* MSB in bit 31 */
0168         } else {
0169             *rx_shift = 16 - bits_per_word; /* MSB in bit 15 */
0170         }
0171     }
0172 }
0173 
0174 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
0175                 struct spi_device *spi,
0176                 struct mpc8xxx_spi *mpc8xxx_spi,
0177                 int bits_per_word)
0178 {
0179     cs->rx_shift = 0;
0180     cs->tx_shift = 0;
0181     if (bits_per_word <= 8) {
0182         cs->get_rx = mpc8xxx_spi_rx_buf_u8;
0183         cs->get_tx = mpc8xxx_spi_tx_buf_u8;
0184     } else if (bits_per_word <= 16) {
0185         cs->get_rx = mpc8xxx_spi_rx_buf_u16;
0186         cs->get_tx = mpc8xxx_spi_tx_buf_u16;
0187     } else if (bits_per_word <= 32) {
0188         cs->get_rx = mpc8xxx_spi_rx_buf_u32;
0189         cs->get_tx = mpc8xxx_spi_tx_buf_u32;
0190     } else
0191         return -EINVAL;
0192 
0193     if (mpc8xxx_spi->set_shifts)
0194         mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
0195                     bits_per_word,
0196                     !(spi->mode & SPI_LSB_FIRST));
0197 
0198     mpc8xxx_spi->rx_shift = cs->rx_shift;
0199     mpc8xxx_spi->tx_shift = cs->tx_shift;
0200     mpc8xxx_spi->get_rx = cs->get_rx;
0201     mpc8xxx_spi->get_tx = cs->get_tx;
0202 
0203     return bits_per_word;
0204 }
0205 
0206 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
0207                 struct spi_device *spi,
0208                 int bits_per_word)
0209 {
0210     /* QE uses Little Endian for words > 8
0211      * so transform all words > 8 into 8 bits
0212      * Unfortnatly that doesn't work for LSB so
0213      * reject these for now */
0214     /* Note: 32 bits word, LSB works iff
0215      * tfcr/rfcr is set to CPMFCR_GBL */
0216     if (spi->mode & SPI_LSB_FIRST &&
0217         bits_per_word > 8)
0218         return -EINVAL;
0219     if (bits_per_word > 8)
0220         return 8; /* pretend its 8 bits */
0221     return bits_per_word;
0222 }
0223 
0224 static int fsl_spi_setup_transfer(struct spi_device *spi,
0225                     struct spi_transfer *t)
0226 {
0227     struct mpc8xxx_spi *mpc8xxx_spi;
0228     int bits_per_word = 0;
0229     u8 pm;
0230     u32 hz = 0;
0231     struct spi_mpc8xxx_cs   *cs = spi->controller_state;
0232 
0233     mpc8xxx_spi = spi_master_get_devdata(spi->master);
0234 
0235     if (t) {
0236         bits_per_word = t->bits_per_word;
0237         hz = t->speed_hz;
0238     }
0239 
0240     /* spi_transfer level calls that work per-word */
0241     if (!bits_per_word)
0242         bits_per_word = spi->bits_per_word;
0243 
0244     if (!hz)
0245         hz = spi->max_speed_hz;
0246 
0247     if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
0248         bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
0249                                mpc8xxx_spi,
0250                                bits_per_word);
0251     else if (mpc8xxx_spi->flags & SPI_QE)
0252         bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
0253                               bits_per_word);
0254 
0255     if (bits_per_word < 0)
0256         return bits_per_word;
0257 
0258     if (bits_per_word == 32)
0259         bits_per_word = 0;
0260     else
0261         bits_per_word = bits_per_word - 1;
0262 
0263     /* mask out bits we are going to set */
0264     cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
0265                   | SPMODE_PM(0xF));
0266 
0267     cs->hw_mode |= SPMODE_LEN(bits_per_word);
0268 
0269     if ((mpc8xxx_spi->spibrg / hz) > 64) {
0270         cs->hw_mode |= SPMODE_DIV16;
0271         pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
0272         WARN_ONCE(pm > 16,
0273               "%s: Requested speed is too low: %d Hz. Will use %d Hz instead.\n",
0274               dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
0275         if (pm > 16)
0276             pm = 16;
0277     } else {
0278         pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
0279     }
0280     if (pm)
0281         pm--;
0282 
0283     cs->hw_mode |= SPMODE_PM(pm);
0284 
0285     fsl_spi_change_mode(spi);
0286     return 0;
0287 }
0288 
0289 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
0290                 struct spi_transfer *t, unsigned int len)
0291 {
0292     u32 word;
0293     struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
0294 
0295     mspi->count = len;
0296 
0297     /* enable rx ints */
0298     mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
0299 
0300     /* transmit word */
0301     word = mspi->get_tx(mspi);
0302     mpc8xxx_spi_write_reg(&reg_base->transmit, word);
0303 
0304     return 0;
0305 }
0306 
0307 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
0308                 bool is_dma_mapped)
0309 {
0310     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
0311     struct fsl_spi_reg __iomem *reg_base;
0312     unsigned int len = t->len;
0313     u8 bits_per_word;
0314     int ret;
0315 
0316     reg_base = mpc8xxx_spi->reg_base;
0317     bits_per_word = spi->bits_per_word;
0318     if (t->bits_per_word)
0319         bits_per_word = t->bits_per_word;
0320 
0321     if (bits_per_word > 8) {
0322         /* invalid length? */
0323         if (len & 1)
0324             return -EINVAL;
0325         len /= 2;
0326     }
0327     if (bits_per_word > 16) {
0328         /* invalid length? */
0329         if (len & 1)
0330             return -EINVAL;
0331         len /= 2;
0332     }
0333 
0334     mpc8xxx_spi->tx = t->tx_buf;
0335     mpc8xxx_spi->rx = t->rx_buf;
0336 
0337     reinit_completion(&mpc8xxx_spi->done);
0338 
0339     if (mpc8xxx_spi->flags & SPI_CPM_MODE)
0340         ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
0341     else
0342         ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
0343     if (ret)
0344         return ret;
0345 
0346     wait_for_completion(&mpc8xxx_spi->done);
0347 
0348     /* disable rx ints */
0349     mpc8xxx_spi_write_reg(&reg_base->mask, 0);
0350 
0351     if (mpc8xxx_spi->flags & SPI_CPM_MODE)
0352         fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
0353 
0354     return mpc8xxx_spi->count;
0355 }
0356 
0357 static int fsl_spi_do_one_msg(struct spi_master *master,
0358                   struct spi_message *m)
0359 {
0360     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
0361     struct spi_device *spi = m->spi;
0362     struct spi_transfer *t, *first;
0363     unsigned int cs_change;
0364     const int nsecs = 50;
0365     int status, last_bpw;
0366 
0367     /*
0368      * In CPU mode, optimize large byte transfers to use larger
0369      * bits_per_word values to reduce number of interrupts taken.
0370      */
0371     if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
0372         list_for_each_entry(t, &m->transfers, transfer_list) {
0373             if (t->len < 256 || t->bits_per_word != 8)
0374                 continue;
0375             if ((t->len & 3) == 0)
0376                 t->bits_per_word = 32;
0377             else if ((t->len & 1) == 0)
0378                 t->bits_per_word = 16;
0379         }
0380     }
0381 
0382     /* Don't allow changes if CS is active */
0383     cs_change = 1;
0384     list_for_each_entry(t, &m->transfers, transfer_list) {
0385         if (cs_change)
0386             first = t;
0387         cs_change = t->cs_change;
0388         if (first->speed_hz != t->speed_hz) {
0389             dev_err(&spi->dev,
0390                 "speed_hz cannot change while CS is active\n");
0391             return -EINVAL;
0392         }
0393     }
0394 
0395     last_bpw = -1;
0396     cs_change = 1;
0397     status = -EINVAL;
0398     list_for_each_entry(t, &m->transfers, transfer_list) {
0399         if (cs_change || last_bpw != t->bits_per_word)
0400             status = fsl_spi_setup_transfer(spi, t);
0401         if (status < 0)
0402             break;
0403         last_bpw = t->bits_per_word;
0404 
0405         if (cs_change) {
0406             fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
0407             ndelay(nsecs);
0408         }
0409         cs_change = t->cs_change;
0410         if (t->len)
0411             status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
0412         if (status) {
0413             status = -EMSGSIZE;
0414             break;
0415         }
0416         m->actual_length += t->len;
0417 
0418         spi_transfer_delay_exec(t);
0419 
0420         if (cs_change) {
0421             ndelay(nsecs);
0422             fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
0423             ndelay(nsecs);
0424         }
0425     }
0426 
0427     m->status = status;
0428 
0429     if (status || !cs_change) {
0430         ndelay(nsecs);
0431         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
0432     }
0433 
0434     fsl_spi_setup_transfer(spi, NULL);
0435     spi_finalize_current_message(master);
0436     return 0;
0437 }
0438 
0439 static int fsl_spi_setup(struct spi_device *spi)
0440 {
0441     struct mpc8xxx_spi *mpc8xxx_spi;
0442     struct fsl_spi_reg __iomem *reg_base;
0443     bool initial_setup = false;
0444     int retval;
0445     u32 hw_mode;
0446     struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
0447 
0448     if (!spi->max_speed_hz)
0449         return -EINVAL;
0450 
0451     if (!cs) {
0452         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
0453         if (!cs)
0454             return -ENOMEM;
0455         spi_set_ctldata(spi, cs);
0456         initial_setup = true;
0457     }
0458     mpc8xxx_spi = spi_master_get_devdata(spi->master);
0459 
0460     reg_base = mpc8xxx_spi->reg_base;
0461 
0462     hw_mode = cs->hw_mode; /* Save original settings */
0463     cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
0464     /* mask out bits we are going to set */
0465     cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
0466              | SPMODE_REV | SPMODE_LOOP);
0467 
0468     if (spi->mode & SPI_CPHA)
0469         cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
0470     if (spi->mode & SPI_CPOL)
0471         cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
0472     if (!(spi->mode & SPI_LSB_FIRST))
0473         cs->hw_mode |= SPMODE_REV;
0474     if (spi->mode & SPI_LOOP)
0475         cs->hw_mode |= SPMODE_LOOP;
0476 
0477     retval = fsl_spi_setup_transfer(spi, NULL);
0478     if (retval < 0) {
0479         cs->hw_mode = hw_mode; /* Restore settings */
0480         if (initial_setup)
0481             kfree(cs);
0482         return retval;
0483     }
0484 
0485     /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
0486     fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
0487 
0488     return 0;
0489 }
0490 
0491 static void fsl_spi_cleanup(struct spi_device *spi)
0492 {
0493     struct spi_mpc8xxx_cs *cs = spi_get_ctldata(spi);
0494 
0495     kfree(cs);
0496     spi_set_ctldata(spi, NULL);
0497 }
0498 
0499 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
0500 {
0501     struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
0502 
0503     /* We need handle RX first */
0504     if (events & SPIE_NE) {
0505         u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
0506 
0507         if (mspi->rx)
0508             mspi->get_rx(rx_data, mspi);
0509     }
0510 
0511     if ((events & SPIE_NF) == 0)
0512         /* spin until TX is done */
0513         while (((events =
0514             mpc8xxx_spi_read_reg(&reg_base->event)) &
0515                         SPIE_NF) == 0)
0516             cpu_relax();
0517 
0518     /* Clear the events */
0519     mpc8xxx_spi_write_reg(&reg_base->event, events);
0520 
0521     mspi->count -= 1;
0522     if (mspi->count) {
0523         u32 word = mspi->get_tx(mspi);
0524 
0525         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
0526     } else {
0527         complete(&mspi->done);
0528     }
0529 }
0530 
0531 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
0532 {
0533     struct mpc8xxx_spi *mspi = context_data;
0534     irqreturn_t ret = IRQ_NONE;
0535     u32 events;
0536     struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
0537 
0538     /* Get interrupt events(tx/rx) */
0539     events = mpc8xxx_spi_read_reg(&reg_base->event);
0540     if (events)
0541         ret = IRQ_HANDLED;
0542 
0543     dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
0544 
0545     if (mspi->flags & SPI_CPM_MODE)
0546         fsl_spi_cpm_irq(mspi, events);
0547     else
0548         fsl_spi_cpu_irq(mspi, events);
0549 
0550     return ret;
0551 }
0552 
0553 static void fsl_spi_grlib_cs_control(struct spi_device *spi, bool on)
0554 {
0555     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
0556     struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
0557     u32 slvsel;
0558     u16 cs = spi->chip_select;
0559 
0560     if (spi->cs_gpiod) {
0561         gpiod_set_value(spi->cs_gpiod, on);
0562     } else if (cs < mpc8xxx_spi->native_chipselects) {
0563         slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
0564         slvsel = on ? (slvsel | (1 << cs)) : (slvsel & ~(1 << cs));
0565         mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
0566     }
0567 }
0568 
0569 static void fsl_spi_grlib_probe(struct device *dev)
0570 {
0571     struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0572     struct spi_master *master = dev_get_drvdata(dev);
0573     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
0574     struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
0575     int mbits;
0576     u32 capabilities;
0577 
0578     capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
0579 
0580     mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
0581     mbits = SPCAP_MAXWLEN(capabilities);
0582     if (mbits)
0583         mpc8xxx_spi->max_bits_per_word = mbits + 1;
0584 
0585     mpc8xxx_spi->native_chipselects = 0;
0586     if (SPCAP_SSEN(capabilities)) {
0587         mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
0588         mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
0589     }
0590     master->num_chipselect = mpc8xxx_spi->native_chipselects;
0591     pdata->cs_control = fsl_spi_grlib_cs_control;
0592 }
0593 
0594 static struct spi_master *fsl_spi_probe(struct device *dev,
0595         struct resource *mem, unsigned int irq)
0596 {
0597     struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0598     struct spi_master *master;
0599     struct mpc8xxx_spi *mpc8xxx_spi;
0600     struct fsl_spi_reg __iomem *reg_base;
0601     u32 regval;
0602     int ret = 0;
0603 
0604     master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
0605     if (master == NULL) {
0606         ret = -ENOMEM;
0607         goto err;
0608     }
0609 
0610     dev_set_drvdata(dev, master);
0611 
0612     mpc8xxx_spi_probe(dev, mem, irq);
0613 
0614     master->setup = fsl_spi_setup;
0615     master->cleanup = fsl_spi_cleanup;
0616     master->transfer_one_message = fsl_spi_do_one_msg;
0617     master->use_gpio_descriptors = true;
0618 
0619     mpc8xxx_spi = spi_master_get_devdata(master);
0620     mpc8xxx_spi->max_bits_per_word = 32;
0621     mpc8xxx_spi->type = fsl_spi_get_type(dev);
0622 
0623     ret = fsl_spi_cpm_init(mpc8xxx_spi);
0624     if (ret)
0625         goto err_cpm_init;
0626 
0627     mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
0628     if (IS_ERR(mpc8xxx_spi->reg_base)) {
0629         ret = PTR_ERR(mpc8xxx_spi->reg_base);
0630         goto err_probe;
0631     }
0632 
0633     if (mpc8xxx_spi->type == TYPE_GRLIB)
0634         fsl_spi_grlib_probe(dev);
0635 
0636     master->bits_per_word_mask =
0637         (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
0638         SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
0639 
0640     if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
0641         mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
0642 
0643     if (mpc8xxx_spi->set_shifts)
0644         /* 8 bits per word and MSB first */
0645         mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
0646                     &mpc8xxx_spi->tx_shift, 8, 1);
0647 
0648     /* Register for SPI Interrupt */
0649     ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
0650                    0, "fsl_spi", mpc8xxx_spi);
0651 
0652     if (ret != 0)
0653         goto err_probe;
0654 
0655     reg_base = mpc8xxx_spi->reg_base;
0656 
0657     /* SPI controller initializations */
0658     mpc8xxx_spi_write_reg(&reg_base->mode, 0);
0659     mpc8xxx_spi_write_reg(&reg_base->mask, 0);
0660     mpc8xxx_spi_write_reg(&reg_base->command, 0);
0661     mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
0662 
0663     /* Enable SPI interface */
0664     regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
0665     if (mpc8xxx_spi->max_bits_per_word < 8) {
0666         regval &= ~SPMODE_LEN(0xF);
0667         regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
0668     }
0669     if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
0670         regval |= SPMODE_OP;
0671 
0672     mpc8xxx_spi_write_reg(&reg_base->mode, regval);
0673 
0674     ret = devm_spi_register_master(dev, master);
0675     if (ret < 0)
0676         goto err_probe;
0677 
0678     dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
0679          mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
0680 
0681     return master;
0682 
0683 err_probe:
0684     fsl_spi_cpm_free(mpc8xxx_spi);
0685 err_cpm_init:
0686     spi_master_put(master);
0687 err:
0688     return ERR_PTR(ret);
0689 }
0690 
0691 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
0692 {
0693     if (spi->cs_gpiod) {
0694         gpiod_set_value(spi->cs_gpiod, on);
0695     } else {
0696         struct device *dev = spi->dev.parent->parent;
0697         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0698         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
0699 
0700         if (WARN_ON_ONCE(!pinfo->immr_spi_cs))
0701             return;
0702         iowrite32be(on ? 0 : SPI_BOOT_SEL_BIT, pinfo->immr_spi_cs);
0703     }
0704 }
0705 
0706 static int of_fsl_spi_probe(struct platform_device *ofdev)
0707 {
0708     struct device *dev = &ofdev->dev;
0709     struct device_node *np = ofdev->dev.of_node;
0710     struct spi_master *master;
0711     struct resource mem;
0712     int irq, type;
0713     int ret;
0714     bool spisel_boot = false;
0715 #if IS_ENABLED(CONFIG_FSL_SOC)
0716     struct mpc8xxx_spi_probe_info *pinfo = NULL;
0717 #endif
0718 
0719 
0720     ret = of_mpc8xxx_spi_probe(ofdev);
0721     if (ret)
0722         return ret;
0723 
0724     type = fsl_spi_get_type(&ofdev->dev);
0725     if (type == TYPE_FSL) {
0726         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0727 #if IS_ENABLED(CONFIG_FSL_SOC)
0728         pinfo = to_of_pinfo(pdata);
0729 
0730         spisel_boot = of_property_read_bool(np, "fsl,spisel_boot");
0731         if (spisel_boot) {
0732             pinfo->immr_spi_cs = ioremap(get_immrbase() + IMMR_SPI_CS_OFFSET, 4);
0733             if (!pinfo->immr_spi_cs)
0734                 return -ENOMEM;
0735         }
0736 #endif
0737         /*
0738          * Handle the case where we have one hardwired (always selected)
0739          * device on the first "chipselect". Else we let the core code
0740          * handle any GPIOs or native chip selects and assign the
0741          * appropriate callback for dealing with the CS lines. This isn't
0742          * supported on the GRLIB variant.
0743          */
0744         ret = gpiod_count(dev, "cs");
0745         if (ret < 0)
0746             ret = 0;
0747         if (ret == 0 && !spisel_boot) {
0748             pdata->max_chipselect = 1;
0749         } else {
0750             pdata->max_chipselect = ret + spisel_boot;
0751             pdata->cs_control = fsl_spi_cs_control;
0752         }
0753     }
0754 
0755     ret = of_address_to_resource(np, 0, &mem);
0756     if (ret)
0757         goto unmap_out;
0758 
0759     irq = platform_get_irq(ofdev, 0);
0760     if (irq < 0) {
0761         ret = irq;
0762         goto unmap_out;
0763     }
0764 
0765     master = fsl_spi_probe(dev, &mem, irq);
0766 
0767     return PTR_ERR_OR_ZERO(master);
0768 
0769 unmap_out:
0770 #if IS_ENABLED(CONFIG_FSL_SOC)
0771     if (spisel_boot)
0772         iounmap(pinfo->immr_spi_cs);
0773 #endif
0774     return ret;
0775 }
0776 
0777 static int of_fsl_spi_remove(struct platform_device *ofdev)
0778 {
0779     struct spi_master *master = platform_get_drvdata(ofdev);
0780     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
0781 
0782     fsl_spi_cpm_free(mpc8xxx_spi);
0783     return 0;
0784 }
0785 
0786 static struct platform_driver of_fsl_spi_driver = {
0787     .driver = {
0788         .name = "fsl_spi",
0789         .of_match_table = of_fsl_spi_match,
0790     },
0791     .probe      = of_fsl_spi_probe,
0792     .remove     = of_fsl_spi_remove,
0793 };
0794 
0795 #ifdef CONFIG_MPC832x_RDB
0796 /*
0797  * XXX XXX XXX
0798  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
0799  * only. The driver should go away soon, since newer MPC8323E-RDB's device
0800  * tree can work with OpenFirmware driver. But for now we support old trees
0801  * as well.
0802  */
0803 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
0804 {
0805     struct resource *mem;
0806     int irq;
0807     struct spi_master *master;
0808 
0809     if (!dev_get_platdata(&pdev->dev))
0810         return -EINVAL;
0811 
0812     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0813     if (!mem)
0814         return -EINVAL;
0815 
0816     irq = platform_get_irq(pdev, 0);
0817     if (irq <= 0)
0818         return -EINVAL;
0819 
0820     master = fsl_spi_probe(&pdev->dev, mem, irq);
0821     return PTR_ERR_OR_ZERO(master);
0822 }
0823 
0824 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
0825 {
0826     struct spi_master *master = platform_get_drvdata(pdev);
0827     struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master);
0828 
0829     fsl_spi_cpm_free(mpc8xxx_spi);
0830 
0831     return 0;
0832 }
0833 
0834 MODULE_ALIAS("platform:mpc8xxx_spi");
0835 static struct platform_driver mpc8xxx_spi_driver = {
0836     .probe = plat_mpc8xxx_spi_probe,
0837     .remove = plat_mpc8xxx_spi_remove,
0838     .driver = {
0839         .name = "mpc8xxx_spi",
0840     },
0841 };
0842 
0843 static bool legacy_driver_failed;
0844 
0845 static void __init legacy_driver_register(void)
0846 {
0847     legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
0848 }
0849 
0850 static void __exit legacy_driver_unregister(void)
0851 {
0852     if (legacy_driver_failed)
0853         return;
0854     platform_driver_unregister(&mpc8xxx_spi_driver);
0855 }
0856 #else
0857 static void __init legacy_driver_register(void) {}
0858 static void __exit legacy_driver_unregister(void) {}
0859 #endif /* CONFIG_MPC832x_RDB */
0860 
0861 static int __init fsl_spi_init(void)
0862 {
0863     legacy_driver_register();
0864     return platform_driver_register(&of_fsl_spi_driver);
0865 }
0866 module_init(fsl_spi_init);
0867 
0868 static void __exit fsl_spi_exit(void)
0869 {
0870     platform_driver_unregister(&of_fsl_spi_driver);
0871     legacy_driver_unregister();
0872 }
0873 module_exit(fsl_spi_exit);
0874 
0875 MODULE_AUTHOR("Kumar Gala");
0876 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
0877 MODULE_LICENSE("GPL");