drivers/spi/spi-fsl-lpspi.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Freescale i.MX7ULP LPSPI driver
0004 //
0005 // Copyright 2016 Freescale Semiconductor, Inc.
0006 // Copyright 2018 NXP Semiconductors
0007
0008 #include <linux/clk.h>
0009 #include <linux/completion.h>
0010 #include <linux/delay.h>
0011 #include <linux/dmaengine.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/err.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/irq.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/of_device.h>
0021 #include <linux/pinctrl/consumer.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/dma/imx-dma.h>
0024 #include <linux/pm_runtime.h>
0025 #include <linux/slab.h>
0026 #include <linux/spi/spi.h>
0027 #include <linux/spi/spi_bitbang.h>
0028 #include <linux/types.h>
0029
0030 #define DRIVER_NAME "fsl_lpspi"
0031
0032 #define FSL_LPSPI_RPM_TIMEOUT 50 /* 50ms */
0033
0034 /* The maximum bytes that edma can transfer once.*/
0035 #define FSL_LPSPI_MAX_EDMA_BYTES  ((1 << 15) - 1)
0036
0037 /* i.MX7ULP LPSPI registers */
0038 #define IMX7ULP_VERID   0x0
0039 #define IMX7ULP_PARAM   0x4
0040 #define IMX7ULP_CR  0x10
0041 #define IMX7ULP_SR  0x14
0042 #define IMX7ULP_IER 0x18
0043 #define IMX7ULP_DER 0x1c
0044 #define IMX7ULP_CFGR0   0x20
0045 #define IMX7ULP_CFGR1   0x24
0046 #define IMX7ULP_DMR0    0x30
0047 #define IMX7ULP_DMR1    0x34
0048 #define IMX7ULP_CCR 0x40
0049 #define IMX7ULP_FCR 0x58
0050 #define IMX7ULP_FSR 0x5c
0051 #define IMX7ULP_TCR 0x60
0052 #define IMX7ULP_TDR 0x64
0053 #define IMX7ULP_RSR 0x70
0054 #define IMX7ULP_RDR 0x74
0055
0056 /* General control register field define */
0057 #define CR_RRF      BIT(9)
0058 #define CR_RTF      BIT(8)
0059 #define CR_RST      BIT(1)
0060 #define CR_MEN      BIT(0)
0061 #define SR_MBF      BIT(24)
0062 #define SR_TCF      BIT(10)
0063 #define SR_FCF      BIT(9)
0064 #define SR_RDF      BIT(1)
0065 #define SR_TDF      BIT(0)
0066 #define IER_TCIE    BIT(10)
0067 #define IER_FCIE    BIT(9)
0068 #define IER_RDIE    BIT(1)
0069 #define IER_TDIE    BIT(0)
0070 #define DER_RDDE    BIT(1)
0071 #define DER_TDDE    BIT(0)
0072 #define CFGR1_PCSCFG    BIT(27)
0073 #define CFGR1_PINCFG    (BIT(24)|BIT(25))
0074 #define CFGR1_PCSPOL    BIT(8)
0075 #define CFGR1_NOSTALL   BIT(3)
0076 #define CFGR1_MASTER    BIT(0)
0077 #define FSR_TXCOUNT (0xFF)
0078 #define RSR_RXEMPTY BIT(1)
0079 #define TCR_CPOL    BIT(31)
0080 #define TCR_CPHA    BIT(30)
0081 #define TCR_CONT    BIT(21)
0082 #define TCR_CONTC   BIT(20)
0083 #define TCR_RXMSK   BIT(19)
0084 #define TCR_TXMSK   BIT(18)
0085
0086 struct lpspi_config {
0087     u8 bpw;
0088     u8 chip_select;
0089     u8 prescale;
0090     u16 mode;
0091     u32 speed_hz;
0092 };
0093
0094 struct fsl_lpspi_data {
0095     struct device *dev;
0096     void __iomem *base;
0097     unsigned long base_phys;
0098     struct clk *clk_ipg;
0099     struct clk *clk_per;
0100     bool is_slave;
0101     bool is_only_cs1;
0102     bool is_first_byte;
0103
0104     void *rx_buf;
0105     const void *tx_buf;
0106     void (*tx)(struct fsl_lpspi_data *);
0107     void (*rx)(struct fsl_lpspi_data *);
0108
0109     u32 remain;
0110     u8 watermark;
0111     u8 txfifosize;
0112     u8 rxfifosize;
0113
0114     struct lpspi_config config;
0115     struct completion xfer_done;
0116
0117     bool slave_aborted;
0118
0119     /* DMA */
0120     bool usedma;
0121     struct completion dma_rx_completion;
0122     struct completion dma_tx_completion;
0123 };
0124
0125 static const struct of_device_id fsl_lpspi_dt_ids[] = {
0126     { .compatible = "fsl,imx7ulp-spi", },
0127     { /* sentinel */ }
0128 };
0129 MODULE_DEVICE_TABLE(of, fsl_lpspi_dt_ids);
0130
0131 #define LPSPI_BUF_RX(type)                      \
0132 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
0133 {                                   \
0134     unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR);    \
0135                                     \
0136     if (fsl_lpspi->rx_buf) {                    \
0137         *(type *)fsl_lpspi->rx_buf = val;           \
0138         fsl_lpspi->rx_buf += sizeof(type);                      \
0139     }                               \
0140 }
0141
0142 #define LPSPI_BUF_TX(type)                      \
0143 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi)   \
0144 {                                   \
0145     type val = 0;                           \
0146                                     \
0147     if (fsl_lpspi->tx_buf) {                    \
0148         val = *(type *)fsl_lpspi->tx_buf;           \
0149         fsl_lpspi->tx_buf += sizeof(type);          \
0150     }                               \
0151                                     \
0152     fsl_lpspi->remain -= sizeof(type);              \
0153     writel(val, fsl_lpspi->base + IMX7ULP_TDR);         \
0154 }
0155
0156 LPSPI_BUF_RX(u8)
0157 LPSPI_BUF_TX(u8)
0158 LPSPI_BUF_RX(u16)
0159 LPSPI_BUF_TX(u16)
0160 LPSPI_BUF_RX(u32)
0161 LPSPI_BUF_TX(u32)
0162
0163 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
0164                   unsigned int enable)
0165 {
0166     writel(enable, fsl_lpspi->base + IMX7ULP_IER);
0167 }
0168
0169 static int fsl_lpspi_bytes_per_word(const int bpw)
0170 {
0171     return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
0172 }
0173
0174 static bool fsl_lpspi_can_dma(struct spi_controller *controller,
0175                   struct spi_device *spi,
0176                   struct spi_transfer *transfer)
0177 {
0178     unsigned int bytes_per_word;
0179
0180     if (!controller->dma_rx)
0181         return false;
0182
0183     bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word);
0184
0185     switch (bytes_per_word) {
0186     case 1:
0187     case 2:
0188     case 4:
0189         break;
0190     default:
0191         return false;
0192     }
0193
0194     return true;
0195 }
0196
0197 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller)
0198 {
0199     struct fsl_lpspi_data *fsl_lpspi =
0200                 spi_controller_get_devdata(controller);
0201     int ret;
0202
0203     ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
0204     if (ret < 0) {
0205         dev_err(fsl_lpspi->dev, "failed to enable clock\n");
0206         return ret;
0207     }
0208
0209     return 0;
0210 }
0211
0212 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller)
0213 {
0214     struct fsl_lpspi_data *fsl_lpspi =
0215                 spi_controller_get_devdata(controller);
0216
0217     pm_runtime_mark_last_busy(fsl_lpspi->dev);
0218     pm_runtime_put_autosuspend(fsl_lpspi->dev);
0219
0220     return 0;
0221 }
0222
0223 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
0224 {
0225     u8 txfifo_cnt;
0226     u32 temp;
0227
0228     txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
0229
0230     while (txfifo_cnt < fsl_lpspi->txfifosize) {
0231         if (!fsl_lpspi->remain)
0232             break;
0233         fsl_lpspi->tx(fsl_lpspi);
0234         txfifo_cnt++;
0235     }
0236
0237     if (txfifo_cnt < fsl_lpspi->txfifosize) {
0238         if (!fsl_lpspi->is_slave) {
0239             temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
0240             temp &= ~TCR_CONTC;
0241             writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
0242         }
0243
0244         fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
0245     } else
0246         fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
0247 }
0248
0249 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
0250 {
0251     while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
0252         fsl_lpspi->rx(fsl_lpspi);
0253 }
0254
0255 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
0256 {
0257     u32 temp = 0;
0258
0259     temp |= fsl_lpspi->config.bpw - 1;
0260     temp |= (fsl_lpspi->config.mode & 0x3) << 30;
0261     temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
0262     if (!fsl_lpspi->is_slave) {
0263         temp |= fsl_lpspi->config.prescale << 27;
0264         /*
0265          * Set TCR_CONT will keep SS asserted after current transfer.
0266          * For the first transfer, clear TCR_CONTC to assert SS.
0267          * For subsequent transfer, set TCR_CONTC to keep SS asserted.
0268          */
0269         if (!fsl_lpspi->usedma) {
0270             temp |= TCR_CONT;
0271             if (fsl_lpspi->is_first_byte)
0272                 temp &= ~TCR_CONTC;
0273             else
0274                 temp |= TCR_CONTC;
0275         }
0276     }
0277     writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
0278
0279     dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
0280 }
0281
0282 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
0283 {
0284     u32 temp;
0285
0286     if (!fsl_lpspi->usedma)
0287         temp = fsl_lpspi->watermark >> 1 |
0288                (fsl_lpspi->watermark >> 1) << 16;
0289     else
0290         temp = fsl_lpspi->watermark >> 1;
0291
0292     writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
0293
0294     dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
0295 }
0296
0297 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
0298 {
0299     struct lpspi_config config = fsl_lpspi->config;
0300     unsigned int perclk_rate, scldiv;
0301     u8 prescale;
0302
0303     perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
0304
0305     if (config.speed_hz > perclk_rate / 2) {
0306         dev_err(fsl_lpspi->dev,
0307               "per-clk should be at least two times of transfer speed");
0308         return -EINVAL;
0309     }
0310
0311     for (prescale = 0; prescale < 8; prescale++) {
0312         scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2;
0313         if (scldiv < 256) {
0314             fsl_lpspi->config.prescale = prescale;
0315             break;
0316         }
0317     }
0318
0319     if (scldiv >= 256)
0320         return -EINVAL;
0321
0322     writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16),
0323                     fsl_lpspi->base + IMX7ULP_CCR);
0324
0325     dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
0326         perclk_rate, config.speed_hz, prescale, scldiv);
0327
0328     return 0;
0329 }
0330
0331 static int fsl_lpspi_dma_configure(struct spi_controller *controller)
0332 {
0333     int ret;
0334     enum dma_slave_buswidth buswidth;
0335     struct dma_slave_config rx = {}, tx = {};
0336     struct fsl_lpspi_data *fsl_lpspi =
0337                 spi_controller_get_devdata(controller);
0338
0339     switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
0340     case 4:
0341         buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
0342         break;
0343     case 2:
0344         buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
0345         break;
0346     case 1:
0347         buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
0348         break;
0349     default:
0350         return -EINVAL;
0351     }
0352
0353     tx.direction = DMA_MEM_TO_DEV;
0354     tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
0355     tx.dst_addr_width = buswidth;
0356     tx.dst_maxburst = 1;
0357     ret = dmaengine_slave_config(controller->dma_tx, &tx);
0358     if (ret) {
0359         dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
0360             ret);
0361         return ret;
0362     }
0363
0364     rx.direction = DMA_DEV_TO_MEM;
0365     rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
0366     rx.src_addr_width = buswidth;
0367     rx.src_maxburst = 1;
0368     ret = dmaengine_slave_config(controller->dma_rx, &rx);
0369     if (ret) {
0370         dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
0371             ret);
0372         return ret;
0373     }
0374
0375     return 0;
0376 }
0377
0378 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
0379 {
0380     u32 temp;
0381     int ret;
0382
0383     if (!fsl_lpspi->is_slave) {
0384         ret = fsl_lpspi_set_bitrate(fsl_lpspi);
0385         if (ret)
0386             return ret;
0387     }
0388
0389     fsl_lpspi_set_watermark(fsl_lpspi);
0390
0391     if (!fsl_lpspi->is_slave)
0392         temp = CFGR1_MASTER;
0393     else
0394         temp = CFGR1_PINCFG;
0395     if (fsl_lpspi->config.mode & SPI_CS_HIGH)
0396         temp |= CFGR1_PCSPOL;
0397     writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
0398
0399     temp = readl(fsl_lpspi->base + IMX7ULP_CR);
0400     temp |= CR_RRF | CR_RTF | CR_MEN;
0401     writel(temp, fsl_lpspi->base + IMX7ULP_CR);
0402
0403     temp = 0;
0404     if (fsl_lpspi->usedma)
0405         temp = DER_TDDE | DER_RDDE;
0406     writel(temp, fsl_lpspi->base + IMX7ULP_DER);
0407
0408     return 0;
0409 }
0410
0411 static int fsl_lpspi_setup_transfer(struct spi_controller *controller,
0412                      struct spi_device *spi,
0413                      struct spi_transfer *t)
0414 {
0415     struct fsl_lpspi_data *fsl_lpspi =
0416                 spi_controller_get_devdata(spi->controller);
0417
0418     if (t == NULL)
0419         return -EINVAL;
0420
0421     fsl_lpspi->config.mode = spi->mode;
0422     fsl_lpspi->config.bpw = t->bits_per_word;
0423     fsl_lpspi->config.speed_hz = t->speed_hz;
0424     if (fsl_lpspi->is_only_cs1)
0425         fsl_lpspi->config.chip_select = 1;
0426     else
0427         fsl_lpspi->config.chip_select = spi->chip_select;
0428
0429     if (!fsl_lpspi->config.speed_hz)
0430         fsl_lpspi->config.speed_hz = spi->max_speed_hz;
0431     if (!fsl_lpspi->config.bpw)
0432         fsl_lpspi->config.bpw = spi->bits_per_word;
0433
0434     /* Initialize the functions for transfer */
0435     if (fsl_lpspi->config.bpw <= 8) {
0436         fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
0437         fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
0438     } else if (fsl_lpspi->config.bpw <= 16) {
0439         fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
0440         fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
0441     } else {
0442         fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
0443         fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
0444     }
0445
0446     if (t->len <= fsl_lpspi->txfifosize)
0447         fsl_lpspi->watermark = t->len;
0448     else
0449         fsl_lpspi->watermark = fsl_lpspi->txfifosize;
0450
0451     if (fsl_lpspi_can_dma(controller, spi, t))
0452         fsl_lpspi->usedma = true;
0453     else
0454         fsl_lpspi->usedma = false;
0455
0456     return fsl_lpspi_config(fsl_lpspi);
0457 }
0458
0459 static int fsl_lpspi_slave_abort(struct spi_controller *controller)
0460 {
0461     struct fsl_lpspi_data *fsl_lpspi =
0462                 spi_controller_get_devdata(controller);
0463
0464     fsl_lpspi->slave_aborted = true;
0465     if (!fsl_lpspi->usedma)
0466         complete(&fsl_lpspi->xfer_done);
0467     else {
0468         complete(&fsl_lpspi->dma_tx_completion);
0469         complete(&fsl_lpspi->dma_rx_completion);
0470     }
0471
0472     return 0;
0473 }
0474
0475 static int fsl_lpspi_wait_for_completion(struct spi_controller *controller)
0476 {
0477     struct fsl_lpspi_data *fsl_lpspi =
0478                 spi_controller_get_devdata(controller);
0479
0480     if (fsl_lpspi->is_slave) {
0481         if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
0482             fsl_lpspi->slave_aborted) {
0483             dev_dbg(fsl_lpspi->dev, "interrupted\n");
0484             return -EINTR;
0485         }
0486     } else {
0487         if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
0488             dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
0489             return -ETIMEDOUT;
0490         }
0491     }
0492
0493     return 0;
0494 }
0495
0496 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
0497 {
0498     u32 temp;
0499
0500     if (!fsl_lpspi->usedma) {
0501         /* Disable all interrupt */
0502         fsl_lpspi_intctrl(fsl_lpspi, 0);
0503     }
0504
0505     /* W1C for all flags in SR */
0506     temp = 0x3F << 8;
0507     writel(temp, fsl_lpspi->base + IMX7ULP_SR);
0508
0509     /* Clear FIFO and disable module */
0510     temp = CR_RRF | CR_RTF;
0511     writel(temp, fsl_lpspi->base + IMX7ULP_CR);
0512
0513     return 0;
0514 }
0515
0516 static void fsl_lpspi_dma_rx_callback(void *cookie)
0517 {
0518     struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
0519
0520     complete(&fsl_lpspi->dma_rx_completion);
0521 }
0522
0523 static void fsl_lpspi_dma_tx_callback(void *cookie)
0524 {
0525     struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
0526
0527     complete(&fsl_lpspi->dma_tx_completion);
0528 }
0529
0530 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
0531                        int size)
0532 {
0533     unsigned long timeout = 0;
0534
0535     /* Time with actual data transfer and CS change delay related to HW */
0536     timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
0537
0538     /* Add extra second for scheduler related activities */
0539     timeout += 1;
0540
0541     /* Double calculated timeout */
0542     return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
0543 }
0544
0545 static int fsl_lpspi_dma_transfer(struct spi_controller *controller,
0546                 struct fsl_lpspi_data *fsl_lpspi,
0547                 struct spi_transfer *transfer)
0548 {
0549     struct dma_async_tx_descriptor *desc_tx, *desc_rx;
0550     unsigned long transfer_timeout;
0551     unsigned long timeout;
0552     struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
0553     int ret;
0554
0555     ret = fsl_lpspi_dma_configure(controller);
0556     if (ret)
0557         return ret;
0558
0559     desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
0560                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
0561                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0562     if (!desc_rx)
0563         return -EINVAL;
0564
0565     desc_rx->callback = fsl_lpspi_dma_rx_callback;
0566     desc_rx->callback_param = (void *)fsl_lpspi;
0567     dmaengine_submit(desc_rx);
0568     reinit_completion(&fsl_lpspi->dma_rx_completion);
0569     dma_async_issue_pending(controller->dma_rx);
0570
0571     desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
0572                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
0573                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0574     if (!desc_tx) {
0575         dmaengine_terminate_all(controller->dma_tx);
0576         return -EINVAL;
0577     }
0578
0579     desc_tx->callback = fsl_lpspi_dma_tx_callback;
0580     desc_tx->callback_param = (void *)fsl_lpspi;
0581     dmaengine_submit(desc_tx);
0582     reinit_completion(&fsl_lpspi->dma_tx_completion);
0583     dma_async_issue_pending(controller->dma_tx);
0584
0585     fsl_lpspi->slave_aborted = false;
0586
0587     if (!fsl_lpspi->is_slave) {
0588         transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
0589                                    transfer->len);
0590
0591         /* Wait eDMA to finish the data transfer.*/
0592         timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
0593                               transfer_timeout);
0594         if (!timeout) {
0595             dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
0596             dmaengine_terminate_all(controller->dma_tx);
0597             dmaengine_terminate_all(controller->dma_rx);
0598             fsl_lpspi_reset(fsl_lpspi);
0599             return -ETIMEDOUT;
0600         }
0601
0602         timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
0603                               transfer_timeout);
0604         if (!timeout) {
0605             dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
0606             dmaengine_terminate_all(controller->dma_tx);
0607             dmaengine_terminate_all(controller->dma_rx);
0608             fsl_lpspi_reset(fsl_lpspi);
0609             return -ETIMEDOUT;
0610         }
0611     } else {
0612         if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
0613             fsl_lpspi->slave_aborted) {
0614             dev_dbg(fsl_lpspi->dev,
0615                 "I/O Error in DMA TX interrupted\n");
0616             dmaengine_terminate_all(controller->dma_tx);
0617             dmaengine_terminate_all(controller->dma_rx);
0618             fsl_lpspi_reset(fsl_lpspi);
0619             return -EINTR;
0620         }
0621
0622         if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
0623             fsl_lpspi->slave_aborted) {
0624             dev_dbg(fsl_lpspi->dev,
0625                 "I/O Error in DMA RX interrupted\n");
0626             dmaengine_terminate_all(controller->dma_tx);
0627             dmaengine_terminate_all(controller->dma_rx);
0628             fsl_lpspi_reset(fsl_lpspi);
0629             return -EINTR;
0630         }
0631     }
0632
0633     fsl_lpspi_reset(fsl_lpspi);
0634
0635     return 0;
0636 }
0637
0638 static void fsl_lpspi_dma_exit(struct spi_controller *controller)
0639 {
0640     if (controller->dma_rx) {
0641         dma_release_channel(controller->dma_rx);
0642         controller->dma_rx = NULL;
0643     }
0644
0645     if (controller->dma_tx) {
0646         dma_release_channel(controller->dma_tx);
0647         controller->dma_tx = NULL;
0648     }
0649 }
0650
0651 static int fsl_lpspi_dma_init(struct device *dev,
0652                   struct fsl_lpspi_data *fsl_lpspi,
0653                   struct spi_controller *controller)
0654 {
0655     int ret;
0656
0657     /* Prepare for TX DMA: */
0658     controller->dma_tx = dma_request_chan(dev, "tx");
0659     if (IS_ERR(controller->dma_tx)) {
0660         ret = PTR_ERR(controller->dma_tx);
0661         dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
0662         controller->dma_tx = NULL;
0663         goto err;
0664     }
0665
0666     /* Prepare for RX DMA: */
0667     controller->dma_rx = dma_request_chan(dev, "rx");
0668     if (IS_ERR(controller->dma_rx)) {
0669         ret = PTR_ERR(controller->dma_rx);
0670         dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
0671         controller->dma_rx = NULL;
0672         goto err;
0673     }
0674
0675     init_completion(&fsl_lpspi->dma_rx_completion);
0676     init_completion(&fsl_lpspi->dma_tx_completion);
0677     controller->can_dma = fsl_lpspi_can_dma;
0678     controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES;
0679
0680     return 0;
0681 err:
0682     fsl_lpspi_dma_exit(controller);
0683     return ret;
0684 }
0685
0686 static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
0687                   struct spi_transfer *t)
0688 {
0689     struct fsl_lpspi_data *fsl_lpspi =
0690                 spi_controller_get_devdata(controller);
0691     int ret;
0692
0693     fsl_lpspi->tx_buf = t->tx_buf;
0694     fsl_lpspi->rx_buf = t->rx_buf;
0695     fsl_lpspi->remain = t->len;
0696
0697     reinit_completion(&fsl_lpspi->xfer_done);
0698     fsl_lpspi->slave_aborted = false;
0699
0700     fsl_lpspi_write_tx_fifo(fsl_lpspi);
0701
0702     ret = fsl_lpspi_wait_for_completion(controller);
0703     if (ret)
0704         return ret;
0705
0706     fsl_lpspi_reset(fsl_lpspi);
0707
0708     return 0;
0709 }
0710
0711 static int fsl_lpspi_transfer_one(struct spi_controller *controller,
0712                   struct spi_device *spi,
0713                   struct spi_transfer *t)
0714 {
0715     struct fsl_lpspi_data *fsl_lpspi =
0716                     spi_controller_get_devdata(controller);
0717     int ret;
0718
0719     fsl_lpspi->is_first_byte = true;
0720     ret = fsl_lpspi_setup_transfer(controller, spi, t);
0721     if (ret < 0)
0722         return ret;
0723
0724     fsl_lpspi_set_cmd(fsl_lpspi);
0725     fsl_lpspi->is_first_byte = false;
0726
0727     if (fsl_lpspi->usedma)
0728         ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
0729     else
0730         ret = fsl_lpspi_pio_transfer(controller, t);
0731     if (ret < 0)
0732         return ret;
0733
0734     return 0;
0735 }
0736
0737 static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
0738 {
0739     u32 temp_SR, temp_IER;
0740     struct fsl_lpspi_data *fsl_lpspi = dev_id;
0741
0742     temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
0743     fsl_lpspi_intctrl(fsl_lpspi, 0);
0744     temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
0745
0746     fsl_lpspi_read_rx_fifo(fsl_lpspi);
0747
0748     if ((temp_SR & SR_TDF) && (temp_IER & IER_TDIE)) {
0749         fsl_lpspi_write_tx_fifo(fsl_lpspi);
0750         return IRQ_HANDLED;
0751     }
0752
0753     if (temp_SR & SR_MBF ||
0754         readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
0755         writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
0756         fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
0757         return IRQ_HANDLED;
0758     }
0759
0760     if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
0761         writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
0762         complete(&fsl_lpspi->xfer_done);
0763         return IRQ_HANDLED;
0764     }
0765
0766     return IRQ_NONE;
0767 }
0768
0769 #ifdef CONFIG_PM
0770 static int fsl_lpspi_runtime_resume(struct device *dev)
0771 {
0772     struct spi_controller *controller = dev_get_drvdata(dev);
0773     struct fsl_lpspi_data *fsl_lpspi;
0774     int ret;
0775
0776     fsl_lpspi = spi_controller_get_devdata(controller);
0777
0778     ret = clk_prepare_enable(fsl_lpspi->clk_per);
0779     if (ret)
0780         return ret;
0781
0782     ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
0783     if (ret) {
0784         clk_disable_unprepare(fsl_lpspi->clk_per);
0785         return ret;
0786     }
0787
0788     return 0;
0789 }
0790
0791 static int fsl_lpspi_runtime_suspend(struct device *dev)
0792 {
0793     struct spi_controller *controller = dev_get_drvdata(dev);
0794     struct fsl_lpspi_data *fsl_lpspi;
0795
0796     fsl_lpspi = spi_controller_get_devdata(controller);
0797
0798     clk_disable_unprepare(fsl_lpspi->clk_per);
0799     clk_disable_unprepare(fsl_lpspi->clk_ipg);
0800
0801     return 0;
0802 }
0803 #endif
0804
0805 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
0806 {
0807     struct device *dev = fsl_lpspi->dev;
0808
0809     pm_runtime_enable(dev);
0810     pm_runtime_set_autosuspend_delay(dev, FSL_LPSPI_RPM_TIMEOUT);
0811     pm_runtime_use_autosuspend(dev);
0812
0813     return 0;
0814 }
0815
0816 static int fsl_lpspi_probe(struct platform_device *pdev)
0817 {
0818     struct fsl_lpspi_data *fsl_lpspi;
0819     struct spi_controller *controller;
0820     struct resource *res;
0821     int ret, irq;
0822     u32 temp;
0823     bool is_slave;
0824
0825     is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave");
0826     if (is_slave)
0827         controller = spi_alloc_slave(&pdev->dev,
0828                     sizeof(struct fsl_lpspi_data));
0829     else
0830         controller = spi_alloc_master(&pdev->dev,
0831                     sizeof(struct fsl_lpspi_data));
0832
0833     if (!controller)
0834         return -ENOMEM;
0835
0836     platform_set_drvdata(pdev, controller);
0837
0838     fsl_lpspi = spi_controller_get_devdata(controller);
0839     fsl_lpspi->dev = &pdev->dev;
0840     fsl_lpspi->is_slave = is_slave;
0841     fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
0842                         "fsl,spi-only-use-cs1-sel");
0843
0844     controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
0845     controller->transfer_one = fsl_lpspi_transfer_one;
0846     controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware;
0847     controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware;
0848     controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
0849     controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
0850     controller->dev.of_node = pdev->dev.of_node;
0851     controller->bus_num = pdev->id;
0852     controller->slave_abort = fsl_lpspi_slave_abort;
0853     if (!fsl_lpspi->is_slave)
0854         controller->use_gpio_descriptors = true;
0855
0856     init_completion(&fsl_lpspi->xfer_done);
0857
0858     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0859     fsl_lpspi->base = devm_ioremap_resource(&pdev->dev, res);
0860     if (IS_ERR(fsl_lpspi->base)) {
0861         ret = PTR_ERR(fsl_lpspi->base);
0862         goto out_controller_put;
0863     }
0864     fsl_lpspi->base_phys = res->start;
0865
0866     irq = platform_get_irq(pdev, 0);
0867     if (irq < 0) {
0868         ret = irq;
0869         goto out_controller_put;
0870     }
0871
0872     ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0,
0873                    dev_name(&pdev->dev), fsl_lpspi);
0874     if (ret) {
0875         dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
0876         goto out_controller_put;
0877     }
0878
0879     fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
0880     if (IS_ERR(fsl_lpspi->clk_per)) {
0881         ret = PTR_ERR(fsl_lpspi->clk_per);
0882         goto out_controller_put;
0883     }
0884
0885     fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
0886     if (IS_ERR(fsl_lpspi->clk_ipg)) {
0887         ret = PTR_ERR(fsl_lpspi->clk_ipg);
0888         goto out_controller_put;
0889     }
0890
0891     /* enable the clock */
0892     ret = fsl_lpspi_init_rpm(fsl_lpspi);
0893     if (ret)
0894         goto out_controller_put;
0895
0896     ret = pm_runtime_get_sync(fsl_lpspi->dev);
0897     if (ret < 0) {
0898         dev_err(fsl_lpspi->dev, "failed to enable clock\n");
0899         goto out_pm_get;
0900     }
0901
0902     temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
0903     fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
0904     fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
0905
0906     ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
0907     if (ret == -EPROBE_DEFER)
0908         goto out_pm_get;
0909
0910     if (ret < 0)
0911         dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret);
0912
0913     ret = devm_spi_register_controller(&pdev->dev, controller);
0914     if (ret < 0) {
0915         dev_err_probe(&pdev->dev, ret, "spi_register_controller error: %i\n", ret);
0916         goto free_dma;
0917     }
0918
0919     pm_runtime_mark_last_busy(fsl_lpspi->dev);
0920     pm_runtime_put_autosuspend(fsl_lpspi->dev);
0921
0922     return 0;
0923
0924 free_dma:
0925     fsl_lpspi_dma_exit(controller);
0926 out_pm_get:
0927     pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
0928     pm_runtime_put_sync(fsl_lpspi->dev);
0929     pm_runtime_disable(fsl_lpspi->dev);
0930 out_controller_put:
0931     spi_controller_put(controller);
0932
0933     return ret;
0934 }
0935
0936 static int fsl_lpspi_remove(struct platform_device *pdev)
0937 {
0938     struct spi_controller *controller = platform_get_drvdata(pdev);
0939     struct fsl_lpspi_data *fsl_lpspi =
0940                 spi_controller_get_devdata(controller);
0941
0942     fsl_lpspi_dma_exit(controller);
0943
0944     pm_runtime_disable(fsl_lpspi->dev);
0945     return 0;
0946 }
0947
0948 static int __maybe_unused fsl_lpspi_suspend(struct device *dev)
0949 {
0950     int ret;
0951
0952     pinctrl_pm_select_sleep_state(dev);
0953     ret = pm_runtime_force_suspend(dev);
0954     return ret;
0955 }
0956
0957 static int __maybe_unused fsl_lpspi_resume(struct device *dev)
0958 {
0959     int ret;
0960
0961     ret = pm_runtime_force_resume(dev);
0962     if (ret) {
0963         dev_err(dev, "Error in resume: %d\n", ret);
0964         return ret;
0965     }
0966
0967     pinctrl_pm_select_default_state(dev);
0968
0969     return 0;
0970 }
0971
0972 static const struct dev_pm_ops fsl_lpspi_pm_ops = {
0973     SET_RUNTIME_PM_OPS(fsl_lpspi_runtime_suspend,
0974                 fsl_lpspi_runtime_resume, NULL)
0975     SET_SYSTEM_SLEEP_PM_OPS(fsl_lpspi_suspend, fsl_lpspi_resume)
0976 };
0977
0978 static struct platform_driver fsl_lpspi_driver = {
0979     .driver = {
0980         .name = DRIVER_NAME,
0981         .of_match_table = fsl_lpspi_dt_ids,
0982         .pm = &fsl_lpspi_pm_ops,
0983     },
0984     .probe = fsl_lpspi_probe,
0985     .remove = fsl_lpspi_remove,
0986 };
0987 module_platform_driver(fsl_lpspi_driver);
0988
0989 MODULE_DESCRIPTION("LPSPI Controller driver");
0990 MODULE_AUTHOR("Gao Pan <pandy.gao@nxp.com>");
0991 MODULE_LICENSE("GPL");