drivers/spi/spi-fsl-lib.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Freescale SPI/eSPI controller driver library.
0004  *
0005  * Maintainer: Kumar Gala
0006  *
0007  * Copyright 2010 Freescale Semiconductor, Inc.
0008  * Copyright (C) 2006 Polycom, Inc.
0009  *
0010  * CPM SPI and QE buffer descriptors mode support:
0011  * Copyright (c) 2009  MontaVista Software, Inc.
0012  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0013  */
0014 #ifndef __SPI_FSL_LIB_H__
0015 #define __SPI_FSL_LIB_H__
0016
0017 #include <asm/io.h>
0018
0019 /* SPI/eSPI Controller driver's private data. */
0020 struct mpc8xxx_spi {
0021     struct device *dev;
0022     void __iomem *reg_base;
0023
0024     /* rx & tx bufs from the spi_transfer */
0025     const void *tx;
0026     void *rx;
0027
0028     int subblock;
0029     struct spi_pram __iomem *pram;
0030 #ifdef CONFIG_FSL_SOC
0031     struct cpm_buf_desc __iomem *tx_bd;
0032     struct cpm_buf_desc __iomem *rx_bd;
0033 #endif
0034
0035     struct spi_transfer *xfer_in_progress;
0036
0037     /* dma addresses for CPM transfers */
0038     dma_addr_t tx_dma;
0039     dma_addr_t rx_dma;
0040     bool map_tx_dma;
0041     bool map_rx_dma;
0042
0043     dma_addr_t dma_dummy_tx;
0044     dma_addr_t dma_dummy_rx;
0045
0046     /* functions to deal with different sized buffers */
0047     void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
0048     u32(*get_tx) (struct mpc8xxx_spi *);
0049
0050     unsigned int count;
0051     unsigned int irq;
0052
0053     unsigned nsecs;     /* (clock cycle time)/2 */
0054
0055     u32 spibrg;     /* SPIBRG input clock */
0056     u32 rx_shift;       /* RX data reg shift when in qe mode */
0057     u32 tx_shift;       /* TX data reg shift when in qe mode */
0058
0059     unsigned int flags;
0060
0061 #if IS_ENABLED(CONFIG_SPI_FSL_SPI)
0062     int type;
0063     int native_chipselects;
0064     u8 max_bits_per_word;
0065
0066     void (*set_shifts)(u32 *rx_shift, u32 *tx_shift,
0067                int bits_per_word, int msb_first);
0068 #endif
0069
0070     struct completion done;
0071 };
0072
0073 struct spi_mpc8xxx_cs {
0074     /* functions to deal with different sized buffers */
0075     void (*get_rx) (u32 rx_data, struct mpc8xxx_spi *);
0076     u32 (*get_tx) (struct mpc8xxx_spi *);
0077     u32 rx_shift;       /* RX data reg shift when in qe mode */
0078     u32 tx_shift;       /* TX data reg shift when in qe mode */
0079     u32 hw_mode;        /* Holds HW mode register settings */
0080 };
0081
0082 static inline void mpc8xxx_spi_write_reg(__be32 __iomem *reg, u32 val)
0083 {
0084     iowrite32be(val, reg);
0085 }
0086
0087 static inline u32 mpc8xxx_spi_read_reg(__be32 __iomem *reg)
0088 {
0089     return ioread32be(reg);
0090 }
0091
0092 struct mpc8xxx_spi_probe_info {
0093     struct fsl_spi_platform_data pdata;
0094     __be32 __iomem *immr_spi_cs;
0095 };
0096
0097 extern u32 mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi *mpc8xxx_spi);
0098 extern u32 mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi *mpc8xxx_spi);
0099 extern u32 mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi *mpc8xxx_spi);
0100 extern void mpc8xxx_spi_rx_buf_u8(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
0101 extern void mpc8xxx_spi_rx_buf_u16(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
0102 extern void mpc8xxx_spi_rx_buf_u32(u32 data, struct mpc8xxx_spi *mpc8xxx_spi);
0103
0104 extern struct mpc8xxx_spi_probe_info *to_of_pinfo(
0105         struct fsl_spi_platform_data *pdata);
0106 extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi *mspi,
0107         struct spi_transfer *t, unsigned int len);
0108 extern const char *mpc8xxx_spi_strmode(unsigned int flags);
0109 extern void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
0110         unsigned int irq);
0111 extern int mpc8xxx_spi_remove(struct device *dev);
0112 extern int of_mpc8xxx_spi_probe(struct platform_device *ofdev);
0113
0114 #endif /* __SPI_FSL_LIB_H__ */