drivers/spi/spi-fsl-lib.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale SPI/eSPI controller driver library.
0004  *
0005  * Maintainer: Kumar Gala
0006  *
0007  * Copyright (C) 2006 Polycom, Inc.
0008  *
0009  * CPM SPI and QE buffer descriptors mode support:
0010  * Copyright (c) 2009  MontaVista Software, Inc.
0011  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0012  *
0013  * Copyright 2010 Freescale Semiconductor, Inc.
0014  */
0015 #include <linux/dma-mapping.h>
0016 #include <linux/fsl_devices.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/kernel.h>
0019 #include <linux/mm.h>
0020 #include <linux/module.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/spi/spi.h>
0023 #ifdef CONFIG_FSL_SOC
0024 #include <sysdev/fsl_soc.h>
0025 #endif
0026
0027 #include "spi-fsl-lib.h"
0028
0029 #define MPC8XXX_SPI_RX_BUF(type)                      \
0030 void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
0031 {                                     \
0032     type *rx = mpc8xxx_spi->rx;                   \
0033     *rx++ = (type)(data >> mpc8xxx_spi->rx_shift);            \
0034     mpc8xxx_spi->rx = rx;                         \
0035 }                                     \
0036 EXPORT_SYMBOL_GPL(mpc8xxx_spi_rx_buf_##type);
0037
0038 #define MPC8XXX_SPI_TX_BUF(type)                \
0039 u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi)  \
0040 {                               \
0041     u32 data;                       \
0042     const type *tx = mpc8xxx_spi->tx;           \
0043     if (!tx)                        \
0044         return 0;                   \
0045     data = *tx++ << mpc8xxx_spi->tx_shift;          \
0046     mpc8xxx_spi->tx = tx;                   \
0047     return data;                        \
0048 }                               \
0049 EXPORT_SYMBOL_GPL(mpc8xxx_spi_tx_buf_##type);
0050
0051 MPC8XXX_SPI_RX_BUF(u8)
0052 MPC8XXX_SPI_RX_BUF(u16)
0053 MPC8XXX_SPI_RX_BUF(u32)
0054 MPC8XXX_SPI_TX_BUF(u8)
0055 MPC8XXX_SPI_TX_BUF(u16)
0056 MPC8XXX_SPI_TX_BUF(u32)
0057
0058 struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
0059 {
0060     return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
0061 }
0062 EXPORT_SYMBOL_GPL(to_of_pinfo);
0063
0064 const char *mpc8xxx_spi_strmode(unsigned int flags)
0065 {
0066     if (flags & SPI_QE_CPU_MODE) {
0067         return "QE CPU";
0068     } else if (flags & SPI_CPM_MODE) {
0069         if (flags & SPI_QE)
0070             return "QE";
0071         else if (flags & SPI_CPM2)
0072             return "CPM2";
0073         else
0074             return "CPM1";
0075     }
0076     return "CPU";
0077 }
0078 EXPORT_SYMBOL_GPL(mpc8xxx_spi_strmode);
0079
0080 void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
0081             unsigned int irq)
0082 {
0083     struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
0084     struct spi_master *master;
0085     struct mpc8xxx_spi *mpc8xxx_spi;
0086
0087     master = dev_get_drvdata(dev);
0088
0089     /* the spi->mode bits understood by this driver: */
0090     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
0091             | SPI_LSB_FIRST | SPI_LOOP;
0092
0093     master->dev.of_node = dev->of_node;
0094
0095     mpc8xxx_spi = spi_master_get_devdata(master);
0096     mpc8xxx_spi->dev = dev;
0097     mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
0098     mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
0099     mpc8xxx_spi->flags = pdata->flags;
0100     mpc8xxx_spi->spibrg = pdata->sysclk;
0101     mpc8xxx_spi->irq = irq;
0102
0103     mpc8xxx_spi->rx_shift = 0;
0104     mpc8xxx_spi->tx_shift = 0;
0105
0106     master->bus_num = pdata->bus_num;
0107     master->num_chipselect = pdata->max_chipselect;
0108
0109     init_completion(&mpc8xxx_spi->done);
0110 }
0111 EXPORT_SYMBOL_GPL(mpc8xxx_spi_probe);
0112
0113 int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
0114 {
0115     struct device *dev = &ofdev->dev;
0116     struct device_node *np = ofdev->dev.of_node;
0117     struct mpc8xxx_spi_probe_info *pinfo;
0118     struct fsl_spi_platform_data *pdata;
0119     const void *prop;
0120     int ret = -ENOMEM;
0121
0122     pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
0123     if (!pinfo)
0124         return ret;
0125
0126     pdata = &pinfo->pdata;
0127     dev->platform_data = pdata;
0128
0129     /* Allocate bus num dynamically. */
0130     pdata->bus_num = -1;
0131
0132 #ifdef CONFIG_FSL_SOC
0133     /* SPI controller is either clocked from QE or SoC clock. */
0134     pdata->sysclk = get_brgfreq();
0135     if (pdata->sysclk == -1) {
0136         pdata->sysclk = fsl_get_sys_freq();
0137         if (pdata->sysclk == -1)
0138             return -ENODEV;
0139     }
0140 #else
0141     ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
0142     if (ret)
0143         return ret;
0144 #endif
0145
0146     prop = of_get_property(np, "mode", NULL);
0147     if (prop && !strcmp(prop, "cpu-qe"))
0148         pdata->flags = SPI_QE_CPU_MODE;
0149     else if (prop && !strcmp(prop, "qe"))
0150         pdata->flags = SPI_CPM_MODE | SPI_QE;
0151     else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
0152         pdata->flags = SPI_CPM_MODE | SPI_CPM2;
0153     else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
0154         pdata->flags = SPI_CPM_MODE | SPI_CPM1;
0155
0156     return 0;
0157 }
0158 EXPORT_SYMBOL_GPL(of_mpc8xxx_spi_probe);
0159
0160 MODULE_LICENSE("GPL");