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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale eSPI controller driver.
0004  *
0005  * Copyright 2010 Freescale Semiconductor, Inc.
0006  */
0007 #include <linux/delay.h>
0008 #include <linux/err.h>
0009 #include <linux/fsl_devices.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/module.h>
0012 #include <linux/mm.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/pm_runtime.h>
0020 #include <sysdev/fsl_soc.h>
0021 
0022 /* eSPI Controller registers */
0023 #define ESPI_SPMODE 0x00    /* eSPI mode register */
0024 #define ESPI_SPIE   0x04    /* eSPI event register */
0025 #define ESPI_SPIM   0x08    /* eSPI mask register */
0026 #define ESPI_SPCOM  0x0c    /* eSPI command register */
0027 #define ESPI_SPITF  0x10    /* eSPI transmit FIFO access register*/
0028 #define ESPI_SPIRF  0x14    /* eSPI receive FIFO access register*/
0029 #define ESPI_SPMODE0    0x20    /* eSPI cs0 mode register */
0030 
0031 #define ESPI_SPMODEx(x) (ESPI_SPMODE0 + (x) * 4)
0032 
0033 /* eSPI Controller mode register definitions */
0034 #define SPMODE_ENABLE       BIT(31)
0035 #define SPMODE_LOOP     BIT(30)
0036 #define SPMODE_TXTHR(x)     ((x) << 8)
0037 #define SPMODE_RXTHR(x)     ((x) << 0)
0038 
0039 /* eSPI Controller CS mode register definitions */
0040 #define CSMODE_CI_INACTIVEHIGH  BIT(31)
0041 #define CSMODE_CP_BEGIN_EDGECLK BIT(30)
0042 #define CSMODE_REV      BIT(29)
0043 #define CSMODE_DIV16        BIT(28)
0044 #define CSMODE_PM(x)        ((x) << 24)
0045 #define CSMODE_POL_1        BIT(20)
0046 #define CSMODE_LEN(x)       ((x) << 16)
0047 #define CSMODE_BEF(x)       ((x) << 12)
0048 #define CSMODE_AFT(x)       ((x) << 8)
0049 #define CSMODE_CG(x)        ((x) << 3)
0050 
0051 #define FSL_ESPI_FIFO_SIZE  32
0052 #define FSL_ESPI_RXTHR      15
0053 
0054 /* Default mode/csmode for eSPI controller */
0055 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(FSL_ESPI_RXTHR))
0056 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
0057         | CSMODE_AFT(0) | CSMODE_CG(1))
0058 
0059 /* SPIE register values */
0060 #define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)
0061 #define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)
0062 #define SPIE_TXE        BIT(15) /* TX FIFO empty */
0063 #define SPIE_DON        BIT(14) /* TX done */
0064 #define SPIE_RXT        BIT(13) /* RX FIFO threshold */
0065 #define SPIE_RXF        BIT(12) /* RX FIFO full */
0066 #define SPIE_TXT        BIT(11) /* TX FIFO threshold*/
0067 #define SPIE_RNE        BIT(9)  /* RX FIFO not empty */
0068 #define SPIE_TNF        BIT(8)  /* TX FIFO not full */
0069 
0070 /* SPIM register values */
0071 #define SPIM_TXE        BIT(15) /* TX FIFO empty */
0072 #define SPIM_DON        BIT(14) /* TX done */
0073 #define SPIM_RXT        BIT(13) /* RX FIFO threshold */
0074 #define SPIM_RXF        BIT(12) /* RX FIFO full */
0075 #define SPIM_TXT        BIT(11) /* TX FIFO threshold*/
0076 #define SPIM_RNE        BIT(9)  /* RX FIFO not empty */
0077 #define SPIM_TNF        BIT(8)  /* TX FIFO not full */
0078 
0079 /* SPCOM register values */
0080 #define SPCOM_CS(x)     ((x) << 30)
0081 #define SPCOM_DO        BIT(28) /* Dual output */
0082 #define SPCOM_TO        BIT(27) /* TX only */
0083 #define SPCOM_RXSKIP(x)     ((x) << 16)
0084 #define SPCOM_TRANLEN(x)    ((x) << 0)
0085 
0086 #define SPCOM_TRANLEN_MAX   0x10000 /* Max transaction length */
0087 
0088 #define AUTOSUSPEND_TIMEOUT 2000
0089 
0090 struct fsl_espi {
0091     struct device *dev;
0092     void __iomem *reg_base;
0093 
0094     struct list_head *m_transfers;
0095     struct spi_transfer *tx_t;
0096     unsigned int tx_pos;
0097     bool tx_done;
0098     struct spi_transfer *rx_t;
0099     unsigned int rx_pos;
0100     bool rx_done;
0101 
0102     bool swab;
0103     unsigned int rxskip;
0104 
0105     spinlock_t lock;
0106 
0107     u32 spibrg;             /* SPIBRG input clock */
0108 
0109     struct completion done;
0110 };
0111 
0112 struct fsl_espi_cs {
0113     u32 hw_mode;
0114 };
0115 
0116 static inline u32 fsl_espi_read_reg(struct fsl_espi *espi, int offset)
0117 {
0118     return ioread32be(espi->reg_base + offset);
0119 }
0120 
0121 static inline u16 fsl_espi_read_reg16(struct fsl_espi *espi, int offset)
0122 {
0123     return ioread16be(espi->reg_base + offset);
0124 }
0125 
0126 static inline u8 fsl_espi_read_reg8(struct fsl_espi *espi, int offset)
0127 {
0128     return ioread8(espi->reg_base + offset);
0129 }
0130 
0131 static inline void fsl_espi_write_reg(struct fsl_espi *espi, int offset,
0132                       u32 val)
0133 {
0134     iowrite32be(val, espi->reg_base + offset);
0135 }
0136 
0137 static inline void fsl_espi_write_reg16(struct fsl_espi *espi, int offset,
0138                     u16 val)
0139 {
0140     iowrite16be(val, espi->reg_base + offset);
0141 }
0142 
0143 static inline void fsl_espi_write_reg8(struct fsl_espi *espi, int offset,
0144                        u8 val)
0145 {
0146     iowrite8(val, espi->reg_base + offset);
0147 }
0148 
0149 static int fsl_espi_check_message(struct spi_message *m)
0150 {
0151     struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
0152     struct spi_transfer *t, *first;
0153 
0154     if (m->frame_length > SPCOM_TRANLEN_MAX) {
0155         dev_err(espi->dev, "message too long, size is %u bytes\n",
0156             m->frame_length);
0157         return -EMSGSIZE;
0158     }
0159 
0160     first = list_first_entry(&m->transfers, struct spi_transfer,
0161                  transfer_list);
0162 
0163     list_for_each_entry(t, &m->transfers, transfer_list) {
0164         if (first->bits_per_word != t->bits_per_word ||
0165             first->speed_hz != t->speed_hz) {
0166             dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n");
0167             return -EINVAL;
0168         }
0169     }
0170 
0171     /* ESPI supports MSB-first transfers for word size 8 / 16 only */
0172     if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 &&
0173         first->bits_per_word != 16) {
0174         dev_err(espi->dev,
0175             "MSB-first transfer not supported for wordsize %u\n",
0176             first->bits_per_word);
0177         return -EINVAL;
0178     }
0179 
0180     return 0;
0181 }
0182 
0183 static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m)
0184 {
0185     struct spi_transfer *t;
0186     unsigned int i = 0, rxskip = 0;
0187 
0188     /*
0189      * prerequisites for ESPI rxskip mode:
0190      * - message has two transfers
0191      * - first transfer is a write and second is a read
0192      *
0193      * In addition the current low-level transfer mechanism requires
0194      * that the rxskip bytes fit into the TX FIFO. Else the transfer
0195      * would hang because after the first FSL_ESPI_FIFO_SIZE bytes
0196      * the TX FIFO isn't re-filled.
0197      */
0198     list_for_each_entry(t, &m->transfers, transfer_list) {
0199         if (i == 0) {
0200             if (!t->tx_buf || t->rx_buf ||
0201                 t->len > FSL_ESPI_FIFO_SIZE)
0202                 return 0;
0203             rxskip = t->len;
0204         } else if (i == 1) {
0205             if (t->tx_buf || !t->rx_buf)
0206                 return 0;
0207         }
0208         i++;
0209     }
0210 
0211     return i == 2 ? rxskip : 0;
0212 }
0213 
0214 static void fsl_espi_fill_tx_fifo(struct fsl_espi *espi, u32 events)
0215 {
0216     u32 tx_fifo_avail;
0217     unsigned int tx_left;
0218     const void *tx_buf;
0219 
0220     /* if events is zero transfer has not started and tx fifo is empty */
0221     tx_fifo_avail = events ? SPIE_TXCNT(events) :  FSL_ESPI_FIFO_SIZE;
0222 start:
0223     tx_left = espi->tx_t->len - espi->tx_pos;
0224     tx_buf = espi->tx_t->tx_buf;
0225     while (tx_fifo_avail >= min(4U, tx_left) && tx_left) {
0226         if (tx_left >= 4) {
0227             if (!tx_buf)
0228                 fsl_espi_write_reg(espi, ESPI_SPITF, 0);
0229             else if (espi->swab)
0230                 fsl_espi_write_reg(espi, ESPI_SPITF,
0231                     swahb32p(tx_buf + espi->tx_pos));
0232             else
0233                 fsl_espi_write_reg(espi, ESPI_SPITF,
0234                     *(u32 *)(tx_buf + espi->tx_pos));
0235             espi->tx_pos += 4;
0236             tx_left -= 4;
0237             tx_fifo_avail -= 4;
0238         } else if (tx_left >= 2 && tx_buf && espi->swab) {
0239             fsl_espi_write_reg16(espi, ESPI_SPITF,
0240                     swab16p(tx_buf + espi->tx_pos));
0241             espi->tx_pos += 2;
0242             tx_left -= 2;
0243             tx_fifo_avail -= 2;
0244         } else {
0245             if (!tx_buf)
0246                 fsl_espi_write_reg8(espi, ESPI_SPITF, 0);
0247             else
0248                 fsl_espi_write_reg8(espi, ESPI_SPITF,
0249                     *(u8 *)(tx_buf + espi->tx_pos));
0250             espi->tx_pos += 1;
0251             tx_left -= 1;
0252             tx_fifo_avail -= 1;
0253         }
0254     }
0255 
0256     if (!tx_left) {
0257         /* Last transfer finished, in rxskip mode only one is needed */
0258         if (list_is_last(&espi->tx_t->transfer_list,
0259             espi->m_transfers) || espi->rxskip) {
0260             espi->tx_done = true;
0261             return;
0262         }
0263         espi->tx_t = list_next_entry(espi->tx_t, transfer_list);
0264         espi->tx_pos = 0;
0265         /* continue with next transfer if tx fifo is not full */
0266         if (tx_fifo_avail)
0267             goto start;
0268     }
0269 }
0270 
0271 static void fsl_espi_read_rx_fifo(struct fsl_espi *espi, u32 events)
0272 {
0273     u32 rx_fifo_avail = SPIE_RXCNT(events);
0274     unsigned int rx_left;
0275     void *rx_buf;
0276 
0277 start:
0278     rx_left = espi->rx_t->len - espi->rx_pos;
0279     rx_buf = espi->rx_t->rx_buf;
0280     while (rx_fifo_avail >= min(4U, rx_left) && rx_left) {
0281         if (rx_left >= 4) {
0282             u32 val = fsl_espi_read_reg(espi, ESPI_SPIRF);
0283 
0284             if (rx_buf && espi->swab)
0285                 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val);
0286             else if (rx_buf)
0287                 *(u32 *)(rx_buf + espi->rx_pos) = val;
0288             espi->rx_pos += 4;
0289             rx_left -= 4;
0290             rx_fifo_avail -= 4;
0291         } else if (rx_left >= 2 && rx_buf && espi->swab) {
0292             u16 val = fsl_espi_read_reg16(espi, ESPI_SPIRF);
0293 
0294             *(u16 *)(rx_buf + espi->rx_pos) = swab16(val);
0295             espi->rx_pos += 2;
0296             rx_left -= 2;
0297             rx_fifo_avail -= 2;
0298         } else {
0299             u8 val = fsl_espi_read_reg8(espi, ESPI_SPIRF);
0300 
0301             if (rx_buf)
0302                 *(u8 *)(rx_buf + espi->rx_pos) = val;
0303             espi->rx_pos += 1;
0304             rx_left -= 1;
0305             rx_fifo_avail -= 1;
0306         }
0307     }
0308 
0309     if (!rx_left) {
0310         if (list_is_last(&espi->rx_t->transfer_list,
0311             espi->m_transfers)) {
0312             espi->rx_done = true;
0313             return;
0314         }
0315         espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
0316         espi->rx_pos = 0;
0317         /* continue with next transfer if rx fifo is not empty */
0318         if (rx_fifo_avail)
0319             goto start;
0320     }
0321 }
0322 
0323 static void fsl_espi_setup_transfer(struct spi_device *spi,
0324                     struct spi_transfer *t)
0325 {
0326     struct fsl_espi *espi = spi_master_get_devdata(spi->master);
0327     int bits_per_word = t ? t->bits_per_word : spi->bits_per_word;
0328     u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz;
0329     struct fsl_espi_cs *cs = spi_get_ctldata(spi);
0330     u32 hw_mode_old = cs->hw_mode;
0331 
0332     /* mask out bits we are going to set */
0333     cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
0334 
0335     cs->hw_mode |= CSMODE_LEN(bits_per_word - 1);
0336 
0337     pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1;
0338 
0339     if (pm > 15) {
0340         cs->hw_mode |= CSMODE_DIV16;
0341         pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1;
0342     }
0343 
0344     cs->hw_mode |= CSMODE_PM(pm);
0345 
0346     /* don't write the mode register if the mode doesn't change */
0347     if (cs->hw_mode != hw_mode_old)
0348         fsl_espi_write_reg(espi, ESPI_SPMODEx(spi->chip_select),
0349                    cs->hw_mode);
0350 }
0351 
0352 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
0353 {
0354     struct fsl_espi *espi = spi_master_get_devdata(spi->master);
0355     unsigned int rx_len = t->len;
0356     u32 mask, spcom;
0357     int ret;
0358 
0359     reinit_completion(&espi->done);
0360 
0361     /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
0362     spcom = SPCOM_CS(spi->chip_select);
0363     spcom |= SPCOM_TRANLEN(t->len - 1);
0364 
0365     /* configure RXSKIP mode */
0366     if (espi->rxskip) {
0367         spcom |= SPCOM_RXSKIP(espi->rxskip);
0368         rx_len = t->len - espi->rxskip;
0369         if (t->rx_nbits == SPI_NBITS_DUAL)
0370             spcom |= SPCOM_DO;
0371     }
0372 
0373     fsl_espi_write_reg(espi, ESPI_SPCOM, spcom);
0374 
0375     /* enable interrupts */
0376     mask = SPIM_DON;
0377     if (rx_len > FSL_ESPI_FIFO_SIZE)
0378         mask |= SPIM_RXT;
0379     fsl_espi_write_reg(espi, ESPI_SPIM, mask);
0380 
0381     /* Prevent filling the fifo from getting interrupted */
0382     spin_lock_irq(&espi->lock);
0383     fsl_espi_fill_tx_fifo(espi, 0);
0384     spin_unlock_irq(&espi->lock);
0385 
0386     /* Won't hang up forever, SPI bus sometimes got lost interrupts... */
0387     ret = wait_for_completion_timeout(&espi->done, 2 * HZ);
0388     if (ret == 0)
0389         dev_err(espi->dev, "Transfer timed out!\n");
0390 
0391     /* disable rx ints */
0392     fsl_espi_write_reg(espi, ESPI_SPIM, 0);
0393 
0394     return ret == 0 ? -ETIMEDOUT : 0;
0395 }
0396 
0397 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans)
0398 {
0399     struct fsl_espi *espi = spi_master_get_devdata(m->spi->master);
0400     struct spi_device *spi = m->spi;
0401     int ret;
0402 
0403     /* In case of LSB-first and bits_per_word > 8 byte-swap all words */
0404     espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8;
0405 
0406     espi->m_transfers = &m->transfers;
0407     espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer,
0408                       transfer_list);
0409     espi->tx_pos = 0;
0410     espi->tx_done = false;
0411     espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer,
0412                       transfer_list);
0413     espi->rx_pos = 0;
0414     espi->rx_done = false;
0415 
0416     espi->rxskip = fsl_espi_check_rxskip_mode(m);
0417     if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) {
0418         dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n");
0419         return -EINVAL;
0420     }
0421 
0422     /* In RXSKIP mode skip first transfer for reads */
0423     if (espi->rxskip)
0424         espi->rx_t = list_next_entry(espi->rx_t, transfer_list);
0425 
0426     fsl_espi_setup_transfer(spi, trans);
0427 
0428     ret = fsl_espi_bufs(spi, trans);
0429 
0430     spi_transfer_delay_exec(trans);
0431 
0432     return ret;
0433 }
0434 
0435 static int fsl_espi_do_one_msg(struct spi_master *master,
0436                    struct spi_message *m)
0437 {
0438     unsigned int rx_nbits = 0, delay_nsecs = 0;
0439     struct spi_transfer *t, trans = {};
0440     int ret;
0441 
0442     ret = fsl_espi_check_message(m);
0443     if (ret)
0444         goto out;
0445 
0446     list_for_each_entry(t, &m->transfers, transfer_list) {
0447         unsigned int delay = spi_delay_to_ns(&t->delay, t);
0448 
0449         if (delay > delay_nsecs)
0450             delay_nsecs = delay;
0451         if (t->rx_nbits > rx_nbits)
0452             rx_nbits = t->rx_nbits;
0453     }
0454 
0455     t = list_first_entry(&m->transfers, struct spi_transfer,
0456                  transfer_list);
0457 
0458     trans.len = m->frame_length;
0459     trans.speed_hz = t->speed_hz;
0460     trans.bits_per_word = t->bits_per_word;
0461     trans.delay.value = delay_nsecs;
0462     trans.delay.unit = SPI_DELAY_UNIT_NSECS;
0463     trans.rx_nbits = rx_nbits;
0464 
0465     if (trans.len)
0466         ret = fsl_espi_trans(m, &trans);
0467 
0468     m->actual_length = ret ? 0 : trans.len;
0469 out:
0470     if (m->status == -EINPROGRESS)
0471         m->status = ret;
0472 
0473     spi_finalize_current_message(master);
0474 
0475     return ret;
0476 }
0477 
0478 static int fsl_espi_setup(struct spi_device *spi)
0479 {
0480     struct fsl_espi *espi;
0481     u32 loop_mode;
0482     struct fsl_espi_cs *cs = spi_get_ctldata(spi);
0483 
0484     if (!cs) {
0485         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
0486         if (!cs)
0487             return -ENOMEM;
0488         spi_set_ctldata(spi, cs);
0489     }
0490 
0491     espi = spi_master_get_devdata(spi->master);
0492 
0493     pm_runtime_get_sync(espi->dev);
0494 
0495     cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi->chip_select));
0496     /* mask out bits we are going to set */
0497     cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
0498              | CSMODE_REV);
0499 
0500     if (spi->mode & SPI_CPHA)
0501         cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
0502     if (spi->mode & SPI_CPOL)
0503         cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
0504     if (!(spi->mode & SPI_LSB_FIRST))
0505         cs->hw_mode |= CSMODE_REV;
0506 
0507     /* Handle the loop mode */
0508     loop_mode = fsl_espi_read_reg(espi, ESPI_SPMODE);
0509     loop_mode &= ~SPMODE_LOOP;
0510     if (spi->mode & SPI_LOOP)
0511         loop_mode |= SPMODE_LOOP;
0512     fsl_espi_write_reg(espi, ESPI_SPMODE, loop_mode);
0513 
0514     fsl_espi_setup_transfer(spi, NULL);
0515 
0516     pm_runtime_mark_last_busy(espi->dev);
0517     pm_runtime_put_autosuspend(espi->dev);
0518 
0519     return 0;
0520 }
0521 
0522 static void fsl_espi_cleanup(struct spi_device *spi)
0523 {
0524     struct fsl_espi_cs *cs = spi_get_ctldata(spi);
0525 
0526     kfree(cs);
0527     spi_set_ctldata(spi, NULL);
0528 }
0529 
0530 static void fsl_espi_cpu_irq(struct fsl_espi *espi, u32 events)
0531 {
0532     if (!espi->rx_done)
0533         fsl_espi_read_rx_fifo(espi, events);
0534 
0535     if (!espi->tx_done)
0536         fsl_espi_fill_tx_fifo(espi, events);
0537 
0538     if (!espi->tx_done || !espi->rx_done)
0539         return;
0540 
0541     /* we're done, but check for errors before returning */
0542     events = fsl_espi_read_reg(espi, ESPI_SPIE);
0543 
0544     if (!(events & SPIE_DON))
0545         dev_err(espi->dev,
0546             "Transfer done but SPIE_DON isn't set!\n");
0547 
0548     if (SPIE_RXCNT(events) || SPIE_TXCNT(events) != FSL_ESPI_FIFO_SIZE) {
0549         dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n");
0550         dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n",
0551             SPIE_RXCNT(events), SPIE_TXCNT(events));
0552     }
0553 
0554     complete(&espi->done);
0555 }
0556 
0557 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
0558 {
0559     struct fsl_espi *espi = context_data;
0560     u32 events, mask;
0561 
0562     spin_lock(&espi->lock);
0563 
0564     /* Get interrupt events(tx/rx) */
0565     events = fsl_espi_read_reg(espi, ESPI_SPIE);
0566     mask = fsl_espi_read_reg(espi, ESPI_SPIM);
0567     if (!(events & mask)) {
0568         spin_unlock(&espi->lock);
0569         return IRQ_NONE;
0570     }
0571 
0572     dev_vdbg(espi->dev, "%s: events %x\n", __func__, events);
0573 
0574     fsl_espi_cpu_irq(espi, events);
0575 
0576     /* Clear the events */
0577     fsl_espi_write_reg(espi, ESPI_SPIE, events);
0578 
0579     spin_unlock(&espi->lock);
0580 
0581     return IRQ_HANDLED;
0582 }
0583 
0584 #ifdef CONFIG_PM
0585 static int fsl_espi_runtime_suspend(struct device *dev)
0586 {
0587     struct spi_master *master = dev_get_drvdata(dev);
0588     struct fsl_espi *espi = spi_master_get_devdata(master);
0589     u32 regval;
0590 
0591     regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
0592     regval &= ~SPMODE_ENABLE;
0593     fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
0594 
0595     return 0;
0596 }
0597 
0598 static int fsl_espi_runtime_resume(struct device *dev)
0599 {
0600     struct spi_master *master = dev_get_drvdata(dev);
0601     struct fsl_espi *espi = spi_master_get_devdata(master);
0602     u32 regval;
0603 
0604     regval = fsl_espi_read_reg(espi, ESPI_SPMODE);
0605     regval |= SPMODE_ENABLE;
0606     fsl_espi_write_reg(espi, ESPI_SPMODE, regval);
0607 
0608     return 0;
0609 }
0610 #endif
0611 
0612 static size_t fsl_espi_max_message_size(struct spi_device *spi)
0613 {
0614     return SPCOM_TRANLEN_MAX;
0615 }
0616 
0617 static void fsl_espi_init_regs(struct device *dev, bool initial)
0618 {
0619     struct spi_master *master = dev_get_drvdata(dev);
0620     struct fsl_espi *espi = spi_master_get_devdata(master);
0621     struct device_node *nc;
0622     u32 csmode, cs, prop;
0623     int ret;
0624 
0625     /* SPI controller initializations */
0626     fsl_espi_write_reg(espi, ESPI_SPMODE, 0);
0627     fsl_espi_write_reg(espi, ESPI_SPIM, 0);
0628     fsl_espi_write_reg(espi, ESPI_SPCOM, 0);
0629     fsl_espi_write_reg(espi, ESPI_SPIE, 0xffffffff);
0630 
0631     /* Init eSPI CS mode register */
0632     for_each_available_child_of_node(master->dev.of_node, nc) {
0633         /* get chip select */
0634         ret = of_property_read_u32(nc, "reg", &cs);
0635         if (ret || cs >= master->num_chipselect)
0636             continue;
0637 
0638         csmode = CSMODE_INIT_VAL;
0639 
0640         /* check if CSBEF is set in device tree */
0641         ret = of_property_read_u32(nc, "fsl,csbef", &prop);
0642         if (!ret) {
0643             csmode &= ~(CSMODE_BEF(0xf));
0644             csmode |= CSMODE_BEF(prop);
0645         }
0646 
0647         /* check if CSAFT is set in device tree */
0648         ret = of_property_read_u32(nc, "fsl,csaft", &prop);
0649         if (!ret) {
0650             csmode &= ~(CSMODE_AFT(0xf));
0651             csmode |= CSMODE_AFT(prop);
0652         }
0653 
0654         fsl_espi_write_reg(espi, ESPI_SPMODEx(cs), csmode);
0655 
0656         if (initial)
0657             dev_info(dev, "cs=%u, init_csmode=0x%x\n", cs, csmode);
0658     }
0659 
0660     /* Enable SPI interface */
0661     fsl_espi_write_reg(espi, ESPI_SPMODE, SPMODE_INIT_VAL | SPMODE_ENABLE);
0662 }
0663 
0664 static int fsl_espi_probe(struct device *dev, struct resource *mem,
0665               unsigned int irq, unsigned int num_cs)
0666 {
0667     struct spi_master *master;
0668     struct fsl_espi *espi;
0669     int ret;
0670 
0671     master = spi_alloc_master(dev, sizeof(struct fsl_espi));
0672     if (!master)
0673         return -ENOMEM;
0674 
0675     dev_set_drvdata(dev, master);
0676 
0677     master->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
0678                 SPI_LSB_FIRST | SPI_LOOP;
0679     master->dev.of_node = dev->of_node;
0680     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
0681     master->setup = fsl_espi_setup;
0682     master->cleanup = fsl_espi_cleanup;
0683     master->transfer_one_message = fsl_espi_do_one_msg;
0684     master->auto_runtime_pm = true;
0685     master->max_message_size = fsl_espi_max_message_size;
0686     master->num_chipselect = num_cs;
0687 
0688     espi = spi_master_get_devdata(master);
0689     spin_lock_init(&espi->lock);
0690 
0691     espi->dev = dev;
0692     espi->spibrg = fsl_get_sys_freq();
0693     if (espi->spibrg == -1) {
0694         dev_err(dev, "Can't get sys frequency!\n");
0695         ret = -EINVAL;
0696         goto err_probe;
0697     }
0698     /* determined by clock divider fields DIV16/PM in register SPMODEx */
0699     master->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16);
0700     master->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4);
0701 
0702     init_completion(&espi->done);
0703 
0704     espi->reg_base = devm_ioremap_resource(dev, mem);
0705     if (IS_ERR(espi->reg_base)) {
0706         ret = PTR_ERR(espi->reg_base);
0707         goto err_probe;
0708     }
0709 
0710     /* Register for SPI Interrupt */
0711     ret = devm_request_irq(dev, irq, fsl_espi_irq, 0, "fsl_espi", espi);
0712     if (ret)
0713         goto err_probe;
0714 
0715     fsl_espi_init_regs(dev, true);
0716 
0717     pm_runtime_set_autosuspend_delay(dev, AUTOSUSPEND_TIMEOUT);
0718     pm_runtime_use_autosuspend(dev);
0719     pm_runtime_set_active(dev);
0720     pm_runtime_enable(dev);
0721     pm_runtime_get_sync(dev);
0722 
0723     ret = devm_spi_register_master(dev, master);
0724     if (ret < 0)
0725         goto err_pm;
0726 
0727     dev_info(dev, "irq = %u\n", irq);
0728 
0729     pm_runtime_mark_last_busy(dev);
0730     pm_runtime_put_autosuspend(dev);
0731 
0732     return 0;
0733 
0734 err_pm:
0735     pm_runtime_put_noidle(dev);
0736     pm_runtime_disable(dev);
0737     pm_runtime_set_suspended(dev);
0738 err_probe:
0739     spi_master_put(master);
0740     return ret;
0741 }
0742 
0743 static int of_fsl_espi_get_chipselects(struct device *dev)
0744 {
0745     struct device_node *np = dev->of_node;
0746     u32 num_cs;
0747     int ret;
0748 
0749     ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs);
0750     if (ret) {
0751         dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
0752         return 0;
0753     }
0754 
0755     return num_cs;
0756 }
0757 
0758 static int of_fsl_espi_probe(struct platform_device *ofdev)
0759 {
0760     struct device *dev = &ofdev->dev;
0761     struct device_node *np = ofdev->dev.of_node;
0762     struct resource mem;
0763     unsigned int irq, num_cs;
0764     int ret;
0765 
0766     if (of_property_read_bool(np, "mode")) {
0767         dev_err(dev, "mode property is not supported on ESPI!\n");
0768         return -EINVAL;
0769     }
0770 
0771     num_cs = of_fsl_espi_get_chipselects(dev);
0772     if (!num_cs)
0773         return -EINVAL;
0774 
0775     ret = of_address_to_resource(np, 0, &mem);
0776     if (ret)
0777         return ret;
0778 
0779     irq = irq_of_parse_and_map(np, 0);
0780     if (!irq)
0781         return -EINVAL;
0782 
0783     return fsl_espi_probe(dev, &mem, irq, num_cs);
0784 }
0785 
0786 static int of_fsl_espi_remove(struct platform_device *dev)
0787 {
0788     pm_runtime_disable(&dev->dev);
0789 
0790     return 0;
0791 }
0792 
0793 #ifdef CONFIG_PM_SLEEP
0794 static int of_fsl_espi_suspend(struct device *dev)
0795 {
0796     struct spi_master *master = dev_get_drvdata(dev);
0797     int ret;
0798 
0799     ret = spi_master_suspend(master);
0800     if (ret)
0801         return ret;
0802 
0803     return pm_runtime_force_suspend(dev);
0804 }
0805 
0806 static int of_fsl_espi_resume(struct device *dev)
0807 {
0808     struct spi_master *master = dev_get_drvdata(dev);
0809     int ret;
0810 
0811     fsl_espi_init_regs(dev, false);
0812 
0813     ret = pm_runtime_force_resume(dev);
0814     if (ret < 0)
0815         return ret;
0816 
0817     return spi_master_resume(master);
0818 }
0819 #endif /* CONFIG_PM_SLEEP */
0820 
0821 static const struct dev_pm_ops espi_pm = {
0822     SET_RUNTIME_PM_OPS(fsl_espi_runtime_suspend,
0823                fsl_espi_runtime_resume, NULL)
0824     SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
0825 };
0826 
0827 static const struct of_device_id of_fsl_espi_match[] = {
0828     { .compatible = "fsl,mpc8536-espi" },
0829     {}
0830 };
0831 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
0832 
0833 static struct platform_driver fsl_espi_driver = {
0834     .driver = {
0835         .name = "fsl_espi",
0836         .of_match_table = of_fsl_espi_match,
0837         .pm = &espi_pm,
0838     },
0839     .probe      = of_fsl_espi_probe,
0840     .remove     = of_fsl_espi_remove,
0841 };
0842 module_platform_driver(fsl_espi_driver);
0843 
0844 MODULE_AUTHOR("Mingkai Hu");
0845 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
0846 MODULE_LICENSE("GPL");
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