0001
0002
0003
0004 #include <linux/bitfield.h>
0005 #include <linux/bits.h>
0006 #include <linux/fsi.h>
0007 #include <linux/jiffies.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/spi/spi.h>
0012
0013 #define FSI_ENGID_SPI 0x23
0014 #define FSI_MBOX_ROOT_CTRL_8 0x2860
0015 #define FSI_MBOX_ROOT_CTRL_8_SPI_MUX 0xf0000000
0016
0017 #define FSI2SPI_DATA0 0x00
0018 #define FSI2SPI_DATA1 0x04
0019 #define FSI2SPI_CMD 0x08
0020 #define FSI2SPI_CMD_WRITE BIT(31)
0021 #define FSI2SPI_RESET 0x18
0022 #define FSI2SPI_STATUS 0x1c
0023 #define FSI2SPI_STATUS_ANY_ERROR BIT(31)
0024 #define FSI2SPI_IRQ 0x20
0025
0026 #define SPI_FSI_BASE 0x70000
0027 #define SPI_FSI_TIMEOUT_MS 1000
0028 #define SPI_FSI_MAX_RX_SIZE 8
0029 #define SPI_FSI_MAX_TX_SIZE 40
0030
0031 #define SPI_FSI_ERROR 0x0
0032 #define SPI_FSI_COUNTER_CFG 0x1
0033 #define SPI_FSI_CFG1 0x2
0034 #define SPI_FSI_CLOCK_CFG 0x3
0035 #define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32)
0036 #define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33))
0037 #define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38))
0038 #define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39))
0039 #define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42))
0040 #define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44)
0041 #define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51)
0042 #define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52)
0043 #define SPI_FSI_MMAP 0x4
0044 #define SPI_FSI_DATA_TX 0x5
0045 #define SPI_FSI_DATA_RX 0x6
0046 #define SPI_FSI_SEQUENCE 0x7
0047 #define SPI_FSI_SEQUENCE_STOP 0x00
0048 #define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf))
0049 #define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf))
0050 #define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf))
0051 #define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0
0052 #define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf))
0053 #define SPI_FSI_STATUS 0x8
0054 #define SPI_FSI_STATUS_ERROR \
0055 (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12))
0056 #define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48)
0057 #define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48)
0058 #define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57)
0059 #define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58)
0060 #define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59)
0061 #define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61)
0062 #define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62)
0063 #define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63)
0064 #define SPI_FSI_STATUS_ANY_ERROR \
0065 (SPI_FSI_STATUS_ERROR | \
0066 SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \
0067 SPI_FSI_STATUS_RDR_OVERRUN)
0068 #define SPI_FSI_PORT_CTRL 0x9
0069
0070 struct fsi2spi {
0071 struct fsi_device *fsi;
0072 struct mutex lock;
0073 };
0074
0075 struct fsi_spi {
0076 struct device *dev;
0077 struct fsi2spi *bridge;
0078 u32 base;
0079 };
0080
0081 struct fsi_spi_sequence {
0082 int bit;
0083 u64 data;
0084 };
0085
0086 static int fsi_spi_check_mux(struct fsi_device *fsi, struct device *dev)
0087 {
0088 int rc;
0089 u32 root_ctrl_8;
0090 __be32 root_ctrl_8_be;
0091
0092 rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8_be,
0093 sizeof(root_ctrl_8_be));
0094 if (rc)
0095 return rc;
0096
0097 root_ctrl_8 = be32_to_cpu(root_ctrl_8_be);
0098 dev_dbg(dev, "Root control register 8: %08x\n", root_ctrl_8);
0099 if ((root_ctrl_8 & FSI_MBOX_ROOT_CTRL_8_SPI_MUX) ==
0100 FSI_MBOX_ROOT_CTRL_8_SPI_MUX)
0101 return 0;
0102
0103 return -ENOLINK;
0104 }
0105
0106 static int fsi_spi_check_status(struct fsi_spi *ctx)
0107 {
0108 int rc;
0109 u32 sts;
0110 __be32 sts_be;
0111
0112 rc = fsi_device_read(ctx->bridge->fsi, FSI2SPI_STATUS, &sts_be,
0113 sizeof(sts_be));
0114 if (rc)
0115 return rc;
0116
0117 sts = be32_to_cpu(sts_be);
0118 if (sts & FSI2SPI_STATUS_ANY_ERROR) {
0119 dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts);
0120 return -EIO;
0121 }
0122
0123 return 0;
0124 }
0125
0126 static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value)
0127 {
0128 int rc = 0;
0129 __be32 cmd_be;
0130 __be32 data_be;
0131 u32 cmd = offset + ctx->base;
0132 struct fsi2spi *bridge = ctx->bridge;
0133
0134 *value = 0ULL;
0135
0136 if (cmd & FSI2SPI_CMD_WRITE)
0137 return -EINVAL;
0138
0139 rc = mutex_lock_interruptible(&bridge->lock);
0140 if (rc)
0141 return rc;
0142
0143 cmd_be = cpu_to_be32(cmd);
0144 rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
0145 sizeof(cmd_be));
0146 if (rc)
0147 goto unlock;
0148
0149 rc = fsi_spi_check_status(ctx);
0150 if (rc)
0151 goto unlock;
0152
0153 rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA0, &data_be,
0154 sizeof(data_be));
0155 if (rc)
0156 goto unlock;
0157
0158 *value |= (u64)be32_to_cpu(data_be) << 32;
0159
0160 rc = fsi_device_read(bridge->fsi, FSI2SPI_DATA1, &data_be,
0161 sizeof(data_be));
0162 if (rc)
0163 goto unlock;
0164
0165 *value |= (u64)be32_to_cpu(data_be);
0166 dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value);
0167
0168 unlock:
0169 mutex_unlock(&bridge->lock);
0170 return rc;
0171 }
0172
0173 static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value)
0174 {
0175 int rc = 0;
0176 __be32 cmd_be;
0177 __be32 data_be;
0178 u32 cmd = offset + ctx->base;
0179 struct fsi2spi *bridge = ctx->bridge;
0180
0181 if (cmd & FSI2SPI_CMD_WRITE)
0182 return -EINVAL;
0183
0184 rc = mutex_lock_interruptible(&bridge->lock);
0185 if (rc)
0186 return rc;
0187
0188 dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value);
0189
0190 data_be = cpu_to_be32(upper_32_bits(value));
0191 rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA0, &data_be,
0192 sizeof(data_be));
0193 if (rc)
0194 goto unlock;
0195
0196 data_be = cpu_to_be32(lower_32_bits(value));
0197 rc = fsi_device_write(bridge->fsi, FSI2SPI_DATA1, &data_be,
0198 sizeof(data_be));
0199 if (rc)
0200 goto unlock;
0201
0202 cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE);
0203 rc = fsi_device_write(bridge->fsi, FSI2SPI_CMD, &cmd_be,
0204 sizeof(cmd_be));
0205 if (rc)
0206 goto unlock;
0207
0208 rc = fsi_spi_check_status(ctx);
0209
0210 unlock:
0211 mutex_unlock(&bridge->lock);
0212 return rc;
0213 }
0214
0215 static int fsi_spi_data_in(u64 in, u8 *rx, int len)
0216 {
0217 int i;
0218 int num_bytes = min(len, 8);
0219
0220 for (i = 0; i < num_bytes; ++i)
0221 rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i)));
0222
0223 return num_bytes;
0224 }
0225
0226 static int fsi_spi_data_out(u64 *out, const u8 *tx, int len)
0227 {
0228 int i;
0229 int num_bytes = min(len, 8);
0230 u8 *out_bytes = (u8 *)out;
0231
0232
0233 *out = 0ULL;
0234
0235 for (i = 0; i < num_bytes; ++i)
0236 out_bytes[8 - (i + 1)] = tx[i];
0237
0238 return num_bytes;
0239 }
0240
0241 static int fsi_spi_reset(struct fsi_spi *ctx)
0242 {
0243 int rc;
0244
0245 dev_dbg(ctx->dev, "Resetting SPI controller.\n");
0246
0247 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
0248 SPI_FSI_CLOCK_CFG_RESET1);
0249 if (rc)
0250 return rc;
0251
0252 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
0253 SPI_FSI_CLOCK_CFG_RESET2);
0254 if (rc)
0255 return rc;
0256
0257 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL);
0258 }
0259
0260 static int fsi_spi_status(struct fsi_spi *ctx, u64 *status, const char *dir)
0261 {
0262 int rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, status);
0263
0264 if (rc)
0265 return rc;
0266
0267 if (*status & SPI_FSI_STATUS_ANY_ERROR) {
0268 dev_err(ctx->dev, "%s error: %016llx\n", dir, *status);
0269
0270 rc = fsi_spi_reset(ctx);
0271 if (rc)
0272 return rc;
0273
0274 return -EREMOTEIO;
0275 }
0276
0277 return 0;
0278 }
0279
0280 static void fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val)
0281 {
0282
0283
0284
0285
0286
0287
0288 seq->data |= (u64)val << seq->bit;
0289 seq->bit -= 8;
0290 }
0291
0292 static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq)
0293 {
0294 seq->bit = 56;
0295 seq->data = 0ULL;
0296 }
0297
0298 static int fsi_spi_transfer_data(struct fsi_spi *ctx,
0299 struct spi_transfer *transfer)
0300 {
0301 int loops;
0302 int rc = 0;
0303 unsigned long end;
0304 u64 status = 0ULL;
0305
0306 if (transfer->tx_buf) {
0307 int nb;
0308 int sent = 0;
0309 u64 out = 0ULL;
0310 const u8 *tx = transfer->tx_buf;
0311
0312 while (transfer->len > sent) {
0313 nb = fsi_spi_data_out(&out, &tx[sent],
0314 (int)transfer->len - sent);
0315
0316 rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out);
0317 if (rc)
0318 return rc;
0319
0320 loops = 0;
0321 end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
0322 do {
0323 if (loops++ && time_after(jiffies, end))
0324 return -ETIMEDOUT;
0325
0326 rc = fsi_spi_status(ctx, &status, "TX");
0327 if (rc)
0328 return rc;
0329 } while (status & SPI_FSI_STATUS_TDR_FULL);
0330
0331 sent += nb;
0332 }
0333 } else if (transfer->rx_buf) {
0334 int recv = 0;
0335 u64 in = 0ULL;
0336 u8 *rx = transfer->rx_buf;
0337
0338 while (transfer->len > recv) {
0339 loops = 0;
0340 end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
0341 do {
0342 if (loops++ && time_after(jiffies, end))
0343 return -ETIMEDOUT;
0344
0345 rc = fsi_spi_status(ctx, &status, "RX");
0346 if (rc)
0347 return rc;
0348 } while (!(status & SPI_FSI_STATUS_RDR_FULL));
0349
0350 rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in);
0351 if (rc)
0352 return rc;
0353
0354 recv += fsi_spi_data_in(in, &rx[recv],
0355 (int)transfer->len - recv);
0356 }
0357 }
0358
0359 return 0;
0360 }
0361
0362 static int fsi_spi_transfer_init(struct fsi_spi *ctx)
0363 {
0364 int loops = 0;
0365 int rc;
0366 bool reset = false;
0367 unsigned long end;
0368 u64 seq_state;
0369 u64 clock_cfg = 0ULL;
0370 u64 status = 0ULL;
0371 u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE |
0372 SPI_FSI_CLOCK_CFG_SCK_NO_DEL |
0373 FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 19);
0374
0375 end = jiffies + msecs_to_jiffies(SPI_FSI_TIMEOUT_MS);
0376 do {
0377 if (loops++ && time_after(jiffies, end))
0378 return -ETIMEDOUT;
0379
0380 rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status);
0381 if (rc)
0382 return rc;
0383
0384 seq_state = status & SPI_FSI_STATUS_SEQ_STATE;
0385
0386 if (status & (SPI_FSI_STATUS_ANY_ERROR |
0387 SPI_FSI_STATUS_TDR_FULL |
0388 SPI_FSI_STATUS_RDR_FULL)) {
0389 if (reset) {
0390 dev_err(ctx->dev,
0391 "Initialization error: %08llx\n",
0392 status);
0393 return -EIO;
0394 }
0395
0396 rc = fsi_spi_reset(ctx);
0397 if (rc)
0398 return rc;
0399
0400 reset = true;
0401 continue;
0402 }
0403 } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE));
0404
0405 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL);
0406 if (rc)
0407 return rc;
0408
0409 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg);
0410 if (rc)
0411 return rc;
0412
0413 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE |
0414 SPI_FSI_CLOCK_CFG_ECC_DISABLE |
0415 SPI_FSI_CLOCK_CFG_MODE |
0416 SPI_FSI_CLOCK_CFG_SCK_RECV_DEL |
0417 SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg)
0418 rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG,
0419 wanted_clock_cfg);
0420
0421 return rc;
0422 }
0423
0424 static int fsi_spi_transfer_one_message(struct spi_controller *ctlr,
0425 struct spi_message *mesg)
0426 {
0427 int rc;
0428 u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1);
0429 unsigned int len;
0430 struct spi_transfer *transfer;
0431 struct fsi_spi *ctx = spi_controller_get_devdata(ctlr);
0432
0433 rc = fsi_spi_check_mux(ctx->bridge->fsi, ctx->dev);
0434 if (rc)
0435 goto error;
0436
0437 list_for_each_entry(transfer, &mesg->transfers, transfer_list) {
0438 struct fsi_spi_sequence seq;
0439 struct spi_transfer *next = NULL;
0440
0441
0442 if (!transfer->tx_buf || transfer->len > SPI_FSI_MAX_TX_SIZE) {
0443 rc = -EINVAL;
0444 goto error;
0445 }
0446
0447 dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len);
0448
0449 rc = fsi_spi_transfer_init(ctx);
0450 if (rc < 0)
0451 goto error;
0452
0453 fsi_spi_sequence_init(&seq);
0454 fsi_spi_sequence_add(&seq, seq_slave);
0455
0456 len = transfer->len;
0457 while (len > 8) {
0458 fsi_spi_sequence_add(&seq,
0459 SPI_FSI_SEQUENCE_SHIFT_OUT(8));
0460 len -= 8;
0461 }
0462 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SHIFT_OUT(len));
0463
0464 if (!list_is_last(&transfer->transfer_list,
0465 &mesg->transfers)) {
0466 next = list_next_entry(transfer, transfer_list);
0467
0468
0469 if (next->rx_buf) {
0470 u8 shift;
0471
0472 if (next->len > SPI_FSI_MAX_RX_SIZE) {
0473 rc = -EINVAL;
0474 goto error;
0475 }
0476
0477 dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n",
0478 next->len);
0479
0480 shift = SPI_FSI_SEQUENCE_SHIFT_IN(next->len);
0481 fsi_spi_sequence_add(&seq, shift);
0482 } else {
0483 next = NULL;
0484 }
0485 }
0486
0487 fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0));
0488
0489 rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data);
0490 if (rc)
0491 goto error;
0492
0493 rc = fsi_spi_transfer_data(ctx, transfer);
0494 if (rc)
0495 goto error;
0496
0497 if (next) {
0498 rc = fsi_spi_transfer_data(ctx, next);
0499 if (rc)
0500 goto error;
0501
0502 transfer = next;
0503 }
0504 }
0505
0506 error:
0507 mesg->status = rc;
0508 spi_finalize_current_message(ctlr);
0509
0510 return rc;
0511 }
0512
0513 static size_t fsi_spi_max_transfer_size(struct spi_device *spi)
0514 {
0515 return SPI_FSI_MAX_RX_SIZE;
0516 }
0517
0518 static int fsi_spi_probe(struct device *dev)
0519 {
0520 int rc;
0521 struct device_node *np;
0522 int num_controllers_registered = 0;
0523 struct fsi2spi *bridge;
0524 struct fsi_device *fsi = to_fsi_dev(dev);
0525
0526 rc = fsi_spi_check_mux(fsi, dev);
0527 if (rc)
0528 return -ENODEV;
0529
0530 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
0531 if (!bridge)
0532 return -ENOMEM;
0533
0534 bridge->fsi = fsi;
0535 mutex_init(&bridge->lock);
0536
0537 for_each_available_child_of_node(dev->of_node, np) {
0538 u32 base;
0539 struct fsi_spi *ctx;
0540 struct spi_controller *ctlr;
0541
0542 if (of_property_read_u32(np, "reg", &base))
0543 continue;
0544
0545 ctlr = spi_alloc_master(dev, sizeof(*ctx));
0546 if (!ctlr) {
0547 of_node_put(np);
0548 break;
0549 }
0550
0551 ctlr->dev.of_node = np;
0552 ctlr->num_chipselect = of_get_available_child_count(np) ?: 1;
0553 ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
0554 ctlr->max_transfer_size = fsi_spi_max_transfer_size;
0555 ctlr->transfer_one_message = fsi_spi_transfer_one_message;
0556
0557 ctx = spi_controller_get_devdata(ctlr);
0558 ctx->dev = &ctlr->dev;
0559 ctx->bridge = bridge;
0560 ctx->base = base + SPI_FSI_BASE;
0561
0562 rc = devm_spi_register_controller(dev, ctlr);
0563 if (rc)
0564 spi_controller_put(ctlr);
0565 else
0566 num_controllers_registered++;
0567 }
0568
0569 if (!num_controllers_registered)
0570 return -ENODEV;
0571
0572 return 0;
0573 }
0574
0575 static const struct fsi_device_id fsi_spi_ids[] = {
0576 { FSI_ENGID_SPI, FSI_VERSION_ANY },
0577 { }
0578 };
0579 MODULE_DEVICE_TABLE(fsi, fsi_spi_ids);
0580
0581 static struct fsi_driver fsi_spi_driver = {
0582 .id_table = fsi_spi_ids,
0583 .drv = {
0584 .name = "spi-fsi",
0585 .bus = &fsi_bus_type,
0586 .probe = fsi_spi_probe,
0587 },
0588 };
0589 module_fsi_driver(fsi_spi_driver);
0590
0591 MODULE_AUTHOR("Eddie James <eajames@linux.ibm.com>");
0592 MODULE_DESCRIPTION("FSI attached SPI controller");
0593 MODULE_LICENSE("GPL");
