drivers/spi/spi-dw.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SPI_DW_H__
0003 #define __SPI_DW_H__
0004
0005 #include <linux/bits.h>
0006 #include <linux/completion.h>
0007 #include <linux/debugfs.h>
0008 #include <linux/irqreturn.h>
0009 #include <linux/io.h>
0010 #include <linux/scatterlist.h>
0011 #include <linux/spi/spi-mem.h>
0012 #include <linux/bitfield.h>
0013
0014 /* Synopsys DW SSI IP-core virtual IDs */
0015 #define DW_PSSI_ID          0
0016 #define DW_HSSI_ID          1
0017
0018 /* Synopsys DW SSI component versions (FourCC sequence) */
0019 #define DW_HSSI_102A            0x3130322a
0020
0021 /* DW SSI IP-core ID and version check helpers */
0022 #define dw_spi_ip_is(_dws, _ip) \
0023     ((_dws)->ip == DW_ ## _ip ## _ID)
0024
0025 #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
0026     (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
0027
0028 #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
0029
0030 #define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=)
0031
0032 /* DW SPI controller capabilities */
0033 #define DW_SPI_CAP_CS_OVERRIDE      BIT(0)
0034 #define DW_SPI_CAP_DFS32        BIT(1)
0035
0036 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
0037 #define DW_SPI_CTRLR0           0x00
0038 #define DW_SPI_CTRLR1           0x04
0039 #define DW_SPI_SSIENR           0x08
0040 #define DW_SPI_MWCR         0x0c
0041 #define DW_SPI_SER          0x10
0042 #define DW_SPI_BAUDR            0x14
0043 #define DW_SPI_TXFTLR           0x18
0044 #define DW_SPI_RXFTLR           0x1c
0045 #define DW_SPI_TXFLR            0x20
0046 #define DW_SPI_RXFLR            0x24
0047 #define DW_SPI_SR           0x28
0048 #define DW_SPI_IMR          0x2c
0049 #define DW_SPI_ISR          0x30
0050 #define DW_SPI_RISR         0x34
0051 #define DW_SPI_TXOICR           0x38
0052 #define DW_SPI_RXOICR           0x3c
0053 #define DW_SPI_RXUICR           0x40
0054 #define DW_SPI_MSTICR           0x44
0055 #define DW_SPI_ICR          0x48
0056 #define DW_SPI_DMACR            0x4c
0057 #define DW_SPI_DMATDLR          0x50
0058 #define DW_SPI_DMARDLR          0x54
0059 #define DW_SPI_IDR          0x58
0060 #define DW_SPI_VERSION          0x5c
0061 #define DW_SPI_DR           0x60
0062 #define DW_SPI_RX_SAMPLE_DLY        0xf0
0063 #define DW_SPI_CS_OVERRIDE      0xf4
0064
0065 /* Bit fields in CTRLR0 (DWC APB SSI) */
0066 #define DW_PSSI_CTRLR0_DFS_MASK         GENMASK(3, 0)
0067 #define DW_PSSI_CTRLR0_DFS32_MASK       GENMASK(20, 16)
0068
0069 #define DW_PSSI_CTRLR0_FRF_MASK         GENMASK(5, 4)
0070 #define DW_SPI_CTRLR0_FRF_MOTO_SPI      0x0
0071 #define DW_SPI_CTRLR0_FRF_TI_SSP        0x1
0072 #define DW_SPI_CTRLR0_FRF_NS_MICROWIRE      0x2
0073 #define DW_SPI_CTRLR0_FRF_RESV          0x3
0074
0075 #define DW_PSSI_CTRLR0_MODE_MASK        GENMASK(7, 6)
0076 #define DW_PSSI_CTRLR0_SCPHA            BIT(6)
0077 #define DW_PSSI_CTRLR0_SCPOL            BIT(7)
0078
0079 #define DW_PSSI_CTRLR0_TMOD_MASK        GENMASK(9, 8)
0080 #define DW_SPI_CTRLR0_TMOD_TR           0x0 /* xmit & recv */
0081 #define DW_SPI_CTRLR0_TMOD_TO           0x1 /* xmit only */
0082 #define DW_SPI_CTRLR0_TMOD_RO           0x2 /* recv only */
0083 #define DW_SPI_CTRLR0_TMOD_EPROMREAD        0x3 /* eeprom read mode */
0084
0085 #define DW_PSSI_CTRLR0_SLV_OE           BIT(10)
0086 #define DW_PSSI_CTRLR0_SRL          BIT(11)
0087 #define DW_PSSI_CTRLR0_CFS          BIT(12)
0088
0089 /* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
0090 #define DW_HSSI_CTRLR0_DFS_MASK         GENMASK(4, 0)
0091 #define DW_HSSI_CTRLR0_FRF_MASK         GENMASK(7, 6)
0092 #define DW_HSSI_CTRLR0_SCPHA            BIT(8)
0093 #define DW_HSSI_CTRLR0_SCPOL            BIT(9)
0094 #define DW_HSSI_CTRLR0_TMOD_MASK        GENMASK(11, 10)
0095 #define DW_HSSI_CTRLR0_SRL          BIT(13)
0096 #define DW_HSSI_CTRLR0_MST          BIT(31)
0097
0098 /* Bit fields in CTRLR1 */
0099 #define DW_SPI_NDF_MASK             GENMASK(15, 0)
0100
0101 /* Bit fields in SR, 7 bits */
0102 #define DW_SPI_SR_MASK              GENMASK(6, 0)
0103 #define DW_SPI_SR_BUSY              BIT(0)
0104 #define DW_SPI_SR_TF_NOT_FULL           BIT(1)
0105 #define DW_SPI_SR_TF_EMPT           BIT(2)
0106 #define DW_SPI_SR_RF_NOT_EMPT           BIT(3)
0107 #define DW_SPI_SR_RF_FULL           BIT(4)
0108 #define DW_SPI_SR_TX_ERR            BIT(5)
0109 #define DW_SPI_SR_DCOL              BIT(6)
0110
0111 /* Bit fields in ISR, IMR, RISR, 7 bits */
0112 #define DW_SPI_INT_MASK             GENMASK(5, 0)
0113 #define DW_SPI_INT_TXEI             BIT(0)
0114 #define DW_SPI_INT_TXOI             BIT(1)
0115 #define DW_SPI_INT_RXUI             BIT(2)
0116 #define DW_SPI_INT_RXOI             BIT(3)
0117 #define DW_SPI_INT_RXFI             BIT(4)
0118 #define DW_SPI_INT_MSTI             BIT(5)
0119
0120 /* Bit fields in DMACR */
0121 #define DW_SPI_DMACR_RDMAE          BIT(0)
0122 #define DW_SPI_DMACR_TDMAE          BIT(1)
0123
0124 /* Mem/DMA operations helpers */
0125 #define DW_SPI_WAIT_RETRIES         5
0126 #define DW_SPI_BUF_SIZE \
0127     (sizeof_field(struct spi_mem_op, cmd.opcode) + \
0128      sizeof_field(struct spi_mem_op, addr.val) + 256)
0129 #define DW_SPI_GET_BYTE(_val, _idx) \
0130     ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
0131
0132 /* Slave spi_transfer/spi_mem_op related */
0133 struct dw_spi_cfg {
0134     u8 tmode;
0135     u8 dfs;
0136     u32 ndf;
0137     u32 freq;
0138 };
0139
0140 struct dw_spi;
0141 struct dw_spi_dma_ops {
0142     int (*dma_init)(struct device *dev, struct dw_spi *dws);
0143     void (*dma_exit)(struct dw_spi *dws);
0144     int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
0145     bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
0146             struct spi_transfer *xfer);
0147     int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
0148     void (*dma_stop)(struct dw_spi *dws);
0149 };
0150
0151 struct dw_spi {
0152     struct spi_controller   *master;
0153
0154     u32         ip;     /* Synopsys DW SSI IP-core ID */
0155     u32         ver;        /* Synopsys component version */
0156     u32         caps;       /* DW SPI capabilities */
0157
0158     void __iomem        *regs;
0159     unsigned long       paddr;
0160     int         irq;
0161     u32         fifo_len;   /* depth of the FIFO buffer */
0162     unsigned int        dfs_offset;     /* CTRLR0 DFS field offset */
0163     u32         max_mem_freq;   /* max mem-ops bus freq */
0164     u32         max_freq;   /* max bus freq supported */
0165
0166     u32         reg_io_width;   /* DR I/O width in bytes */
0167     u16         bus_num;
0168     u16         num_cs;     /* supported slave numbers */
0169     void (*set_cs)(struct spi_device *spi, bool enable);
0170
0171     /* Current message transfer state info */
0172     void            *tx;
0173     unsigned int        tx_len;
0174     void            *rx;
0175     unsigned int        rx_len;
0176     u8          buf[DW_SPI_BUF_SIZE];
0177     int         dma_mapped;
0178     u8          n_bytes;    /* current is a 1/2 bytes op */
0179     irqreturn_t     (*transfer_handler)(struct dw_spi *dws);
0180     u32         current_freq;   /* frequency in hz */
0181     u32         cur_rx_sample_dly;
0182     u32         def_rx_sample_dly_ns;
0183
0184     /* Custom memory operations */
0185     struct spi_controller_mem_ops mem_ops;
0186
0187     /* DMA info */
0188     struct dma_chan     *txchan;
0189     u32         txburst;
0190     struct dma_chan     *rxchan;
0191     u32         rxburst;
0192     u32         dma_sg_burst;
0193     unsigned long       dma_chan_busy;
0194     dma_addr_t      dma_addr; /* phy address of the Data register */
0195     const struct dw_spi_dma_ops *dma_ops;
0196     struct completion   dma_completion;
0197
0198 #ifdef CONFIG_DEBUG_FS
0199     struct dentry *debugfs;
0200     struct debugfs_regset32 regset;
0201 #endif
0202 };
0203
0204 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
0205 {
0206     return __raw_readl(dws->regs + offset);
0207 }
0208
0209 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
0210 {
0211     __raw_writel(val, dws->regs + offset);
0212 }
0213
0214 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
0215 {
0216     switch (dws->reg_io_width) {
0217     case 2:
0218         return readw_relaxed(dws->regs + offset);
0219     case 4:
0220     default:
0221         return readl_relaxed(dws->regs + offset);
0222     }
0223 }
0224
0225 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
0226 {
0227     switch (dws->reg_io_width) {
0228     case 2:
0229         writew_relaxed(val, dws->regs + offset);
0230         break;
0231     case 4:
0232     default:
0233         writel_relaxed(val, dws->regs + offset);
0234         break;
0235     }
0236 }
0237
0238 static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
0239 {
0240     dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
0241 }
0242
0243 static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
0244 {
0245     dw_writel(dws, DW_SPI_BAUDR, div);
0246 }
0247
0248 /* Disable IRQ bits */
0249 static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
0250 {
0251     u32 new_mask;
0252
0253     new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
0254     dw_writel(dws, DW_SPI_IMR, new_mask);
0255 }
0256
0257 /* Enable IRQ bits */
0258 static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
0259 {
0260     u32 new_mask;
0261
0262     new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
0263     dw_writel(dws, DW_SPI_IMR, new_mask);
0264 }
0265
0266 /*
0267  * This disables the SPI controller, interrupts, clears the interrupts status
0268  * and CS, then re-enables the controller back. Transmit and receive FIFO
0269  * buffers are cleared when the device is disabled.
0270  */
0271 static inline void dw_spi_reset_chip(struct dw_spi *dws)
0272 {
0273     dw_spi_enable_chip(dws, 0);
0274     dw_spi_mask_intr(dws, 0xff);
0275     dw_readl(dws, DW_SPI_ICR);
0276     dw_writel(dws, DW_SPI_SER, 0);
0277     dw_spi_enable_chip(dws, 1);
0278 }
0279
0280 static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
0281 {
0282     dw_spi_enable_chip(dws, 0);
0283     dw_spi_set_clk(dws, 0);
0284 }
0285
0286 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
0287 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
0288                  struct dw_spi_cfg *cfg);
0289 extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
0290 extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
0291 extern void dw_spi_remove_host(struct dw_spi *dws);
0292 extern int dw_spi_suspend_host(struct dw_spi *dws);
0293 extern int dw_spi_resume_host(struct dw_spi *dws);
0294
0295 #ifdef CONFIG_SPI_DW_DMA
0296
0297 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
0298 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
0299
0300 #else
0301
0302 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
0303 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
0304
0305 #endif /* !CONFIG_SPI_DW_DMA */
0306
0307 #endif /* __SPI_DW_H__ */