drivers/spi/spi-dw-pci.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PCI interface driver for DW SPI Core
0004  *
0005  * Copyright (c) 2009, 2014 Intel Corporation.
0006  */
0007
0008 #include <linux/pci.h>
0009 #include <linux/pm_runtime.h>
0010 #include <linux/slab.h>
0011 #include <linux/spi/spi.h>
0012 #include <linux/module.h>
0013
0014 #include "spi-dw.h"
0015
0016 #define DRIVER_NAME "dw_spi_pci"
0017
0018 /* HW info for MRST Clk Control Unit, 32b reg per controller */
0019 #define MRST_SPI_CLK_BASE   100000000   /* 100m */
0020 #define MRST_CLK_SPI_REG    0xff11d86c
0021 #define CLK_SPI_BDIV_OFFSET 0
0022 #define CLK_SPI_BDIV_MASK   0x00000007
0023 #define CLK_SPI_CDIV_OFFSET 9
0024 #define CLK_SPI_CDIV_MASK   0x00000e00
0025 #define CLK_SPI_DISABLE_OFFSET  8
0026
0027 struct dw_spi_pci_desc {
0028     int (*setup)(struct dw_spi *);
0029     u16 num_cs;
0030     u16 bus_num;
0031     u32 max_freq;
0032 };
0033
0034 static int dw_spi_pci_mid_init(struct dw_spi *dws)
0035 {
0036     void __iomem *clk_reg;
0037     u32 clk_cdiv;
0038
0039     clk_reg = ioremap(MRST_CLK_SPI_REG, 16);
0040     if (!clk_reg)
0041         return -ENOMEM;
0042
0043     /* Get SPI controller operating freq info */
0044     clk_cdiv = readl(clk_reg + dws->bus_num * sizeof(u32));
0045     clk_cdiv &= CLK_SPI_CDIV_MASK;
0046     clk_cdiv >>= CLK_SPI_CDIV_OFFSET;
0047     dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
0048
0049     iounmap(clk_reg);
0050
0051     dw_spi_dma_setup_mfld(dws);
0052
0053     return 0;
0054 }
0055
0056 static int dw_spi_pci_generic_init(struct dw_spi *dws)
0057 {
0058     dw_spi_dma_setup_generic(dws);
0059
0060     return 0;
0061 }
0062
0063 static struct dw_spi_pci_desc dw_spi_pci_mid_desc_1 = {
0064     .setup = dw_spi_pci_mid_init,
0065     .num_cs = 5,
0066     .bus_num = 0,
0067 };
0068
0069 static struct dw_spi_pci_desc dw_spi_pci_mid_desc_2 = {
0070     .setup = dw_spi_pci_mid_init,
0071     .num_cs = 2,
0072     .bus_num = 1,
0073 };
0074
0075 static struct dw_spi_pci_desc dw_spi_pci_ehl_desc = {
0076     .setup = dw_spi_pci_generic_init,
0077     .num_cs = 2,
0078     .bus_num = -1,
0079     .max_freq = 100000000,
0080 };
0081
0082 static int dw_spi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0083 {
0084     struct dw_spi_pci_desc *desc = (struct dw_spi_pci_desc *)ent->driver_data;
0085     struct dw_spi *dws;
0086     int pci_bar = 0;
0087     int ret;
0088
0089     ret = pcim_enable_device(pdev);
0090     if (ret)
0091         return ret;
0092
0093     dws = devm_kzalloc(&pdev->dev, sizeof(*dws), GFP_KERNEL);
0094     if (!dws)
0095         return -ENOMEM;
0096
0097     /* Get basic io resource and map it */
0098     dws->paddr = pci_resource_start(pdev, pci_bar);
0099     pci_set_master(pdev);
0100
0101     ret = pcim_iomap_regions(pdev, 1 << pci_bar, pci_name(pdev));
0102     if (ret)
0103         return ret;
0104
0105     ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
0106     if (ret < 0)
0107         return ret;
0108
0109     dws->regs = pcim_iomap_table(pdev)[pci_bar];
0110     dws->irq = pci_irq_vector(pdev, 0);
0111
0112     /*
0113      * Specific handling for platforms, like dma setup,
0114      * clock rate, FIFO depth.
0115      */
0116     if (desc) {
0117         dws->num_cs = desc->num_cs;
0118         dws->bus_num = desc->bus_num;
0119         dws->max_freq = desc->max_freq;
0120
0121         if (desc->setup) {
0122             ret = desc->setup(dws);
0123             if (ret)
0124                 goto err_free_irq_vectors;
0125         }
0126     } else {
0127         ret = -ENODEV;
0128         goto err_free_irq_vectors;
0129     }
0130
0131     ret = dw_spi_add_host(&pdev->dev, dws);
0132     if (ret)
0133         goto err_free_irq_vectors;
0134
0135     /* PCI hook and SPI hook use the same drv data */
0136     pci_set_drvdata(pdev, dws);
0137
0138     dev_info(&pdev->dev, "found PCI SPI controller(ID: %04x:%04x)\n",
0139         pdev->vendor, pdev->device);
0140
0141     pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
0142     pm_runtime_use_autosuspend(&pdev->dev);
0143     pm_runtime_put_autosuspend(&pdev->dev);
0144     pm_runtime_allow(&pdev->dev);
0145
0146     return 0;
0147
0148 err_free_irq_vectors:
0149     pci_free_irq_vectors(pdev);
0150     return ret;
0151 }
0152
0153 static void dw_spi_pci_remove(struct pci_dev *pdev)
0154 {
0155     struct dw_spi *dws = pci_get_drvdata(pdev);
0156
0157     pm_runtime_forbid(&pdev->dev);
0158     pm_runtime_get_noresume(&pdev->dev);
0159
0160     dw_spi_remove_host(dws);
0161     pci_free_irq_vectors(pdev);
0162 }
0163
0164 #ifdef CONFIG_PM_SLEEP
0165 static int dw_spi_pci_suspend(struct device *dev)
0166 {
0167     struct dw_spi *dws = dev_get_drvdata(dev);
0168
0169     return dw_spi_suspend_host(dws);
0170 }
0171
0172 static int dw_spi_pci_resume(struct device *dev)
0173 {
0174     struct dw_spi *dws = dev_get_drvdata(dev);
0175
0176     return dw_spi_resume_host(dws);
0177 }
0178 #endif
0179
0180 static SIMPLE_DEV_PM_OPS(dw_spi_pci_pm_ops, dw_spi_pci_suspend, dw_spi_pci_resume);
0181
0182 static const struct pci_device_id dw_spi_pci_ids[] = {
0183     /* Intel MID platform SPI controller 0 */
0184     /*
0185      * The access to the device 8086:0801 is disabled by HW, since it's
0186      * exclusively used by SCU to communicate with MSIC.
0187      */
0188     /* Intel MID platform SPI controller 1 */
0189     { PCI_VDEVICE(INTEL, 0x0800), (kernel_ulong_t)&dw_spi_pci_mid_desc_1},
0190     /* Intel MID platform SPI controller 2 */
0191     { PCI_VDEVICE(INTEL, 0x0812), (kernel_ulong_t)&dw_spi_pci_mid_desc_2},
0192     /* Intel Elkhart Lake PSE SPI controllers */
0193     { PCI_VDEVICE(INTEL, 0x4b84), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
0194     { PCI_VDEVICE(INTEL, 0x4b85), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
0195     { PCI_VDEVICE(INTEL, 0x4b86), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
0196     { PCI_VDEVICE(INTEL, 0x4b87), (kernel_ulong_t)&dw_spi_pci_ehl_desc},
0197     {},
0198 };
0199 MODULE_DEVICE_TABLE(pci, dw_spi_pci_ids);
0200
0201 static struct pci_driver dw_spi_pci_driver = {
0202     .name =     DRIVER_NAME,
0203     .id_table = dw_spi_pci_ids,
0204     .probe =    dw_spi_pci_probe,
0205     .remove =   dw_spi_pci_remove,
0206     .driver         = {
0207         .pm     = &dw_spi_pci_pm_ops,
0208     },
0209 };
0210 module_pci_driver(dw_spi_pci_driver);
0211
0212 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
0213 MODULE_DESCRIPTION("PCI interface driver for DW SPI Core");
0214 MODULE_LICENSE("GPL v2");
0215 MODULE_IMPORT_NS(SPI_DW_CORE);