drivers/spi/spi-dw-core.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Designware SPI core controller driver (refer pxa2xx_spi.c)
0004  *
0005  * Copyright (c) 2009, Intel Corporation.
0006  */
0007
0008 #include <linux/bitfield.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/module.h>
0012 #include <linux/preempt.h>
0013 #include <linux/highmem.h>
0014 #include <linux/delay.h>
0015 #include <linux/slab.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/spi/spi-mem.h>
0018 #include <linux/string.h>
0019 #include <linux/of.h>
0020
0021 #include "spi-dw.h"
0022
0023 #ifdef CONFIG_DEBUG_FS
0024 #include <linux/debugfs.h>
0025 #endif
0026
0027 /* Slave spi_device related */
0028 struct dw_spi_chip_data {
0029     u32 cr0;
0030     u32 rx_sample_dly;  /* RX sample delay */
0031 };
0032
0033 #ifdef CONFIG_DEBUG_FS
0034
0035 #define DW_SPI_DBGFS_REG(_name, _off)   \
0036 {                   \
0037     .name = _name,          \
0038     .offset = _off,         \
0039 }
0040
0041 static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
0042     DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
0043     DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
0044     DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
0045     DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
0046     DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
0047     DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
0048     DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
0049     DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
0050     DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
0051     DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
0052     DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
0053     DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
0054     DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
0055     DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
0056     DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
0057     DW_SPI_DBGFS_REG("RX_SAMPLE_DLY", DW_SPI_RX_SAMPLE_DLY),
0058 };
0059
0060 static int dw_spi_debugfs_init(struct dw_spi *dws)
0061 {
0062     char name[32];
0063
0064     snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
0065     dws->debugfs = debugfs_create_dir(name, NULL);
0066     if (!dws->debugfs)
0067         return -ENOMEM;
0068
0069     dws->regset.regs = dw_spi_dbgfs_regs;
0070     dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
0071     dws->regset.base = dws->regs;
0072     debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
0073
0074     return 0;
0075 }
0076
0077 static void dw_spi_debugfs_remove(struct dw_spi *dws)
0078 {
0079     debugfs_remove_recursive(dws->debugfs);
0080 }
0081
0082 #else
0083 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
0084 {
0085     return 0;
0086 }
0087
0088 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
0089 {
0090 }
0091 #endif /* CONFIG_DEBUG_FS */
0092
0093 void dw_spi_set_cs(struct spi_device *spi, bool enable)
0094 {
0095     struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
0096     bool cs_high = !!(spi->mode & SPI_CS_HIGH);
0097
0098     /*
0099      * DW SPI controller demands any native CS being set in order to
0100      * proceed with data transfer. So in order to activate the SPI
0101      * communications we must set a corresponding bit in the Slave
0102      * Enable register no matter whether the SPI core is configured to
0103      * support active-high or active-low CS level.
0104      */
0105     if (cs_high == enable)
0106         dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
0107     else
0108         dw_writel(dws, DW_SPI_SER, 0);
0109 }
0110 EXPORT_SYMBOL_NS_GPL(dw_spi_set_cs, SPI_DW_CORE);
0111
0112 /* Return the max entries we can fill into tx fifo */
0113 static inline u32 dw_spi_tx_max(struct dw_spi *dws)
0114 {
0115     u32 tx_room, rxtx_gap;
0116
0117     tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
0118
0119     /*
0120      * Another concern is about the tx/rx mismatch, we
0121      * though to use (dws->fifo_len - rxflr - txflr) as
0122      * one maximum value for tx, but it doesn't cover the
0123      * data which is out of tx/rx fifo and inside the
0124      * shift registers. So a control from sw point of
0125      * view is taken.
0126      */
0127     rxtx_gap = dws->fifo_len - (dws->rx_len - dws->tx_len);
0128
0129     return min3((u32)dws->tx_len, tx_room, rxtx_gap);
0130 }
0131
0132 /* Return the max entries we should read out of rx fifo */
0133 static inline u32 dw_spi_rx_max(struct dw_spi *dws)
0134 {
0135     return min_t(u32, dws->rx_len, dw_readl(dws, DW_SPI_RXFLR));
0136 }
0137
0138 static void dw_writer(struct dw_spi *dws)
0139 {
0140     u32 max = dw_spi_tx_max(dws);
0141     u32 txw = 0;
0142
0143     while (max--) {
0144         if (dws->tx) {
0145             if (dws->n_bytes == 1)
0146                 txw = *(u8 *)(dws->tx);
0147             else if (dws->n_bytes == 2)
0148                 txw = *(u16 *)(dws->tx);
0149             else
0150                 txw = *(u32 *)(dws->tx);
0151
0152             dws->tx += dws->n_bytes;
0153         }
0154         dw_write_io_reg(dws, DW_SPI_DR, txw);
0155         --dws->tx_len;
0156     }
0157 }
0158
0159 static void dw_reader(struct dw_spi *dws)
0160 {
0161     u32 max = dw_spi_rx_max(dws);
0162     u32 rxw;
0163
0164     while (max--) {
0165         rxw = dw_read_io_reg(dws, DW_SPI_DR);
0166         if (dws->rx) {
0167             if (dws->n_bytes == 1)
0168                 *(u8 *)(dws->rx) = rxw;
0169             else if (dws->n_bytes == 2)
0170                 *(u16 *)(dws->rx) = rxw;
0171             else
0172                 *(u32 *)(dws->rx) = rxw;
0173
0174             dws->rx += dws->n_bytes;
0175         }
0176         --dws->rx_len;
0177     }
0178 }
0179
0180 int dw_spi_check_status(struct dw_spi *dws, bool raw)
0181 {
0182     u32 irq_status;
0183     int ret = 0;
0184
0185     if (raw)
0186         irq_status = dw_readl(dws, DW_SPI_RISR);
0187     else
0188         irq_status = dw_readl(dws, DW_SPI_ISR);
0189
0190     if (irq_status & DW_SPI_INT_RXOI) {
0191         dev_err(&dws->master->dev, "RX FIFO overflow detected\n");
0192         ret = -EIO;
0193     }
0194
0195     if (irq_status & DW_SPI_INT_RXUI) {
0196         dev_err(&dws->master->dev, "RX FIFO underflow detected\n");
0197         ret = -EIO;
0198     }
0199
0200     if (irq_status & DW_SPI_INT_TXOI) {
0201         dev_err(&dws->master->dev, "TX FIFO overflow detected\n");
0202         ret = -EIO;
0203     }
0204
0205     /* Generically handle the erroneous situation */
0206     if (ret) {
0207         dw_spi_reset_chip(dws);
0208         if (dws->master->cur_msg)
0209             dws->master->cur_msg->status = ret;
0210     }
0211
0212     return ret;
0213 }
0214 EXPORT_SYMBOL_NS_GPL(dw_spi_check_status, SPI_DW_CORE);
0215
0216 static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
0217 {
0218     u16 irq_status = dw_readl(dws, DW_SPI_ISR);
0219
0220     if (dw_spi_check_status(dws, false)) {
0221         spi_finalize_current_transfer(dws->master);
0222         return IRQ_HANDLED;
0223     }
0224
0225     /*
0226      * Read data from the Rx FIFO every time we've got a chance executing
0227      * this method. If there is nothing left to receive, terminate the
0228      * procedure. Otherwise adjust the Rx FIFO Threshold level if it's a
0229      * final stage of the transfer. By doing so we'll get the next IRQ
0230      * right when the leftover incoming data is received.
0231      */
0232     dw_reader(dws);
0233     if (!dws->rx_len) {
0234         dw_spi_mask_intr(dws, 0xff);
0235         spi_finalize_current_transfer(dws->master);
0236     } else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
0237         dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
0238     }
0239
0240     /*
0241      * Send data out if Tx FIFO Empty IRQ is received. The IRQ will be
0242      * disabled after the data transmission is finished so not to
0243      * have the TXE IRQ flood at the final stage of the transfer.
0244      */
0245     if (irq_status & DW_SPI_INT_TXEI) {
0246         dw_writer(dws);
0247         if (!dws->tx_len)
0248             dw_spi_mask_intr(dws, DW_SPI_INT_TXEI);
0249     }
0250
0251     return IRQ_HANDLED;
0252 }
0253
0254 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
0255 {
0256     struct spi_controller *master = dev_id;
0257     struct dw_spi *dws = spi_controller_get_devdata(master);
0258     u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
0259
0260     if (!irq_status)
0261         return IRQ_NONE;
0262
0263     if (!master->cur_msg) {
0264         dw_spi_mask_intr(dws, 0xff);
0265         return IRQ_HANDLED;
0266     }
0267
0268     return dws->transfer_handler(dws);
0269 }
0270
0271 static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
0272 {
0273     u32 cr0 = 0;
0274
0275     if (dw_spi_ip_is(dws, PSSI)) {
0276         /* CTRLR0[ 5: 4] Frame Format */
0277         cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
0278
0279         /*
0280          * SPI mode (SCPOL|SCPH)
0281          * CTRLR0[ 6] Serial Clock Phase
0282          * CTRLR0[ 7] Serial Clock Polarity
0283          */
0284         if (spi->mode & SPI_CPOL)
0285             cr0 |= DW_PSSI_CTRLR0_SCPOL;
0286         if (spi->mode & SPI_CPHA)
0287             cr0 |= DW_PSSI_CTRLR0_SCPHA;
0288
0289         /* CTRLR0[11] Shift Register Loop */
0290         if (spi->mode & SPI_LOOP)
0291             cr0 |= DW_PSSI_CTRLR0_SRL;
0292     } else {
0293         /* CTRLR0[ 7: 6] Frame Format */
0294         cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_FRF_MASK, DW_SPI_CTRLR0_FRF_MOTO_SPI);
0295
0296         /*
0297          * SPI mode (SCPOL|SCPH)
0298          * CTRLR0[ 8] Serial Clock Phase
0299          * CTRLR0[ 9] Serial Clock Polarity
0300          */
0301         if (spi->mode & SPI_CPOL)
0302             cr0 |= DW_HSSI_CTRLR0_SCPOL;
0303         if (spi->mode & SPI_CPHA)
0304             cr0 |= DW_HSSI_CTRLR0_SCPHA;
0305
0306         /* CTRLR0[13] Shift Register Loop */
0307         if (spi->mode & SPI_LOOP)
0308             cr0 |= DW_HSSI_CTRLR0_SRL;
0309
0310         /* CTRLR0[31] MST */
0311         if (dw_spi_ver_is_ge(dws, HSSI, 102A))
0312             cr0 |= DW_HSSI_CTRLR0_MST;
0313     }
0314
0315     return cr0;
0316 }
0317
0318 void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
0319               struct dw_spi_cfg *cfg)
0320 {
0321     struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
0322     u32 cr0 = chip->cr0;
0323     u32 speed_hz;
0324     u16 clk_div;
0325
0326     /* CTRLR0[ 4/3: 0] or CTRLR0[ 20: 16] Data Frame Size */
0327     cr0 |= (cfg->dfs - 1) << dws->dfs_offset;
0328
0329     if (dw_spi_ip_is(dws, PSSI))
0330         /* CTRLR0[ 9:8] Transfer Mode */
0331         cr0 |= FIELD_PREP(DW_PSSI_CTRLR0_TMOD_MASK, cfg->tmode);
0332     else
0333         /* CTRLR0[11:10] Transfer Mode */
0334         cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
0335
0336     dw_writel(dws, DW_SPI_CTRLR0, cr0);
0337
0338     if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD ||
0339         cfg->tmode == DW_SPI_CTRLR0_TMOD_RO)
0340         dw_writel(dws, DW_SPI_CTRLR1, cfg->ndf ? cfg->ndf - 1 : 0);
0341
0342     /* Note DW APB SSI clock divider doesn't support odd numbers */
0343     clk_div = (DIV_ROUND_UP(dws->max_freq, cfg->freq) + 1) & 0xfffe;
0344     speed_hz = dws->max_freq / clk_div;
0345
0346     if (dws->current_freq != speed_hz) {
0347         dw_spi_set_clk(dws, clk_div);
0348         dws->current_freq = speed_hz;
0349     }
0350
0351     /* Update RX sample delay if required */
0352     if (dws->cur_rx_sample_dly != chip->rx_sample_dly) {
0353         dw_writel(dws, DW_SPI_RX_SAMPLE_DLY, chip->rx_sample_dly);
0354         dws->cur_rx_sample_dly = chip->rx_sample_dly;
0355     }
0356 }
0357 EXPORT_SYMBOL_NS_GPL(dw_spi_update_config, SPI_DW_CORE);
0358
0359 static void dw_spi_irq_setup(struct dw_spi *dws)
0360 {
0361     u16 level;
0362     u8 imask;
0363
0364     /*
0365      * Originally Tx and Rx data lengths match. Rx FIFO Threshold level
0366      * will be adjusted at the final stage of the IRQ-based SPI transfer
0367      * execution so not to lose the leftover of the incoming data.
0368      */
0369     level = min_t(u16, dws->fifo_len / 2, dws->tx_len);
0370     dw_writel(dws, DW_SPI_TXFTLR, level);
0371     dw_writel(dws, DW_SPI_RXFTLR, level - 1);
0372
0373     dws->transfer_handler = dw_spi_transfer_handler;
0374
0375     imask = DW_SPI_INT_TXEI | DW_SPI_INT_TXOI |
0376         DW_SPI_INT_RXUI | DW_SPI_INT_RXOI | DW_SPI_INT_RXFI;
0377     dw_spi_umask_intr(dws, imask);
0378 }
0379
0380 /*
0381  * The iterative procedure of the poll-based transfer is simple: write as much
0382  * as possible to the Tx FIFO, wait until the pending to receive data is ready
0383  * to be read, read it from the Rx FIFO and check whether the performed
0384  * procedure has been successful.
0385  *
0386  * Note this method the same way as the IRQ-based transfer won't work well for
0387  * the SPI devices connected to the controller with native CS due to the
0388  * automatic CS assertion/de-assertion.
0389  */
0390 static int dw_spi_poll_transfer(struct dw_spi *dws,
0391                 struct spi_transfer *transfer)
0392 {
0393     struct spi_delay delay;
0394     u16 nbits;
0395     int ret;
0396
0397     delay.unit = SPI_DELAY_UNIT_SCK;
0398     nbits = dws->n_bytes * BITS_PER_BYTE;
0399
0400     do {
0401         dw_writer(dws);
0402
0403         delay.value = nbits * (dws->rx_len - dws->tx_len);
0404         spi_delay_exec(&delay, transfer);
0405
0406         dw_reader(dws);
0407
0408         ret = dw_spi_check_status(dws, true);
0409         if (ret)
0410             return ret;
0411     } while (dws->rx_len);
0412
0413     return 0;
0414 }
0415
0416 static int dw_spi_transfer_one(struct spi_controller *master,
0417                    struct spi_device *spi,
0418                    struct spi_transfer *transfer)
0419 {
0420     struct dw_spi *dws = spi_controller_get_devdata(master);
0421     struct dw_spi_cfg cfg = {
0422         .tmode = DW_SPI_CTRLR0_TMOD_TR,
0423         .dfs = transfer->bits_per_word,
0424         .freq = transfer->speed_hz,
0425     };
0426     int ret;
0427
0428     dws->dma_mapped = 0;
0429     dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
0430     dws->tx = (void *)transfer->tx_buf;
0431     dws->tx_len = transfer->len / dws->n_bytes;
0432     dws->rx = transfer->rx_buf;
0433     dws->rx_len = dws->tx_len;
0434
0435     /* Ensure the data above is visible for all CPUs */
0436     smp_mb();
0437
0438     dw_spi_enable_chip(dws, 0);
0439
0440     dw_spi_update_config(dws, spi, &cfg);
0441
0442     transfer->effective_speed_hz = dws->current_freq;
0443
0444     /* Check if current transfer is a DMA transaction */
0445     if (master->can_dma && master->can_dma(master, spi, transfer))
0446         dws->dma_mapped = master->cur_msg_mapped;
0447
0448     /* For poll mode just disable all interrupts */
0449     dw_spi_mask_intr(dws, 0xff);
0450
0451     if (dws->dma_mapped) {
0452         ret = dws->dma_ops->dma_setup(dws, transfer);
0453         if (ret)
0454             return ret;
0455     }
0456
0457     dw_spi_enable_chip(dws, 1);
0458
0459     if (dws->dma_mapped)
0460         return dws->dma_ops->dma_transfer(dws, transfer);
0461     else if (dws->irq == IRQ_NOTCONNECTED)
0462         return dw_spi_poll_transfer(dws, transfer);
0463
0464     dw_spi_irq_setup(dws);
0465
0466     return 1;
0467 }
0468
0469 static void dw_spi_handle_err(struct spi_controller *master,
0470                   struct spi_message *msg)
0471 {
0472     struct dw_spi *dws = spi_controller_get_devdata(master);
0473
0474     if (dws->dma_mapped)
0475         dws->dma_ops->dma_stop(dws);
0476
0477     dw_spi_reset_chip(dws);
0478 }
0479
0480 static int dw_spi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
0481 {
0482     if (op->data.dir == SPI_MEM_DATA_IN)
0483         op->data.nbytes = clamp_val(op->data.nbytes, 0, DW_SPI_NDF_MASK + 1);
0484
0485     return 0;
0486 }
0487
0488 static bool dw_spi_supports_mem_op(struct spi_mem *mem,
0489                    const struct spi_mem_op *op)
0490 {
0491     if (op->data.buswidth > 1 || op->addr.buswidth > 1 ||
0492         op->dummy.buswidth > 1 || op->cmd.buswidth > 1)
0493         return false;
0494
0495     return spi_mem_default_supports_op(mem, op);
0496 }
0497
0498 static int dw_spi_init_mem_buf(struct dw_spi *dws, const struct spi_mem_op *op)
0499 {
0500     unsigned int i, j, len;
0501     u8 *out;
0502
0503     /*
0504      * Calculate the total length of the EEPROM command transfer and
0505      * either use the pre-allocated buffer or create a temporary one.
0506      */
0507     len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
0508     if (op->data.dir == SPI_MEM_DATA_OUT)
0509         len += op->data.nbytes;
0510
0511     if (len <= DW_SPI_BUF_SIZE) {
0512         out = dws->buf;
0513     } else {
0514         out = kzalloc(len, GFP_KERNEL);
0515         if (!out)
0516             return -ENOMEM;
0517     }
0518
0519     /*
0520      * Collect the operation code, address and dummy bytes into the single
0521      * buffer. If it's a transfer with data to be sent, also copy it into the
0522      * single buffer in order to speed the data transmission up.
0523      */
0524     for (i = 0; i < op->cmd.nbytes; ++i)
0525         out[i] = DW_SPI_GET_BYTE(op->cmd.opcode, op->cmd.nbytes - i - 1);
0526     for (j = 0; j < op->addr.nbytes; ++i, ++j)
0527         out[i] = DW_SPI_GET_BYTE(op->addr.val, op->addr.nbytes - j - 1);
0528     for (j = 0; j < op->dummy.nbytes; ++i, ++j)
0529         out[i] = 0x0;
0530
0531     if (op->data.dir == SPI_MEM_DATA_OUT)
0532         memcpy(&out[i], op->data.buf.out, op->data.nbytes);
0533
0534     dws->n_bytes = 1;
0535     dws->tx = out;
0536     dws->tx_len = len;
0537     if (op->data.dir == SPI_MEM_DATA_IN) {
0538         dws->rx = op->data.buf.in;
0539         dws->rx_len = op->data.nbytes;
0540     } else {
0541         dws->rx = NULL;
0542         dws->rx_len = 0;
0543     }
0544
0545     return 0;
0546 }
0547
0548 static void dw_spi_free_mem_buf(struct dw_spi *dws)
0549 {
0550     if (dws->tx != dws->buf)
0551         kfree(dws->tx);
0552 }
0553
0554 static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)
0555 {
0556     u32 room, entries, sts;
0557     unsigned int len;
0558     u8 *buf;
0559
0560     /*
0561      * At initial stage we just pre-fill the Tx FIFO in with no rush,
0562      * since native CS hasn't been enabled yet and the automatic data
0563      * transmission won't start til we do that.
0564      */
0565     len = min(dws->fifo_len, dws->tx_len);
0566     buf = dws->tx;
0567     while (len--)
0568         dw_write_io_reg(dws, DW_SPI_DR, *buf++);
0569
0570     /*
0571      * After setting any bit in the SER register the transmission will
0572      * start automatically. We have to keep up with that procedure
0573      * otherwise the CS de-assertion will happen whereupon the memory
0574      * operation will be pre-terminated.
0575      */
0576     len = dws->tx_len - ((void *)buf - dws->tx);
0577     dw_spi_set_cs(spi, false);
0578     while (len) {
0579         entries = readl_relaxed(dws->regs + DW_SPI_TXFLR);
0580         if (!entries) {
0581             dev_err(&dws->master->dev, "CS de-assertion on Tx\n");
0582             return -EIO;
0583         }
0584         room = min(dws->fifo_len - entries, len);
0585         for (; room; --room, --len)
0586             dw_write_io_reg(dws, DW_SPI_DR, *buf++);
0587     }
0588
0589     /*
0590      * Data fetching will start automatically if the EEPROM-read mode is
0591      * activated. We have to keep up with the incoming data pace to
0592      * prevent the Rx FIFO overflow causing the inbound data loss.
0593      */
0594     len = dws->rx_len;
0595     buf = dws->rx;
0596     while (len) {
0597         entries = readl_relaxed(dws->regs + DW_SPI_RXFLR);
0598         if (!entries) {
0599             sts = readl_relaxed(dws->regs + DW_SPI_RISR);
0600             if (sts & DW_SPI_INT_RXOI) {
0601                 dev_err(&dws->master->dev, "FIFO overflow on Rx\n");
0602                 return -EIO;
0603             }
0604             continue;
0605         }
0606         entries = min(entries, len);
0607         for (; entries; --entries, --len)
0608             *buf++ = dw_read_io_reg(dws, DW_SPI_DR);
0609     }
0610
0611     return 0;
0612 }
0613
0614 static inline bool dw_spi_ctlr_busy(struct dw_spi *dws)
0615 {
0616     return dw_readl(dws, DW_SPI_SR) & DW_SPI_SR_BUSY;
0617 }
0618
0619 static int dw_spi_wait_mem_op_done(struct dw_spi *dws)
0620 {
0621     int retry = DW_SPI_WAIT_RETRIES;
0622     struct spi_delay delay;
0623     unsigned long ns, us;
0624     u32 nents;
0625
0626     nents = dw_readl(dws, DW_SPI_TXFLR);
0627     ns = NSEC_PER_SEC / dws->current_freq * nents;
0628     ns *= dws->n_bytes * BITS_PER_BYTE;
0629     if (ns <= NSEC_PER_USEC) {
0630         delay.unit = SPI_DELAY_UNIT_NSECS;
0631         delay.value = ns;
0632     } else {
0633         us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
0634         delay.unit = SPI_DELAY_UNIT_USECS;
0635         delay.value = clamp_val(us, 0, USHRT_MAX);
0636     }
0637
0638     while (dw_spi_ctlr_busy(dws) && retry--)
0639         spi_delay_exec(&delay, NULL);
0640
0641     if (retry < 0) {
0642         dev_err(&dws->master->dev, "Mem op hanged up\n");
0643         return -EIO;
0644     }
0645
0646     return 0;
0647 }
0648
0649 static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi)
0650 {
0651     dw_spi_enable_chip(dws, 0);
0652     dw_spi_set_cs(spi, true);
0653     dw_spi_enable_chip(dws, 1);
0654 }
0655
0656 /*
0657  * The SPI memory operation implementation below is the best choice for the
0658  * devices, which are selected by the native chip-select lane. It's
0659  * specifically developed to workaround the problem with automatic chip-select
0660  * lane toggle when there is no data in the Tx FIFO buffer. Luckily the current
0661  * SPI-mem core calls exec_op() callback only if the GPIO-based CS is
0662  * unavailable.
0663  */
0664 static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
0665 {
0666     struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
0667     struct dw_spi_cfg cfg;
0668     unsigned long flags;
0669     int ret;
0670
0671     /*
0672      * Collect the outbound data into a single buffer to speed the
0673      * transmission up at least on the initial stage.
0674      */
0675     ret = dw_spi_init_mem_buf(dws, op);
0676     if (ret)
0677         return ret;
0678
0679     /*
0680      * DW SPI EEPROM-read mode is required only for the SPI memory Data-IN
0681      * operation. Transmit-only mode is suitable for the rest of them.
0682      */
0683     cfg.dfs = 8;
0684     cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq);
0685     if (op->data.dir == SPI_MEM_DATA_IN) {
0686         cfg.tmode = DW_SPI_CTRLR0_TMOD_EPROMREAD;
0687         cfg.ndf = op->data.nbytes;
0688     } else {
0689         cfg.tmode = DW_SPI_CTRLR0_TMOD_TO;
0690     }
0691
0692     dw_spi_enable_chip(dws, 0);
0693
0694     dw_spi_update_config(dws, mem->spi, &cfg);
0695
0696     dw_spi_mask_intr(dws, 0xff);
0697
0698     dw_spi_enable_chip(dws, 1);
0699
0700     /*
0701      * DW APB SSI controller has very nasty peculiarities. First originally
0702      * (without any vendor-specific modifications) it doesn't provide a
0703      * direct way to set and clear the native chip-select signal. Instead
0704      * the controller asserts the CS lane if Tx FIFO isn't empty and a
0705      * transmission is going on, and automatically de-asserts it back to
0706      * the high level if the Tx FIFO doesn't have anything to be pushed
0707      * out. Due to that a multi-tasking or heavy IRQs activity might be
0708      * fatal, since the transfer procedure preemption may cause the Tx FIFO
0709      * getting empty and sudden CS de-assertion, which in the middle of the
0710      * transfer will most likely cause the data loss. Secondly the
0711      * EEPROM-read or Read-only DW SPI transfer modes imply the incoming
0712      * data being automatically pulled in into the Rx FIFO. So if the
0713      * driver software is late in fetching the data from the FIFO before
0714      * it's overflown, new incoming data will be lost. In order to make
0715      * sure the executed memory operations are CS-atomic and to prevent the
0716      * Rx FIFO overflow we have to disable the local interrupts so to block
0717      * any preemption during the subsequent IO operations.
0718      *
0719      * Note. At some circumstances disabling IRQs may not help to prevent
0720      * the problems described above. The CS de-assertion and Rx FIFO
0721      * overflow may still happen due to the relatively slow system bus or
0722      * CPU not working fast enough, so the write-then-read algo implemented
0723      * here just won't keep up with the SPI bus data transfer. Such
0724      * situation is highly platform specific and is supposed to be fixed by
0725      * manually restricting the SPI bus frequency using the
0726      * dws->max_mem_freq parameter.
0727      */
0728     local_irq_save(flags);
0729     preempt_disable();
0730
0731     ret = dw_spi_write_then_read(dws, mem->spi);
0732
0733     local_irq_restore(flags);
0734     preempt_enable();
0735
0736     /*
0737      * Wait for the operation being finished and check the controller
0738      * status only if there hasn't been any run-time error detected. In the
0739      * former case it's just pointless. In the later one to prevent an
0740      * additional error message printing since any hw error flag being set
0741      * would be due to an error detected on the data transfer.
0742      */
0743     if (!ret) {
0744         ret = dw_spi_wait_mem_op_done(dws);
0745         if (!ret)
0746             ret = dw_spi_check_status(dws, true);
0747     }
0748
0749     dw_spi_stop_mem_op(dws, mem->spi);
0750
0751     dw_spi_free_mem_buf(dws);
0752
0753     return ret;
0754 }
0755
0756 /*
0757  * Initialize the default memory operations if a glue layer hasn't specified
0758  * custom ones. Direct mapping operations will be preserved anyway since DW SPI
0759  * controller doesn't have an embedded dirmap interface. Note the memory
0760  * operations implemented in this driver is the best choice only for the DW APB
0761  * SSI controller with standard native CS functionality. If a hardware vendor
0762  * has fixed the automatic CS assertion/de-assertion peculiarity, then it will
0763  * be safer to use the normal SPI-messages-based transfers implementation.
0764  */
0765 static void dw_spi_init_mem_ops(struct dw_spi *dws)
0766 {
0767     if (!dws->mem_ops.exec_op && !(dws->caps & DW_SPI_CAP_CS_OVERRIDE) &&
0768         !dws->set_cs) {
0769         dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size;
0770         dws->mem_ops.supports_op = dw_spi_supports_mem_op;
0771         dws->mem_ops.exec_op = dw_spi_exec_mem_op;
0772         if (!dws->max_mem_freq)
0773             dws->max_mem_freq = dws->max_freq;
0774     }
0775 }
0776
0777 /* This may be called twice for each spi dev */
0778 static int dw_spi_setup(struct spi_device *spi)
0779 {
0780     struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
0781     struct dw_spi_chip_data *chip;
0782
0783     /* Only alloc on first setup */
0784     chip = spi_get_ctldata(spi);
0785     if (!chip) {
0786         struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
0787         u32 rx_sample_dly_ns;
0788
0789         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
0790         if (!chip)
0791             return -ENOMEM;
0792         spi_set_ctldata(spi, chip);
0793         /* Get specific / default rx-sample-delay */
0794         if (device_property_read_u32(&spi->dev,
0795                          "rx-sample-delay-ns",
0796                          &rx_sample_dly_ns) != 0)
0797             /* Use default controller value */
0798             rx_sample_dly_ns = dws->def_rx_sample_dly_ns;
0799         chip->rx_sample_dly = DIV_ROUND_CLOSEST(rx_sample_dly_ns,
0800                             NSEC_PER_SEC /
0801                             dws->max_freq);
0802     }
0803
0804     /*
0805      * Update CR0 data each time the setup callback is invoked since
0806      * the device parameters could have been changed, for instance, by
0807      * the MMC SPI driver or something else.
0808      */
0809     chip->cr0 = dw_spi_prepare_cr0(dws, spi);
0810
0811     return 0;
0812 }
0813
0814 static void dw_spi_cleanup(struct spi_device *spi)
0815 {
0816     struct dw_spi_chip_data *chip = spi_get_ctldata(spi);
0817
0818     kfree(chip);
0819     spi_set_ctldata(spi, NULL);
0820 }
0821
0822 /* Restart the controller, disable all interrupts, clean rx fifo */
0823 static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)
0824 {
0825     dw_spi_reset_chip(dws);
0826
0827     /*
0828      * Retrieve the Synopsys component version if it hasn't been specified
0829      * by the platform. CoreKit version ID is encoded as a 3-chars ASCII
0830      * code enclosed with '*' (typical for the most of Synopsys IP-cores).
0831      */
0832     if (!dws->ver) {
0833         dws->ver = dw_readl(dws, DW_SPI_VERSION);
0834
0835         dev_dbg(dev, "Synopsys DWC%sSSI v%c.%c%c\n",
0836             dw_spi_ip_is(dws, PSSI) ? " APB " : " ",
0837             DW_SPI_GET_BYTE(dws->ver, 3), DW_SPI_GET_BYTE(dws->ver, 2),
0838             DW_SPI_GET_BYTE(dws->ver, 1));
0839     }
0840
0841     /*
0842      * Try to detect the FIFO depth if not set by interface driver,
0843      * the depth could be from 2 to 256 from HW spec
0844      */
0845     if (!dws->fifo_len) {
0846         u32 fifo;
0847
0848         for (fifo = 1; fifo < 256; fifo++) {
0849             dw_writel(dws, DW_SPI_TXFTLR, fifo);
0850             if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
0851                 break;
0852         }
0853         dw_writel(dws, DW_SPI_TXFTLR, 0);
0854
0855         dws->fifo_len = (fifo == 1) ? 0 : fifo;
0856         dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
0857     }
0858
0859     /*
0860      * Detect CTRLR0.DFS field size and offset by testing the lowest bits
0861      * writability. Note DWC SSI controller also has the extended DFS, but
0862      * with zero offset.
0863      */
0864     if (dw_spi_ip_is(dws, PSSI)) {
0865         u32 cr0, tmp = dw_readl(dws, DW_SPI_CTRLR0);
0866
0867         dw_spi_enable_chip(dws, 0);
0868         dw_writel(dws, DW_SPI_CTRLR0, 0xffffffff);
0869         cr0 = dw_readl(dws, DW_SPI_CTRLR0);
0870         dw_writel(dws, DW_SPI_CTRLR0, tmp);
0871         dw_spi_enable_chip(dws, 1);
0872
0873         if (!(cr0 & DW_PSSI_CTRLR0_DFS_MASK)) {
0874             dws->caps |= DW_SPI_CAP_DFS32;
0875             dws->dfs_offset = __bf_shf(DW_PSSI_CTRLR0_DFS32_MASK);
0876             dev_dbg(dev, "Detected 32-bits max data frame size\n");
0877         }
0878     } else {
0879         dws->caps |= DW_SPI_CAP_DFS32;
0880     }
0881
0882     /* enable HW fixup for explicit CS deselect for Amazon's alpine chip */
0883     if (dws->caps & DW_SPI_CAP_CS_OVERRIDE)
0884         dw_writel(dws, DW_SPI_CS_OVERRIDE, 0xF);
0885 }
0886
0887 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
0888 {
0889     struct spi_controller *master;
0890     int ret;
0891
0892     if (!dws)
0893         return -EINVAL;
0894
0895     master = spi_alloc_master(dev, 0);
0896     if (!master)
0897         return -ENOMEM;
0898
0899     device_set_node(&master->dev, dev_fwnode(dev));
0900
0901     dws->master = master;
0902     dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
0903
0904     spi_controller_set_devdata(master, dws);
0905
0906     /* Basic HW init */
0907     dw_spi_hw_init(dev, dws);
0908
0909     ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
0910               master);
0911     if (ret < 0 && ret != -ENOTCONN) {
0912         dev_err(dev, "can not get IRQ\n");
0913         goto err_free_master;
0914     }
0915
0916     dw_spi_init_mem_ops(dws);
0917
0918     master->use_gpio_descriptors = true;
0919     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
0920     if (dws->caps & DW_SPI_CAP_DFS32)
0921         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
0922     else
0923         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
0924     master->bus_num = dws->bus_num;
0925     master->num_chipselect = dws->num_cs;
0926     master->setup = dw_spi_setup;
0927     master->cleanup = dw_spi_cleanup;
0928     if (dws->set_cs)
0929         master->set_cs = dws->set_cs;
0930     else
0931         master->set_cs = dw_spi_set_cs;
0932     master->transfer_one = dw_spi_transfer_one;
0933     master->handle_err = dw_spi_handle_err;
0934     if (dws->mem_ops.exec_op)
0935         master->mem_ops = &dws->mem_ops;
0936     master->max_speed_hz = dws->max_freq;
0937     master->flags = SPI_MASTER_GPIO_SS;
0938     master->auto_runtime_pm = true;
0939
0940     /* Get default rx sample delay */
0941     device_property_read_u32(dev, "rx-sample-delay-ns",
0942                  &dws->def_rx_sample_dly_ns);
0943
0944     if (dws->dma_ops && dws->dma_ops->dma_init) {
0945         ret = dws->dma_ops->dma_init(dev, dws);
0946         if (ret == -EPROBE_DEFER) {
0947             goto err_free_irq;
0948         } else if (ret) {
0949             dev_warn(dev, "DMA init failed\n");
0950         } else {
0951             master->can_dma = dws->dma_ops->can_dma;
0952             master->flags |= SPI_CONTROLLER_MUST_TX;
0953         }
0954     }
0955
0956     ret = spi_register_controller(master);
0957     if (ret) {
0958         dev_err(&master->dev, "problem registering spi master\n");
0959         goto err_dma_exit;
0960     }
0961
0962     dw_spi_debugfs_init(dws);
0963     return 0;
0964
0965 err_dma_exit:
0966     if (dws->dma_ops && dws->dma_ops->dma_exit)
0967         dws->dma_ops->dma_exit(dws);
0968     dw_spi_enable_chip(dws, 0);
0969 err_free_irq:
0970     free_irq(dws->irq, master);
0971 err_free_master:
0972     spi_controller_put(master);
0973     return ret;
0974 }
0975 EXPORT_SYMBOL_NS_GPL(dw_spi_add_host, SPI_DW_CORE);
0976
0977 void dw_spi_remove_host(struct dw_spi *dws)
0978 {
0979     dw_spi_debugfs_remove(dws);
0980
0981     spi_unregister_controller(dws->master);
0982
0983     if (dws->dma_ops && dws->dma_ops->dma_exit)
0984         dws->dma_ops->dma_exit(dws);
0985
0986     dw_spi_shutdown_chip(dws);
0987
0988     free_irq(dws->irq, dws->master);
0989 }
0990 EXPORT_SYMBOL_NS_GPL(dw_spi_remove_host, SPI_DW_CORE);
0991
0992 int dw_spi_suspend_host(struct dw_spi *dws)
0993 {
0994     int ret;
0995
0996     ret = spi_controller_suspend(dws->master);
0997     if (ret)
0998         return ret;
0999
1000     dw_spi_shutdown_chip(dws);
1001     return 0;
1002 }
1003 EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_host, SPI_DW_CORE);
1004
1005 int dw_spi_resume_host(struct dw_spi *dws)
1006 {
1007     dw_spi_hw_init(&dws->master->dev, dws);
1008     return spi_controller_resume(dws->master);
1009 }
1010 EXPORT_SYMBOL_NS_GPL(dw_spi_resume_host, SPI_DW_CORE);
1011
1012 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
1013 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1014 MODULE_LICENSE("GPL v2");