drivers/spi/spi-dln2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the Diolan DLN-2 USB-SPI adapter
0004  *
0005  * Copyright (c) 2014 Intel Corporation
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/property.h>
0012 #include <linux/mfd/dln2.h>
0013 #include <linux/spi/spi.h>
0014 #include <linux/pm_runtime.h>
0015 #include <asm/unaligned.h>
0016
0017 #define DLN2_SPI_MODULE_ID      0x02
0018 #define DLN2_SPI_CMD(cmd)       DLN2_CMD(cmd, DLN2_SPI_MODULE_ID)
0019
0020 /* SPI commands */
0021 #define DLN2_SPI_GET_PORT_COUNT         DLN2_SPI_CMD(0x00)
0022 #define DLN2_SPI_ENABLE             DLN2_SPI_CMD(0x11)
0023 #define DLN2_SPI_DISABLE            DLN2_SPI_CMD(0x12)
0024 #define DLN2_SPI_IS_ENABLED         DLN2_SPI_CMD(0x13)
0025 #define DLN2_SPI_SET_MODE           DLN2_SPI_CMD(0x14)
0026 #define DLN2_SPI_GET_MODE           DLN2_SPI_CMD(0x15)
0027 #define DLN2_SPI_SET_FRAME_SIZE         DLN2_SPI_CMD(0x16)
0028 #define DLN2_SPI_GET_FRAME_SIZE         DLN2_SPI_CMD(0x17)
0029 #define DLN2_SPI_SET_FREQUENCY          DLN2_SPI_CMD(0x18)
0030 #define DLN2_SPI_GET_FREQUENCY          DLN2_SPI_CMD(0x19)
0031 #define DLN2_SPI_READ_WRITE         DLN2_SPI_CMD(0x1A)
0032 #define DLN2_SPI_READ               DLN2_SPI_CMD(0x1B)
0033 #define DLN2_SPI_WRITE              DLN2_SPI_CMD(0x1C)
0034 #define DLN2_SPI_SET_DELAY_BETWEEN_SS       DLN2_SPI_CMD(0x20)
0035 #define DLN2_SPI_GET_DELAY_BETWEEN_SS       DLN2_SPI_CMD(0x21)
0036 #define DLN2_SPI_SET_DELAY_AFTER_SS     DLN2_SPI_CMD(0x22)
0037 #define DLN2_SPI_GET_DELAY_AFTER_SS     DLN2_SPI_CMD(0x23)
0038 #define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES   DLN2_SPI_CMD(0x24)
0039 #define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES   DLN2_SPI_CMD(0x25)
0040 #define DLN2_SPI_SET_SS             DLN2_SPI_CMD(0x26)
0041 #define DLN2_SPI_GET_SS             DLN2_SPI_CMD(0x27)
0042 #define DLN2_SPI_RELEASE_SS         DLN2_SPI_CMD(0x28)
0043 #define DLN2_SPI_SS_VARIABLE_ENABLE     DLN2_SPI_CMD(0x2B)
0044 #define DLN2_SPI_SS_VARIABLE_DISABLE        DLN2_SPI_CMD(0x2C)
0045 #define DLN2_SPI_SS_VARIABLE_IS_ENABLED     DLN2_SPI_CMD(0x2D)
0046 #define DLN2_SPI_SS_AAT_ENABLE          DLN2_SPI_CMD(0x2E)
0047 #define DLN2_SPI_SS_AAT_DISABLE         DLN2_SPI_CMD(0x2F)
0048 #define DLN2_SPI_SS_AAT_IS_ENABLED      DLN2_SPI_CMD(0x30)
0049 #define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE   DLN2_SPI_CMD(0x31)
0050 #define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE  DLN2_SPI_CMD(0x32)
0051 #define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED   DLN2_SPI_CMD(0x33)
0052 #define DLN2_SPI_SET_CPHA           DLN2_SPI_CMD(0x34)
0053 #define DLN2_SPI_GET_CPHA           DLN2_SPI_CMD(0x35)
0054 #define DLN2_SPI_SET_CPOL           DLN2_SPI_CMD(0x36)
0055 #define DLN2_SPI_GET_CPOL           DLN2_SPI_CMD(0x37)
0056 #define DLN2_SPI_SS_MULTI_ENABLE        DLN2_SPI_CMD(0x38)
0057 #define DLN2_SPI_SS_MULTI_DISABLE       DLN2_SPI_CMD(0x39)
0058 #define DLN2_SPI_SS_MULTI_IS_ENABLED        DLN2_SPI_CMD(0x3A)
0059 #define DLN2_SPI_GET_SUPPORTED_MODES        DLN2_SPI_CMD(0x40)
0060 #define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES  DLN2_SPI_CMD(0x41)
0061 #define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES  DLN2_SPI_CMD(0x42)
0062 #define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES  DLN2_SPI_CMD(0x43)
0063 #define DLN2_SPI_GET_SS_COUNT           DLN2_SPI_CMD(0x44)
0064 #define DLN2_SPI_GET_MIN_FREQUENCY      DLN2_SPI_CMD(0x45)
0065 #define DLN2_SPI_GET_MAX_FREQUENCY      DLN2_SPI_CMD(0x46)
0066 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS   DLN2_SPI_CMD(0x47)
0067 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS   DLN2_SPI_CMD(0x48)
0068 #define DLN2_SPI_GET_MIN_DELAY_AFTER_SS     DLN2_SPI_CMD(0x49)
0069 #define DLN2_SPI_GET_MAX_DELAY_AFTER_SS     DLN2_SPI_CMD(0x4A)
0070 #define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES   DLN2_SPI_CMD(0x4B)
0071 #define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES   DLN2_SPI_CMD(0x4C)
0072
0073 #define DLN2_SPI_MAX_XFER_SIZE          256
0074 #define DLN2_SPI_BUF_SIZE           (DLN2_SPI_MAX_XFER_SIZE + 16)
0075 #define DLN2_SPI_ATTR_LEAVE_SS_LOW      BIT(0)
0076 #define DLN2_TRANSFERS_WAIT_COMPLETE        1
0077 #define DLN2_TRANSFERS_CANCEL           0
0078 #define DLN2_RPM_AUTOSUSPEND_TIMEOUT        2000
0079
0080 struct dln2_spi {
0081     struct platform_device *pdev;
0082     struct spi_master *master;
0083     u8 port;
0084
0085     /*
0086      * This buffer will be used mainly for read/write operations. Since
0087      * they're quite large, we cannot use the stack. Protection is not
0088      * needed because all SPI communication is serialized by the SPI core.
0089      */
0090     void *buf;
0091
0092     u8 bpw;
0093     u32 speed;
0094     u16 mode;
0095     u8 cs;
0096 };
0097
0098 /*
0099  * Enable/Disable SPI module. The disable command will wait for transfers to
0100  * complete first.
0101  */
0102 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
0103 {
0104     u16 cmd;
0105     struct {
0106         u8 port;
0107         u8 wait_for_completion;
0108     } tx;
0109     unsigned len = sizeof(tx);
0110
0111     tx.port = dln2->port;
0112
0113     if (enable) {
0114         cmd = DLN2_SPI_ENABLE;
0115         len -= sizeof(tx.wait_for_completion);
0116     } else {
0117         tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE;
0118         cmd = DLN2_SPI_DISABLE;
0119     }
0120
0121     return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
0122 }
0123
0124 /*
0125  * Select/unselect multiple CS lines. The selected lines will be automatically
0126  * toggled LOW/HIGH by the board firmware during transfers, provided they're
0127  * enabled first.
0128  *
0129  * Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation
0130  *                       will toggle the lines LOW/HIGH automatically.
0131  */
0132 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
0133 {
0134     struct {
0135         u8 port;
0136         u8 cs;
0137     } tx;
0138
0139     tx.port = dln2->port;
0140
0141     /*
0142      * According to Diolan docs, "a slave device can be selected by changing
0143      * the corresponding bit value to 0". The rest must be set to 1. Hence
0144      * the bitwise NOT in front.
0145      */
0146     tx.cs = ~cs_mask;
0147
0148     return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
0149 }
0150
0151 /*
0152  * Select one CS line. The other lines will be un-selected.
0153  */
0154 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
0155 {
0156     return dln2_spi_cs_set(dln2, BIT(cs));
0157 }
0158
0159 /*
0160  * Enable/disable CS lines for usage. The module has to be disabled first.
0161  */
0162 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
0163 {
0164     struct {
0165         u8 port;
0166         u8 cs;
0167     } tx;
0168     u16 cmd;
0169
0170     tx.port = dln2->port;
0171     tx.cs = cs_mask;
0172     cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE;
0173
0174     return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
0175 }
0176
0177 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
0178 {
0179     u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
0180
0181     return dln2_spi_cs_enable(dln2, cs_mask, enable);
0182 }
0183
0184 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
0185 {
0186     int ret;
0187     struct {
0188         u8 port;
0189     } tx;
0190     struct {
0191         __le16 cs_count;
0192     } rx;
0193     unsigned rx_len = sizeof(rx);
0194
0195     tx.port = dln2->port;
0196     ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
0197                 &rx, &rx_len);
0198     if (ret < 0)
0199         return ret;
0200     if (rx_len < sizeof(rx))
0201         return -EPROTO;
0202
0203     *cs_num = le16_to_cpu(rx.cs_count);
0204
0205     dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
0206
0207     return 0;
0208 }
0209
0210 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
0211 {
0212     int ret;
0213     struct {
0214         u8 port;
0215     } tx;
0216     struct {
0217         __le32 speed;
0218     } rx;
0219     unsigned rx_len = sizeof(rx);
0220
0221     tx.port = dln2->port;
0222
0223     ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
0224     if (ret < 0)
0225         return ret;
0226     if (rx_len < sizeof(rx))
0227         return -EPROTO;
0228
0229     *freq = le32_to_cpu(rx.speed);
0230
0231     return 0;
0232 }
0233
0234 /*
0235  * Get bus min/max frequencies.
0236  */
0237 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
0238 {
0239     int ret;
0240
0241     ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
0242     if (ret < 0)
0243         return ret;
0244
0245     ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
0246     if (ret < 0)
0247         return ret;
0248
0249     dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
0250         *fmin, *fmax);
0251
0252     return 0;
0253 }
0254
0255 /*
0256  * Set the bus speed. The module will automatically round down to the closest
0257  * available frequency and returns it. The module has to be disabled first.
0258  */
0259 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
0260 {
0261     int ret;
0262     struct {
0263         u8 port;
0264         __le32 speed;
0265     } __packed tx;
0266     struct {
0267         __le32 speed;
0268     } rx;
0269     int rx_len = sizeof(rx);
0270
0271     tx.port = dln2->port;
0272     tx.speed = cpu_to_le32(speed);
0273
0274     ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
0275                 &rx, &rx_len);
0276     if (ret < 0)
0277         return ret;
0278     if (rx_len < sizeof(rx))
0279         return -EPROTO;
0280
0281     return 0;
0282 }
0283
0284 /*
0285  * Change CPOL & CPHA. The module has to be disabled first.
0286  */
0287 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
0288 {
0289     struct {
0290         u8 port;
0291         u8 mode;
0292     } tx;
0293
0294     tx.port = dln2->port;
0295     tx.mode = mode;
0296
0297     return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
0298 }
0299
0300 /*
0301  * Change frame size. The module has to be disabled first.
0302  */
0303 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
0304 {
0305     struct {
0306         u8 port;
0307         u8 bpw;
0308     } tx;
0309
0310     tx.port = dln2->port;
0311     tx.bpw = bpw;
0312
0313     return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
0314                 &tx, sizeof(tx));
0315 }
0316
0317 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
0318                           u32 *bpw_mask)
0319 {
0320     int ret;
0321     struct {
0322         u8 port;
0323     } tx;
0324     struct {
0325         u8 count;
0326         u8 frame_sizes[36];
0327     } *rx = dln2->buf;
0328     unsigned rx_len = sizeof(*rx);
0329     int i;
0330
0331     tx.port = dln2->port;
0332
0333     ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
0334                 &tx, sizeof(tx), rx, &rx_len);
0335     if (ret < 0)
0336         return ret;
0337     if (rx_len < sizeof(*rx))
0338         return -EPROTO;
0339     if (rx->count > ARRAY_SIZE(rx->frame_sizes))
0340         return -EPROTO;
0341
0342     *bpw_mask = 0;
0343     for (i = 0; i < rx->count; i++)
0344         *bpw_mask |= BIT(rx->frame_sizes[i] - 1);
0345
0346     dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
0347
0348     return 0;
0349 }
0350
0351 /*
0352  * Copy the data to DLN2 buffer and change the byte order to LE, requested by
0353  * DLN2 module. SPI core makes sure that the data length is a multiple of word
0354  * size.
0355  */
0356 static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw)
0357 {
0358 #ifdef __LITTLE_ENDIAN
0359     memcpy(dln2_buf, src, len);
0360 #else
0361     if (bpw <= 8) {
0362         memcpy(dln2_buf, src, len);
0363     } else if (bpw <= 16) {
0364         __le16 *d = (__le16 *)dln2_buf;
0365         u16 *s = (u16 *)src;
0366
0367         len = len / 2;
0368         while (len--)
0369             *d++ = cpu_to_le16p(s++);
0370     } else {
0371         __le32 *d = (__le32 *)dln2_buf;
0372         u32 *s = (u32 *)src;
0373
0374         len = len / 4;
0375         while (len--)
0376             *d++ = cpu_to_le32p(s++);
0377     }
0378 #endif
0379
0380     return 0;
0381 }
0382
0383 /*
0384  * Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2
0385  * buffer is LE ordered. SPI core makes sure that the data length is a multiple
0386  * of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make
0387  * sure we avoid unaligned accesses for 32 bit case.
0388  */
0389 static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw)
0390 {
0391 #ifdef __LITTLE_ENDIAN
0392     memcpy(dest, dln2_buf, len);
0393 #else
0394     if (bpw <= 8) {
0395         memcpy(dest, dln2_buf, len);
0396     } else if (bpw <= 16) {
0397         u16 *d = (u16 *)dest;
0398         __le16 *s = (__le16 *)dln2_buf;
0399
0400         len = len / 2;
0401         while (len--)
0402             *d++ = le16_to_cpup(s++);
0403     } else {
0404         u32 *d = (u32 *)dest;
0405         __le32 *s = (__le32 *)dln2_buf;
0406
0407         len = len / 4;
0408         while (len--)
0409             *d++ = get_unaligned_le32(s++);
0410     }
0411 #endif
0412
0413     return 0;
0414 }
0415
0416 /*
0417  * Perform one write operation.
0418  */
0419 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
0420                   u16 data_len, u8 attr)
0421 {
0422     struct {
0423         u8 port;
0424         __le16 size;
0425         u8 attr;
0426         u8 buf[DLN2_SPI_MAX_XFER_SIZE];
0427     } __packed *tx = dln2->buf;
0428     unsigned tx_len;
0429
0430     BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE);
0431
0432     if (data_len > DLN2_SPI_MAX_XFER_SIZE)
0433         return -EINVAL;
0434
0435     tx->port = dln2->port;
0436     tx->size = cpu_to_le16(data_len);
0437     tx->attr = attr;
0438
0439     dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
0440
0441     tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
0442     return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
0443 }
0444
0445 /*
0446  * Perform one read operation.
0447  */
0448 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
0449                  u16 data_len, u8 attr)
0450 {
0451     int ret;
0452     struct {
0453         u8 port;
0454         __le16 size;
0455         u8 attr;
0456     } __packed tx;
0457     struct {
0458         __le16 size;
0459         u8 buf[DLN2_SPI_MAX_XFER_SIZE];
0460     } __packed *rx = dln2->buf;
0461     unsigned rx_len = sizeof(*rx);
0462
0463     BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE);
0464
0465     if (data_len > DLN2_SPI_MAX_XFER_SIZE)
0466         return -EINVAL;
0467
0468     tx.port = dln2->port;
0469     tx.size = cpu_to_le16(data_len);
0470     tx.attr = attr;
0471
0472     ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
0473                 rx, &rx_len);
0474     if (ret < 0)
0475         return ret;
0476     if (rx_len < sizeof(rx->size) + data_len)
0477         return -EPROTO;
0478     if (le16_to_cpu(rx->size) != data_len)
0479         return -EPROTO;
0480
0481     dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
0482
0483     return 0;
0484 }
0485
0486 /*
0487  * Perform one write & read operation.
0488  */
0489 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
0490                    u8 *rx_data, u16 data_len, u8 attr)
0491 {
0492     int ret;
0493     struct {
0494         u8 port;
0495         __le16 size;
0496         u8 attr;
0497         u8 buf[DLN2_SPI_MAX_XFER_SIZE];
0498     } __packed *tx;
0499     struct {
0500         __le16 size;
0501         u8 buf[DLN2_SPI_MAX_XFER_SIZE];
0502     } __packed *rx;
0503     unsigned tx_len, rx_len;
0504
0505     BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE ||
0506              sizeof(*rx) > DLN2_SPI_BUF_SIZE);
0507
0508     if (data_len > DLN2_SPI_MAX_XFER_SIZE)
0509         return -EINVAL;
0510
0511     /*
0512      * Since this is a pseudo full-duplex communication, we're perfectly
0513      * safe to use the same buffer for both tx and rx. When DLN2 sends the
0514      * response back, with the rx data, we don't need the tx buffer anymore.
0515      */
0516     tx = dln2->buf;
0517     rx = dln2->buf;
0518
0519     tx->port = dln2->port;
0520     tx->size = cpu_to_le16(data_len);
0521     tx->attr = attr;
0522
0523     dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
0524
0525     tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE;
0526     rx_len = sizeof(*rx);
0527
0528     ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
0529                 rx, &rx_len);
0530     if (ret < 0)
0531         return ret;
0532     if (rx_len < sizeof(rx->size) + data_len)
0533         return -EPROTO;
0534     if (le16_to_cpu(rx->size) != data_len)
0535         return -EPROTO;
0536
0537     dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
0538
0539     return 0;
0540 }
0541
0542 /*
0543  * Read/Write wrapper. It will automatically split an operation into multiple
0544  * single ones due to device buffer constraints.
0545  */
0546 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
0547              u8 *rx_data, u16 data_len, u8 attr)
0548 {
0549     int ret;
0550     u16 len;
0551     u8 temp_attr;
0552     u16 remaining = data_len;
0553     u16 offset;
0554
0555     do {
0556         if (remaining > DLN2_SPI_MAX_XFER_SIZE) {
0557             len = DLN2_SPI_MAX_XFER_SIZE;
0558             temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
0559         } else {
0560             len = remaining;
0561             temp_attr = attr;
0562         }
0563
0564         offset = data_len - remaining;
0565
0566         if (tx_data && rx_data) {
0567             ret = dln2_spi_read_write_one(dln2,
0568                               tx_data + offset,
0569                               rx_data + offset,
0570                               len, temp_attr);
0571         } else if (tx_data) {
0572             ret = dln2_spi_write_one(dln2,
0573                          tx_data + offset,
0574                          len, temp_attr);
0575         } else if (rx_data) {
0576             ret = dln2_spi_read_one(dln2,
0577                         rx_data + offset,
0578                         len, temp_attr);
0579          } else {
0580             return -EINVAL;
0581          }
0582
0583         if (ret < 0)
0584             return ret;
0585
0586         remaining -= len;
0587     } while (remaining);
0588
0589     return 0;
0590 }
0591
0592 static int dln2_spi_prepare_message(struct spi_master *master,
0593                     struct spi_message *message)
0594 {
0595     int ret;
0596     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0597     struct spi_device *spi = message->spi;
0598
0599     if (dln2->cs != spi->chip_select) {
0600         ret = dln2_spi_cs_set_one(dln2, spi->chip_select);
0601         if (ret < 0)
0602             return ret;
0603
0604         dln2->cs = spi->chip_select;
0605     }
0606
0607     return 0;
0608 }
0609
0610 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
0611                    u8 bpw, u8 mode)
0612 {
0613     int ret;
0614     bool bus_setup_change;
0615
0616     bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
0617                dln2->bpw != bpw;
0618
0619     if (!bus_setup_change)
0620         return 0;
0621
0622     ret = dln2_spi_enable(dln2, false);
0623     if (ret < 0)
0624         return ret;
0625
0626     if (dln2->speed != speed) {
0627         ret = dln2_spi_set_speed(dln2, speed);
0628         if (ret < 0)
0629             return ret;
0630
0631         dln2->speed = speed;
0632     }
0633
0634     if (dln2->mode != mode) {
0635         ret = dln2_spi_set_mode(dln2, mode & 0x3);
0636         if (ret < 0)
0637             return ret;
0638
0639         dln2->mode = mode;
0640     }
0641
0642     if (dln2->bpw != bpw) {
0643         ret = dln2_spi_set_bpw(dln2, bpw);
0644         if (ret < 0)
0645             return ret;
0646
0647         dln2->bpw = bpw;
0648     }
0649
0650     return dln2_spi_enable(dln2, true);
0651 }
0652
0653 static int dln2_spi_transfer_one(struct spi_master *master,
0654                  struct spi_device *spi,
0655                  struct spi_transfer *xfer)
0656 {
0657     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0658     int status;
0659     u8 attr = 0;
0660
0661     status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
0662                      xfer->bits_per_word,
0663                      spi->mode);
0664     if (status < 0) {
0665         dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
0666         return status;
0667     }
0668
0669     if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
0670         attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
0671
0672     status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
0673                    xfer->len, attr);
0674     if (status < 0)
0675         dev_err(&dln2->pdev->dev, "write/read failed!\n");
0676
0677     return status;
0678 }
0679
0680 static int dln2_spi_probe(struct platform_device *pdev)
0681 {
0682     struct spi_master *master;
0683     struct dln2_spi *dln2;
0684     struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
0685     struct device *dev = &pdev->dev;
0686     int ret;
0687
0688     master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
0689     if (!master)
0690         return -ENOMEM;
0691
0692     device_set_node(&master->dev, dev_fwnode(dev));
0693
0694     platform_set_drvdata(pdev, master);
0695
0696     dln2 = spi_master_get_devdata(master);
0697
0698     dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
0699     if (!dln2->buf) {
0700         ret = -ENOMEM;
0701         goto exit_free_master;
0702     }
0703
0704     dln2->master = master;
0705     dln2->pdev = pdev;
0706     dln2->port = pdata->port;
0707     /* cs/mode can never be 0xff, so the first transfer will set them */
0708     dln2->cs = 0xff;
0709     dln2->mode = 0xff;
0710
0711     /* disable SPI module before continuing with the setup */
0712     ret = dln2_spi_enable(dln2, false);
0713     if (ret < 0) {
0714         dev_err(&pdev->dev, "Failed to disable SPI module\n");
0715         goto exit_free_master;
0716     }
0717
0718     ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
0719     if (ret < 0) {
0720         dev_err(&pdev->dev, "Failed to get number of CS pins\n");
0721         goto exit_free_master;
0722     }
0723
0724     ret = dln2_spi_get_speed_range(dln2,
0725                        &master->min_speed_hz,
0726                        &master->max_speed_hz);
0727     if (ret < 0) {
0728         dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
0729         goto exit_free_master;
0730     }
0731
0732     ret = dln2_spi_get_supported_frame_sizes(dln2,
0733                          &master->bits_per_word_mask);
0734     if (ret < 0) {
0735         dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
0736         goto exit_free_master;
0737     }
0738
0739     ret = dln2_spi_cs_enable_all(dln2, true);
0740     if (ret < 0) {
0741         dev_err(&pdev->dev, "Failed to enable CS pins\n");
0742         goto exit_free_master;
0743     }
0744
0745     master->bus_num = -1;
0746     master->mode_bits = SPI_CPOL | SPI_CPHA;
0747     master->prepare_message = dln2_spi_prepare_message;
0748     master->transfer_one = dln2_spi_transfer_one;
0749     master->auto_runtime_pm = true;
0750
0751     /* enable SPI module, we're good to go */
0752     ret = dln2_spi_enable(dln2, true);
0753     if (ret < 0) {
0754         dev_err(&pdev->dev, "Failed to enable SPI module\n");
0755         goto exit_free_master;
0756     }
0757
0758     pm_runtime_set_autosuspend_delay(&pdev->dev,
0759                      DLN2_RPM_AUTOSUSPEND_TIMEOUT);
0760     pm_runtime_use_autosuspend(&pdev->dev);
0761     pm_runtime_set_active(&pdev->dev);
0762     pm_runtime_enable(&pdev->dev);
0763
0764     ret = devm_spi_register_master(&pdev->dev, master);
0765     if (ret < 0) {
0766         dev_err(&pdev->dev, "Failed to register master\n");
0767         goto exit_register;
0768     }
0769
0770     return ret;
0771
0772 exit_register:
0773     pm_runtime_disable(&pdev->dev);
0774     pm_runtime_set_suspended(&pdev->dev);
0775
0776     if (dln2_spi_enable(dln2, false) < 0)
0777         dev_err(&pdev->dev, "Failed to disable SPI module\n");
0778 exit_free_master:
0779     spi_master_put(master);
0780
0781     return ret;
0782 }
0783
0784 static int dln2_spi_remove(struct platform_device *pdev)
0785 {
0786     struct spi_master *master = platform_get_drvdata(pdev);
0787     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0788
0789     pm_runtime_disable(&pdev->dev);
0790
0791     if (dln2_spi_enable(dln2, false) < 0)
0792         dev_err(&pdev->dev, "Failed to disable SPI module\n");
0793
0794     return 0;
0795 }
0796
0797 #ifdef CONFIG_PM_SLEEP
0798 static int dln2_spi_suspend(struct device *dev)
0799 {
0800     int ret;
0801     struct spi_master *master = dev_get_drvdata(dev);
0802     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0803
0804     ret = spi_master_suspend(master);
0805     if (ret < 0)
0806         return ret;
0807
0808     if (!pm_runtime_suspended(dev)) {
0809         ret = dln2_spi_enable(dln2, false);
0810         if (ret < 0)
0811             return ret;
0812     }
0813
0814     /*
0815      * USB power may be cut off during sleep. Resetting the following
0816      * parameters will force the board to be set up before first transfer.
0817      */
0818     dln2->cs = 0xff;
0819     dln2->speed = 0;
0820     dln2->bpw = 0;
0821     dln2->mode = 0xff;
0822
0823     return 0;
0824 }
0825
0826 static int dln2_spi_resume(struct device *dev)
0827 {
0828     int ret;
0829     struct spi_master *master = dev_get_drvdata(dev);
0830     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0831
0832     if (!pm_runtime_suspended(dev)) {
0833         ret = dln2_spi_cs_enable_all(dln2, true);
0834         if (ret < 0)
0835             return ret;
0836
0837         ret = dln2_spi_enable(dln2, true);
0838         if (ret < 0)
0839             return ret;
0840     }
0841
0842     return spi_master_resume(master);
0843 }
0844 #endif /* CONFIG_PM_SLEEP */
0845
0846 #ifdef CONFIG_PM
0847 static int dln2_spi_runtime_suspend(struct device *dev)
0848 {
0849     struct spi_master *master = dev_get_drvdata(dev);
0850     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0851
0852     return dln2_spi_enable(dln2, false);
0853 }
0854
0855 static int dln2_spi_runtime_resume(struct device *dev)
0856 {
0857     struct spi_master *master = dev_get_drvdata(dev);
0858     struct dln2_spi *dln2 = spi_master_get_devdata(master);
0859
0860     return  dln2_spi_enable(dln2, true);
0861 }
0862 #endif /* CONFIG_PM */
0863
0864 static const struct dev_pm_ops dln2_spi_pm = {
0865     SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume)
0866     SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend,
0867                dln2_spi_runtime_resume, NULL)
0868 };
0869
0870 static struct platform_driver spi_dln2_driver = {
0871     .driver = {
0872         .name   = "dln2-spi",
0873         .pm = &dln2_spi_pm,
0874     },
0875     .probe      = dln2_spi_probe,
0876     .remove     = dln2_spi_remove,
0877 };
0878 module_platform_driver(spi_dln2_driver);
0879
0880 MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
0881 MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
0882 MODULE_LICENSE("GPL v2");
0883 MODULE_ALIAS("platform:dln2-spi");