drivers/spi/spi-coldfire-qspi.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale/Motorola Coldfire Queued SPI driver
0004  *
0005  * Copyright 2010 Steven King <sfking@fdwdc.com>
0006 */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/errno.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/sched.h>
0014 #include <linux/delay.h>
0015 #include <linux/io.h>
0016 #include <linux/clk.h>
0017 #include <linux/err.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/pm_runtime.h>
0020
0021 #include <asm/coldfire.h>
0022 #include <asm/mcfsim.h>
0023 #include <asm/mcfqspi.h>
0024
0025 #define DRIVER_NAME "mcfqspi"
0026
0027 #define MCFQSPI_BUSCLK          (MCF_BUSCLK / 2)
0028
0029 #define MCFQSPI_QMR         0x00
0030 #define     MCFQSPI_QMR_MSTR    0x8000
0031 #define     MCFQSPI_QMR_CPOL    0x0200
0032 #define     MCFQSPI_QMR_CPHA    0x0100
0033 #define MCFQSPI_QDLYR           0x04
0034 #define     MCFQSPI_QDLYR_SPE   0x8000
0035 #define MCFQSPI_QWR         0x08
0036 #define     MCFQSPI_QWR_HALT    0x8000
0037 #define     MCFQSPI_QWR_WREN    0x4000
0038 #define     MCFQSPI_QWR_CSIV    0x1000
0039 #define MCFQSPI_QIR         0x0C
0040 #define     MCFQSPI_QIR_WCEFB   0x8000
0041 #define     MCFQSPI_QIR_ABRTB   0x4000
0042 #define     MCFQSPI_QIR_ABRTL   0x1000
0043 #define     MCFQSPI_QIR_WCEFE   0x0800
0044 #define     MCFQSPI_QIR_ABRTE   0x0400
0045 #define     MCFQSPI_QIR_SPIFE   0x0100
0046 #define     MCFQSPI_QIR_WCEF    0x0008
0047 #define     MCFQSPI_QIR_ABRT    0x0004
0048 #define     MCFQSPI_QIR_SPIF    0x0001
0049 #define MCFQSPI_QAR         0x010
0050 #define     MCFQSPI_QAR_TXBUF   0x00
0051 #define     MCFQSPI_QAR_RXBUF   0x10
0052 #define     MCFQSPI_QAR_CMDBUF  0x20
0053 #define MCFQSPI_QDR         0x014
0054 #define MCFQSPI_QCR         0x014
0055 #define     MCFQSPI_QCR_CONT    0x8000
0056 #define     MCFQSPI_QCR_BITSE   0x4000
0057 #define     MCFQSPI_QCR_DT      0x2000
0058
0059 struct mcfqspi {
0060     void __iomem *iobase;
0061     int irq;
0062     struct clk *clk;
0063     struct mcfqspi_cs_control *cs_control;
0064
0065     wait_queue_head_t waitq;
0066 };
0067
0068 static void mcfqspi_wr_qmr(struct mcfqspi *mcfqspi, u16 val)
0069 {
0070     writew(val, mcfqspi->iobase + MCFQSPI_QMR);
0071 }
0072
0073 static void mcfqspi_wr_qdlyr(struct mcfqspi *mcfqspi, u16 val)
0074 {
0075     writew(val, mcfqspi->iobase + MCFQSPI_QDLYR);
0076 }
0077
0078 static u16 mcfqspi_rd_qdlyr(struct mcfqspi *mcfqspi)
0079 {
0080     return readw(mcfqspi->iobase + MCFQSPI_QDLYR);
0081 }
0082
0083 static void mcfqspi_wr_qwr(struct mcfqspi *mcfqspi, u16 val)
0084 {
0085     writew(val, mcfqspi->iobase + MCFQSPI_QWR);
0086 }
0087
0088 static void mcfqspi_wr_qir(struct mcfqspi *mcfqspi, u16 val)
0089 {
0090     writew(val, mcfqspi->iobase + MCFQSPI_QIR);
0091 }
0092
0093 static void mcfqspi_wr_qar(struct mcfqspi *mcfqspi, u16 val)
0094 {
0095     writew(val, mcfqspi->iobase + MCFQSPI_QAR);
0096 }
0097
0098 static void mcfqspi_wr_qdr(struct mcfqspi *mcfqspi, u16 val)
0099 {
0100     writew(val, mcfqspi->iobase + MCFQSPI_QDR);
0101 }
0102
0103 static u16 mcfqspi_rd_qdr(struct mcfqspi *mcfqspi)
0104 {
0105     return readw(mcfqspi->iobase + MCFQSPI_QDR);
0106 }
0107
0108 static void mcfqspi_cs_select(struct mcfqspi *mcfqspi, u8 chip_select,
0109                 bool cs_high)
0110 {
0111     mcfqspi->cs_control->select(mcfqspi->cs_control, chip_select, cs_high);
0112 }
0113
0114 static void mcfqspi_cs_deselect(struct mcfqspi *mcfqspi, u8 chip_select,
0115                 bool cs_high)
0116 {
0117     mcfqspi->cs_control->deselect(mcfqspi->cs_control, chip_select, cs_high);
0118 }
0119
0120 static int mcfqspi_cs_setup(struct mcfqspi *mcfqspi)
0121 {
0122     return (mcfqspi->cs_control->setup) ?
0123         mcfqspi->cs_control->setup(mcfqspi->cs_control) : 0;
0124 }
0125
0126 static void mcfqspi_cs_teardown(struct mcfqspi *mcfqspi)
0127 {
0128     if (mcfqspi->cs_control->teardown)
0129         mcfqspi->cs_control->teardown(mcfqspi->cs_control);
0130 }
0131
0132 static u8 mcfqspi_qmr_baud(u32 speed_hz)
0133 {
0134     return clamp((MCFQSPI_BUSCLK + speed_hz - 1) / speed_hz, 2u, 255u);
0135 }
0136
0137 static bool mcfqspi_qdlyr_spe(struct mcfqspi *mcfqspi)
0138 {
0139     return mcfqspi_rd_qdlyr(mcfqspi) & MCFQSPI_QDLYR_SPE;
0140 }
0141
0142 static irqreturn_t mcfqspi_irq_handler(int this_irq, void *dev_id)
0143 {
0144     struct mcfqspi *mcfqspi = dev_id;
0145
0146     /* clear interrupt */
0147     mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE | MCFQSPI_QIR_SPIF);
0148     wake_up(&mcfqspi->waitq);
0149
0150     return IRQ_HANDLED;
0151 }
0152
0153 static void mcfqspi_transfer_msg8(struct mcfqspi *mcfqspi, unsigned count,
0154                   const u8 *txbuf, u8 *rxbuf)
0155 {
0156     unsigned i, n, offset = 0;
0157
0158     n = min(count, 16u);
0159
0160     mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
0161     for (i = 0; i < n; ++i)
0162         mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
0163
0164     mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
0165     if (txbuf)
0166         for (i = 0; i < n; ++i)
0167             mcfqspi_wr_qdr(mcfqspi, *txbuf++);
0168     else
0169         for (i = 0; i < count; ++i)
0170             mcfqspi_wr_qdr(mcfqspi, 0);
0171
0172     count -= n;
0173     if (count) {
0174         u16 qwr = 0xf08;
0175         mcfqspi_wr_qwr(mcfqspi, 0x700);
0176         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0177
0178         do {
0179             wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
0180             mcfqspi_wr_qwr(mcfqspi, qwr);
0181             mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0182             if (rxbuf) {
0183                 mcfqspi_wr_qar(mcfqspi,
0184                            MCFQSPI_QAR_RXBUF + offset);
0185                 for (i = 0; i < 8; ++i)
0186                     *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
0187             }
0188             n = min(count, 8u);
0189             if (txbuf) {
0190                 mcfqspi_wr_qar(mcfqspi,
0191                            MCFQSPI_QAR_TXBUF + offset);
0192                 for (i = 0; i < n; ++i)
0193                     mcfqspi_wr_qdr(mcfqspi, *txbuf++);
0194             }
0195             qwr = (offset ? 0x808 : 0) + ((n - 1) << 8);
0196             offset ^= 8;
0197             count -= n;
0198         } while (count);
0199         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
0200         mcfqspi_wr_qwr(mcfqspi, qwr);
0201         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0202         if (rxbuf) {
0203             mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
0204             for (i = 0; i < 8; ++i)
0205                 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
0206             offset ^= 8;
0207         }
0208     } else {
0209         mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
0210         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0211     }
0212     wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
0213     if (rxbuf) {
0214         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
0215         for (i = 0; i < n; ++i)
0216             *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
0217     }
0218 }
0219
0220 static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
0221                    const u16 *txbuf, u16 *rxbuf)
0222 {
0223     unsigned i, n, offset = 0;
0224
0225     n = min(count, 16u);
0226
0227     mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_CMDBUF);
0228     for (i = 0; i < n; ++i)
0229         mcfqspi_wr_qdr(mcfqspi, MCFQSPI_QCR_BITSE);
0230
0231     mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_TXBUF);
0232     if (txbuf)
0233         for (i = 0; i < n; ++i)
0234             mcfqspi_wr_qdr(mcfqspi, *txbuf++);
0235     else
0236         for (i = 0; i < count; ++i)
0237             mcfqspi_wr_qdr(mcfqspi, 0);
0238
0239     count -= n;
0240     if (count) {
0241         u16 qwr = 0xf08;
0242         mcfqspi_wr_qwr(mcfqspi, 0x700);
0243         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0244
0245         do {
0246             wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
0247             mcfqspi_wr_qwr(mcfqspi, qwr);
0248             mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0249             if (rxbuf) {
0250                 mcfqspi_wr_qar(mcfqspi,
0251                            MCFQSPI_QAR_RXBUF + offset);
0252                 for (i = 0; i < 8; ++i)
0253                     *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
0254             }
0255             n = min(count, 8u);
0256             if (txbuf) {
0257                 mcfqspi_wr_qar(mcfqspi,
0258                            MCFQSPI_QAR_TXBUF + offset);
0259                 for (i = 0; i < n; ++i)
0260                     mcfqspi_wr_qdr(mcfqspi, *txbuf++);
0261             }
0262             qwr = (offset ? 0x808 : 0x000) + ((n - 1) << 8);
0263             offset ^= 8;
0264             count -= n;
0265         } while (count);
0266         wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
0267         mcfqspi_wr_qwr(mcfqspi, qwr);
0268         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0269         if (rxbuf) {
0270             mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
0271             for (i = 0; i < 8; ++i)
0272                 *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
0273             offset ^= 8;
0274         }
0275     } else {
0276         mcfqspi_wr_qwr(mcfqspi, (n - 1) << 8);
0277         mcfqspi_wr_qdlyr(mcfqspi, MCFQSPI_QDLYR_SPE);
0278     }
0279     wait_event(mcfqspi->waitq, !mcfqspi_qdlyr_spe(mcfqspi));
0280     if (rxbuf) {
0281         mcfqspi_wr_qar(mcfqspi, MCFQSPI_QAR_RXBUF + offset);
0282         for (i = 0; i < n; ++i)
0283             *rxbuf++ = mcfqspi_rd_qdr(mcfqspi);
0284     }
0285 }
0286
0287 static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
0288 {
0289     struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
0290     bool cs_high = spi->mode & SPI_CS_HIGH;
0291
0292     if (enable)
0293         mcfqspi_cs_select(mcfqspi, spi->chip_select, cs_high);
0294     else
0295         mcfqspi_cs_deselect(mcfqspi, spi->chip_select, cs_high);
0296 }
0297
0298 static int mcfqspi_transfer_one(struct spi_master *master,
0299                 struct spi_device *spi,
0300                 struct spi_transfer *t)
0301 {
0302     struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
0303     u16 qmr = MCFQSPI_QMR_MSTR;
0304
0305     qmr |= t->bits_per_word << 10;
0306     if (spi->mode & SPI_CPHA)
0307         qmr |= MCFQSPI_QMR_CPHA;
0308     if (spi->mode & SPI_CPOL)
0309         qmr |= MCFQSPI_QMR_CPOL;
0310     qmr |= mcfqspi_qmr_baud(t->speed_hz);
0311     mcfqspi_wr_qmr(mcfqspi, qmr);
0312
0313     mcfqspi_wr_qir(mcfqspi, MCFQSPI_QIR_SPIFE);
0314     if (t->bits_per_word == 8)
0315         mcfqspi_transfer_msg8(mcfqspi, t->len, t->tx_buf, t->rx_buf);
0316     else
0317         mcfqspi_transfer_msg16(mcfqspi, t->len / 2, t->tx_buf,
0318                        t->rx_buf);
0319     mcfqspi_wr_qir(mcfqspi, 0);
0320
0321     return 0;
0322 }
0323
0324 static int mcfqspi_setup(struct spi_device *spi)
0325 {
0326     mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
0327                 spi->chip_select, spi->mode & SPI_CS_HIGH);
0328
0329     dev_dbg(&spi->dev,
0330             "bits per word %d, chip select %d, speed %d KHz\n",
0331             spi->bits_per_word, spi->chip_select,
0332             (MCFQSPI_BUSCLK / mcfqspi_qmr_baud(spi->max_speed_hz))
0333             / 1000);
0334
0335     return 0;
0336 }
0337
0338 static int mcfqspi_probe(struct platform_device *pdev)
0339 {
0340     struct spi_master *master;
0341     struct mcfqspi *mcfqspi;
0342     struct mcfqspi_platform_data *pdata;
0343     int status;
0344
0345     pdata = dev_get_platdata(&pdev->dev);
0346     if (!pdata) {
0347         dev_dbg(&pdev->dev, "platform data is missing\n");
0348         return -ENOENT;
0349     }
0350
0351     if (!pdata->cs_control) {
0352         dev_dbg(&pdev->dev, "pdata->cs_control is NULL\n");
0353         return -EINVAL;
0354     }
0355
0356     master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
0357     if (master == NULL) {
0358         dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
0359         return -ENOMEM;
0360     }
0361
0362     mcfqspi = spi_master_get_devdata(master);
0363
0364     mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
0365     if (IS_ERR(mcfqspi->iobase)) {
0366         status = PTR_ERR(mcfqspi->iobase);
0367         goto fail0;
0368     }
0369
0370     mcfqspi->irq = platform_get_irq(pdev, 0);
0371     if (mcfqspi->irq < 0) {
0372         dev_dbg(&pdev->dev, "platform_get_irq failed\n");
0373         status = -ENXIO;
0374         goto fail0;
0375     }
0376
0377     status = devm_request_irq(&pdev->dev, mcfqspi->irq, mcfqspi_irq_handler,
0378                 0, pdev->name, mcfqspi);
0379     if (status) {
0380         dev_dbg(&pdev->dev, "request_irq failed\n");
0381         goto fail0;
0382     }
0383
0384     mcfqspi->clk = devm_clk_get(&pdev->dev, "qspi_clk");
0385     if (IS_ERR(mcfqspi->clk)) {
0386         dev_dbg(&pdev->dev, "clk_get failed\n");
0387         status = PTR_ERR(mcfqspi->clk);
0388         goto fail0;
0389     }
0390     clk_prepare_enable(mcfqspi->clk);
0391
0392     master->bus_num = pdata->bus_num;
0393     master->num_chipselect = pdata->num_chipselect;
0394
0395     mcfqspi->cs_control = pdata->cs_control;
0396     status = mcfqspi_cs_setup(mcfqspi);
0397     if (status) {
0398         dev_dbg(&pdev->dev, "error initializing cs_control\n");
0399         goto fail1;
0400     }
0401
0402     init_waitqueue_head(&mcfqspi->waitq);
0403
0404     master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
0405     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
0406     master->setup = mcfqspi_setup;
0407     master->set_cs = mcfqspi_set_cs;
0408     master->transfer_one = mcfqspi_transfer_one;
0409     master->auto_runtime_pm = true;
0410
0411     platform_set_drvdata(pdev, master);
0412     pm_runtime_enable(&pdev->dev);
0413
0414     status = devm_spi_register_master(&pdev->dev, master);
0415     if (status) {
0416         dev_dbg(&pdev->dev, "spi_register_master failed\n");
0417         goto fail2;
0418     }
0419
0420     dev_info(&pdev->dev, "Coldfire QSPI bus driver\n");
0421
0422     return 0;
0423
0424 fail2:
0425     pm_runtime_disable(&pdev->dev);
0426     mcfqspi_cs_teardown(mcfqspi);
0427 fail1:
0428     clk_disable_unprepare(mcfqspi->clk);
0429 fail0:
0430     spi_master_put(master);
0431
0432     dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
0433
0434     return status;
0435 }
0436
0437 static int mcfqspi_remove(struct platform_device *pdev)
0438 {
0439     struct spi_master *master = platform_get_drvdata(pdev);
0440     struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
0441
0442     pm_runtime_disable(&pdev->dev);
0443     /* disable the hardware (set the baud rate to 0) */
0444     mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
0445
0446     mcfqspi_cs_teardown(mcfqspi);
0447     clk_disable_unprepare(mcfqspi->clk);
0448
0449     return 0;
0450 }
0451
0452 #ifdef CONFIG_PM_SLEEP
0453 static int mcfqspi_suspend(struct device *dev)
0454 {
0455     struct spi_master *master = dev_get_drvdata(dev);
0456     struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
0457     int ret;
0458
0459     ret = spi_master_suspend(master);
0460     if (ret)
0461         return ret;
0462
0463     clk_disable(mcfqspi->clk);
0464
0465     return 0;
0466 }
0467
0468 static int mcfqspi_resume(struct device *dev)
0469 {
0470     struct spi_master *master = dev_get_drvdata(dev);
0471     struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
0472
0473     clk_enable(mcfqspi->clk);
0474
0475     return spi_master_resume(master);
0476 }
0477 #endif
0478
0479 #ifdef CONFIG_PM
0480 static int mcfqspi_runtime_suspend(struct device *dev)
0481 {
0482     struct spi_master *master = dev_get_drvdata(dev);
0483     struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
0484
0485     clk_disable(mcfqspi->clk);
0486
0487     return 0;
0488 }
0489
0490 static int mcfqspi_runtime_resume(struct device *dev)
0491 {
0492     struct spi_master *master = dev_get_drvdata(dev);
0493     struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
0494
0495     clk_enable(mcfqspi->clk);
0496
0497     return 0;
0498 }
0499 #endif
0500
0501 static const struct dev_pm_ops mcfqspi_pm = {
0502     SET_SYSTEM_SLEEP_PM_OPS(mcfqspi_suspend, mcfqspi_resume)
0503     SET_RUNTIME_PM_OPS(mcfqspi_runtime_suspend, mcfqspi_runtime_resume,
0504             NULL)
0505 };
0506
0507 static struct platform_driver mcfqspi_driver = {
0508     .driver.name    = DRIVER_NAME,
0509     .driver.owner   = THIS_MODULE,
0510     .driver.pm  = &mcfqspi_pm,
0511     .probe      = mcfqspi_probe,
0512     .remove     = mcfqspi_remove,
0513 };
0514 module_platform_driver(mcfqspi_driver);
0515
0516 MODULE_AUTHOR("Steven King <sfking@fdwdc.com>");
0517 MODULE_DESCRIPTION("Coldfire QSPI Controller Driver");
0518 MODULE_LICENSE("GPL");
0519 MODULE_ALIAS("platform:" DRIVER_NAME);