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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SPI_CAVIUM_H
0003 #define __SPI_CAVIUM_H
0004 
0005 #include <linux/clk.h>
0006 
0007 #define OCTEON_SPI_MAX_BYTES 9
0008 #define OCTEON_SPI_MAX_CLOCK_HZ 16000000
0009 
0010 struct octeon_spi_regs {
0011     int config;
0012     int status;
0013     int tx;
0014     int data;
0015 };
0016 
0017 struct octeon_spi {
0018     void __iomem *register_base;
0019     u64 last_cfg;
0020     u64 cs_enax;
0021     int sys_freq;
0022     struct octeon_spi_regs regs;
0023     struct clk *clk;
0024 };
0025 
0026 #define OCTEON_SPI_CFG(x)   (x->regs.config)
0027 #define OCTEON_SPI_STS(x)   (x->regs.status)
0028 #define OCTEON_SPI_TX(x)    (x->regs.tx)
0029 #define OCTEON_SPI_DAT0(x)  (x->regs.data)
0030 
0031 int octeon_spi_transfer_one_message(struct spi_master *master,
0032                     struct spi_message *msg);
0033 
0034 /* MPI register descriptions */
0035 
0036 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
0037 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
0038 #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
0039 #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
0040 
0041 union cvmx_mpi_cfg {
0042     uint64_t u64;
0043     struct cvmx_mpi_cfg_s {
0044 #ifdef __BIG_ENDIAN_BITFIELD
0045         uint64_t reserved_29_63:35;
0046         uint64_t clkdiv:13;
0047         uint64_t csena3:1;
0048         uint64_t csena2:1;
0049         uint64_t csena1:1;
0050         uint64_t csena0:1;
0051         uint64_t cslate:1;
0052         uint64_t tritx:1;
0053         uint64_t idleclks:2;
0054         uint64_t cshi:1;
0055         uint64_t csena:1;
0056         uint64_t int_ena:1;
0057         uint64_t lsbfirst:1;
0058         uint64_t wireor:1;
0059         uint64_t clk_cont:1;
0060         uint64_t idlelo:1;
0061         uint64_t enable:1;
0062 #else
0063         uint64_t enable:1;
0064         uint64_t idlelo:1;
0065         uint64_t clk_cont:1;
0066         uint64_t wireor:1;
0067         uint64_t lsbfirst:1;
0068         uint64_t int_ena:1;
0069         uint64_t csena:1;
0070         uint64_t cshi:1;
0071         uint64_t idleclks:2;
0072         uint64_t tritx:1;
0073         uint64_t cslate:1;
0074         uint64_t csena0:1;
0075         uint64_t csena1:1;
0076         uint64_t csena2:1;
0077         uint64_t csena3:1;
0078         uint64_t clkdiv:13;
0079         uint64_t reserved_29_63:35;
0080 #endif
0081     } s;
0082     struct cvmx_mpi_cfg_cn30xx {
0083 #ifdef __BIG_ENDIAN_BITFIELD
0084         uint64_t reserved_29_63:35;
0085         uint64_t clkdiv:13;
0086         uint64_t reserved_12_15:4;
0087         uint64_t cslate:1;
0088         uint64_t tritx:1;
0089         uint64_t idleclks:2;
0090         uint64_t cshi:1;
0091         uint64_t csena:1;
0092         uint64_t int_ena:1;
0093         uint64_t lsbfirst:1;
0094         uint64_t wireor:1;
0095         uint64_t clk_cont:1;
0096         uint64_t idlelo:1;
0097         uint64_t enable:1;
0098 #else
0099         uint64_t enable:1;
0100         uint64_t idlelo:1;
0101         uint64_t clk_cont:1;
0102         uint64_t wireor:1;
0103         uint64_t lsbfirst:1;
0104         uint64_t int_ena:1;
0105         uint64_t csena:1;
0106         uint64_t cshi:1;
0107         uint64_t idleclks:2;
0108         uint64_t tritx:1;
0109         uint64_t cslate:1;
0110         uint64_t reserved_12_15:4;
0111         uint64_t clkdiv:13;
0112         uint64_t reserved_29_63:35;
0113 #endif
0114     } cn30xx;
0115     struct cvmx_mpi_cfg_cn31xx {
0116 #ifdef __BIG_ENDIAN_BITFIELD
0117         uint64_t reserved_29_63:35;
0118         uint64_t clkdiv:13;
0119         uint64_t reserved_11_15:5;
0120         uint64_t tritx:1;
0121         uint64_t idleclks:2;
0122         uint64_t cshi:1;
0123         uint64_t csena:1;
0124         uint64_t int_ena:1;
0125         uint64_t lsbfirst:1;
0126         uint64_t wireor:1;
0127         uint64_t clk_cont:1;
0128         uint64_t idlelo:1;
0129         uint64_t enable:1;
0130 #else
0131         uint64_t enable:1;
0132         uint64_t idlelo:1;
0133         uint64_t clk_cont:1;
0134         uint64_t wireor:1;
0135         uint64_t lsbfirst:1;
0136         uint64_t int_ena:1;
0137         uint64_t csena:1;
0138         uint64_t cshi:1;
0139         uint64_t idleclks:2;
0140         uint64_t tritx:1;
0141         uint64_t reserved_11_15:5;
0142         uint64_t clkdiv:13;
0143         uint64_t reserved_29_63:35;
0144 #endif
0145     } cn31xx;
0146     struct cvmx_mpi_cfg_cn30xx cn50xx;
0147     struct cvmx_mpi_cfg_cn61xx {
0148 #ifdef __BIG_ENDIAN_BITFIELD
0149         uint64_t reserved_29_63:35;
0150         uint64_t clkdiv:13;
0151         uint64_t reserved_14_15:2;
0152         uint64_t csena1:1;
0153         uint64_t csena0:1;
0154         uint64_t cslate:1;
0155         uint64_t tritx:1;
0156         uint64_t idleclks:2;
0157         uint64_t cshi:1;
0158         uint64_t reserved_6_6:1;
0159         uint64_t int_ena:1;
0160         uint64_t lsbfirst:1;
0161         uint64_t wireor:1;
0162         uint64_t clk_cont:1;
0163         uint64_t idlelo:1;
0164         uint64_t enable:1;
0165 #else
0166         uint64_t enable:1;
0167         uint64_t idlelo:1;
0168         uint64_t clk_cont:1;
0169         uint64_t wireor:1;
0170         uint64_t lsbfirst:1;
0171         uint64_t int_ena:1;
0172         uint64_t reserved_6_6:1;
0173         uint64_t cshi:1;
0174         uint64_t idleclks:2;
0175         uint64_t tritx:1;
0176         uint64_t cslate:1;
0177         uint64_t csena0:1;
0178         uint64_t csena1:1;
0179         uint64_t reserved_14_15:2;
0180         uint64_t clkdiv:13;
0181         uint64_t reserved_29_63:35;
0182 #endif
0183     } cn61xx;
0184     struct cvmx_mpi_cfg_cn66xx {
0185 #ifdef __BIG_ENDIAN_BITFIELD
0186         uint64_t reserved_29_63:35;
0187         uint64_t clkdiv:13;
0188         uint64_t csena3:1;
0189         uint64_t csena2:1;
0190         uint64_t reserved_12_13:2;
0191         uint64_t cslate:1;
0192         uint64_t tritx:1;
0193         uint64_t idleclks:2;
0194         uint64_t cshi:1;
0195         uint64_t reserved_6_6:1;
0196         uint64_t int_ena:1;
0197         uint64_t lsbfirst:1;
0198         uint64_t wireor:1;
0199         uint64_t clk_cont:1;
0200         uint64_t idlelo:1;
0201         uint64_t enable:1;
0202 #else
0203         uint64_t enable:1;
0204         uint64_t idlelo:1;
0205         uint64_t clk_cont:1;
0206         uint64_t wireor:1;
0207         uint64_t lsbfirst:1;
0208         uint64_t int_ena:1;
0209         uint64_t reserved_6_6:1;
0210         uint64_t cshi:1;
0211         uint64_t idleclks:2;
0212         uint64_t tritx:1;
0213         uint64_t cslate:1;
0214         uint64_t reserved_12_13:2;
0215         uint64_t csena2:1;
0216         uint64_t csena3:1;
0217         uint64_t clkdiv:13;
0218         uint64_t reserved_29_63:35;
0219 #endif
0220     } cn66xx;
0221     struct cvmx_mpi_cfg_cn61xx cnf71xx;
0222 };
0223 
0224 union cvmx_mpi_datx {
0225     uint64_t u64;
0226     struct cvmx_mpi_datx_s {
0227 #ifdef __BIG_ENDIAN_BITFIELD
0228         uint64_t reserved_8_63:56;
0229         uint64_t data:8;
0230 #else
0231         uint64_t data:8;
0232         uint64_t reserved_8_63:56;
0233 #endif
0234     } s;
0235     struct cvmx_mpi_datx_s cn30xx;
0236     struct cvmx_mpi_datx_s cn31xx;
0237     struct cvmx_mpi_datx_s cn50xx;
0238     struct cvmx_mpi_datx_s cn61xx;
0239     struct cvmx_mpi_datx_s cn66xx;
0240     struct cvmx_mpi_datx_s cnf71xx;
0241 };
0242 
0243 union cvmx_mpi_sts {
0244     uint64_t u64;
0245     struct cvmx_mpi_sts_s {
0246 #ifdef __BIG_ENDIAN_BITFIELD
0247         uint64_t reserved_13_63:51;
0248         uint64_t rxnum:5;
0249         uint64_t reserved_1_7:7;
0250         uint64_t busy:1;
0251 #else
0252         uint64_t busy:1;
0253         uint64_t reserved_1_7:7;
0254         uint64_t rxnum:5;
0255         uint64_t reserved_13_63:51;
0256 #endif
0257     } s;
0258     struct cvmx_mpi_sts_s cn30xx;
0259     struct cvmx_mpi_sts_s cn31xx;
0260     struct cvmx_mpi_sts_s cn50xx;
0261     struct cvmx_mpi_sts_s cn61xx;
0262     struct cvmx_mpi_sts_s cn66xx;
0263     struct cvmx_mpi_sts_s cnf71xx;
0264 };
0265 
0266 union cvmx_mpi_tx {
0267     uint64_t u64;
0268     struct cvmx_mpi_tx_s {
0269 #ifdef __BIG_ENDIAN_BITFIELD
0270         uint64_t reserved_22_63:42;
0271         uint64_t csid:2;
0272         uint64_t reserved_17_19:3;
0273         uint64_t leavecs:1;
0274         uint64_t reserved_13_15:3;
0275         uint64_t txnum:5;
0276         uint64_t reserved_5_7:3;
0277         uint64_t totnum:5;
0278 #else
0279         uint64_t totnum:5;
0280         uint64_t reserved_5_7:3;
0281         uint64_t txnum:5;
0282         uint64_t reserved_13_15:3;
0283         uint64_t leavecs:1;
0284         uint64_t reserved_17_19:3;
0285         uint64_t csid:2;
0286         uint64_t reserved_22_63:42;
0287 #endif
0288     } s;
0289     struct cvmx_mpi_tx_cn30xx {
0290 #ifdef __BIG_ENDIAN_BITFIELD
0291         uint64_t reserved_17_63:47;
0292         uint64_t leavecs:1;
0293         uint64_t reserved_13_15:3;
0294         uint64_t txnum:5;
0295         uint64_t reserved_5_7:3;
0296         uint64_t totnum:5;
0297 #else
0298         uint64_t totnum:5;
0299         uint64_t reserved_5_7:3;
0300         uint64_t txnum:5;
0301         uint64_t reserved_13_15:3;
0302         uint64_t leavecs:1;
0303         uint64_t reserved_17_63:47;
0304 #endif
0305     } cn30xx;
0306     struct cvmx_mpi_tx_cn30xx cn31xx;
0307     struct cvmx_mpi_tx_cn30xx cn50xx;
0308     struct cvmx_mpi_tx_cn61xx {
0309 #ifdef __BIG_ENDIAN_BITFIELD
0310         uint64_t reserved_21_63:43;
0311         uint64_t csid:1;
0312         uint64_t reserved_17_19:3;
0313         uint64_t leavecs:1;
0314         uint64_t reserved_13_15:3;
0315         uint64_t txnum:5;
0316         uint64_t reserved_5_7:3;
0317         uint64_t totnum:5;
0318 #else
0319         uint64_t totnum:5;
0320         uint64_t reserved_5_7:3;
0321         uint64_t txnum:5;
0322         uint64_t reserved_13_15:3;
0323         uint64_t leavecs:1;
0324         uint64_t reserved_17_19:3;
0325         uint64_t csid:1;
0326         uint64_t reserved_21_63:43;
0327 #endif
0328     } cn61xx;
0329     struct cvmx_mpi_tx_s cn66xx;
0330     struct cvmx_mpi_tx_cn61xx cnf71xx;
0331 };
0332 
0333 #endif /* __SPI_CAVIUM_H */
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