drivers/spi/spi-cavium.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Copyright (C) 2011, 2012 Cavium, Inc.
0007  */
0008
0009 #include <linux/spi/spi.h>
0010 #include <linux/module.h>
0011 #include <linux/delay.h>
0012 #include <linux/io.h>
0013
0014 #include "spi-cavium.h"
0015
0016 static void octeon_spi_wait_ready(struct octeon_spi *p)
0017 {
0018     union cvmx_mpi_sts mpi_sts;
0019     unsigned int loops = 0;
0020
0021     do {
0022         if (loops++)
0023             __delay(500);
0024         mpi_sts.u64 = readq(p->register_base + OCTEON_SPI_STS(p));
0025     } while (mpi_sts.s.busy);
0026 }
0027
0028 static int octeon_spi_do_transfer(struct octeon_spi *p,
0029                   struct spi_message *msg,
0030                   struct spi_transfer *xfer,
0031                   bool last_xfer)
0032 {
0033     struct spi_device *spi = msg->spi;
0034     union cvmx_mpi_cfg mpi_cfg;
0035     union cvmx_mpi_tx mpi_tx;
0036     unsigned int clkdiv;
0037     int mode;
0038     bool cpha, cpol;
0039     const u8 *tx_buf;
0040     u8 *rx_buf;
0041     int len;
0042     int i;
0043
0044     mode = spi->mode;
0045     cpha = mode & SPI_CPHA;
0046     cpol = mode & SPI_CPOL;
0047
0048     clkdiv = p->sys_freq / (2 * xfer->speed_hz);
0049
0050     mpi_cfg.u64 = 0;
0051
0052     mpi_cfg.s.clkdiv = clkdiv;
0053     mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
0054     mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
0055     mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
0056     mpi_cfg.s.idlelo = cpha != cpol;
0057     mpi_cfg.s.cslate = cpha ? 1 : 0;
0058     mpi_cfg.s.enable = 1;
0059
0060     if (spi->chip_select < 4)
0061         p->cs_enax |= 1ull << (12 + spi->chip_select);
0062     mpi_cfg.u64 |= p->cs_enax;
0063
0064     if (mpi_cfg.u64 != p->last_cfg) {
0065         p->last_cfg = mpi_cfg.u64;
0066         writeq(mpi_cfg.u64, p->register_base + OCTEON_SPI_CFG(p));
0067     }
0068     tx_buf = xfer->tx_buf;
0069     rx_buf = xfer->rx_buf;
0070     len = xfer->len;
0071     while (len > OCTEON_SPI_MAX_BYTES) {
0072         for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
0073             u8 d;
0074             if (tx_buf)
0075                 d = *tx_buf++;
0076             else
0077                 d = 0;
0078             writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
0079         }
0080         mpi_tx.u64 = 0;
0081         mpi_tx.s.csid = spi->chip_select;
0082         mpi_tx.s.leavecs = 1;
0083         mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
0084         mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
0085         writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
0086
0087         octeon_spi_wait_ready(p);
0088         if (rx_buf)
0089             for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
0090                 u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
0091                 *rx_buf++ = (u8)v;
0092             }
0093         len -= OCTEON_SPI_MAX_BYTES;
0094     }
0095
0096     for (i = 0; i < len; i++) {
0097         u8 d;
0098         if (tx_buf)
0099             d = *tx_buf++;
0100         else
0101             d = 0;
0102         writeq(d, p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
0103     }
0104
0105     mpi_tx.u64 = 0;
0106     mpi_tx.s.csid = spi->chip_select;
0107     if (last_xfer)
0108         mpi_tx.s.leavecs = xfer->cs_change;
0109     else
0110         mpi_tx.s.leavecs = !xfer->cs_change;
0111     mpi_tx.s.txnum = tx_buf ? len : 0;
0112     mpi_tx.s.totnum = len;
0113     writeq(mpi_tx.u64, p->register_base + OCTEON_SPI_TX(p));
0114
0115     octeon_spi_wait_ready(p);
0116     if (rx_buf)
0117         for (i = 0; i < len; i++) {
0118             u64 v = readq(p->register_base + OCTEON_SPI_DAT0(p) + (8 * i));
0119             *rx_buf++ = (u8)v;
0120         }
0121
0122     spi_transfer_delay_exec(xfer);
0123
0124     return xfer->len;
0125 }
0126
0127 int octeon_spi_transfer_one_message(struct spi_master *master,
0128                     struct spi_message *msg)
0129 {
0130     struct octeon_spi *p = spi_master_get_devdata(master);
0131     unsigned int total_len = 0;
0132     int status = 0;
0133     struct spi_transfer *xfer;
0134
0135     list_for_each_entry(xfer, &msg->transfers, transfer_list) {
0136         bool last_xfer = list_is_last(&xfer->transfer_list,
0137                           &msg->transfers);
0138         int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
0139         if (r < 0) {
0140             status = r;
0141             goto err;
0142         }
0143         total_len += r;
0144     }
0145 err:
0146     msg->status = status;
0147     msg->actual_length = total_len;
0148     spi_finalize_current_message(master);
0149     return status;
0150 }