drivers/spi/spi-cavium-thunderx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Cavium ThunderX SPI driver.
0004  *
0005  * Copyright (C) 2016 Cavium Inc.
0006  * Authors: Jan Glauber <jglauber@cavium.com>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/pci.h>
0011 #include <linux/spi/spi.h>
0012
0013 #include "spi-cavium.h"
0014
0015 #define DRV_NAME "spi-thunderx"
0016
0017 #define SYS_FREQ_DEFAULT 700000000 /* 700 Mhz */
0018
0019 static int thunderx_spi_probe(struct pci_dev *pdev,
0020                   const struct pci_device_id *ent)
0021 {
0022     struct device *dev = &pdev->dev;
0023     struct spi_master *master;
0024     struct octeon_spi *p;
0025     int ret;
0026
0027     master = spi_alloc_master(dev, sizeof(struct octeon_spi));
0028     if (!master)
0029         return -ENOMEM;
0030
0031     p = spi_master_get_devdata(master);
0032
0033     ret = pcim_enable_device(pdev);
0034     if (ret)
0035         goto error;
0036
0037     ret = pci_request_regions(pdev, DRV_NAME);
0038     if (ret)
0039         goto error;
0040
0041     p->register_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));
0042     if (!p->register_base) {
0043         ret = -EINVAL;
0044         goto error;
0045     }
0046
0047     p->regs.config = 0x1000;
0048     p->regs.status = 0x1008;
0049     p->regs.tx = 0x1010;
0050     p->regs.data = 0x1080;
0051
0052     p->clk = devm_clk_get(dev, NULL);
0053     if (IS_ERR(p->clk)) {
0054         ret = PTR_ERR(p->clk);
0055         goto error;
0056     }
0057
0058     ret = clk_prepare_enable(p->clk);
0059     if (ret)
0060         goto error;
0061
0062     p->sys_freq = clk_get_rate(p->clk);
0063     if (!p->sys_freq)
0064         p->sys_freq = SYS_FREQ_DEFAULT;
0065     dev_info(dev, "Set system clock to %u\n", p->sys_freq);
0066
0067     master->flags = SPI_MASTER_HALF_DUPLEX;
0068     master->num_chipselect = 4;
0069     master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
0070                 SPI_LSB_FIRST | SPI_3WIRE;
0071     master->transfer_one_message = octeon_spi_transfer_one_message;
0072     master->bits_per_word_mask = SPI_BPW_MASK(8);
0073     master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
0074     master->dev.of_node = pdev->dev.of_node;
0075
0076     pci_set_drvdata(pdev, master);
0077
0078     ret = devm_spi_register_master(dev, master);
0079     if (ret)
0080         goto error;
0081
0082     return 0;
0083
0084 error:
0085     clk_disable_unprepare(p->clk);
0086     pci_release_regions(pdev);
0087     spi_master_put(master);
0088     return ret;
0089 }
0090
0091 static void thunderx_spi_remove(struct pci_dev *pdev)
0092 {
0093     struct spi_master *master = pci_get_drvdata(pdev);
0094     struct octeon_spi *p;
0095
0096     p = spi_master_get_devdata(master);
0097     if (!p)
0098         return;
0099
0100     clk_disable_unprepare(p->clk);
0101     pci_release_regions(pdev);
0102     /* Put everything in a known state. */
0103     writeq(0, p->register_base + OCTEON_SPI_CFG(p));
0104 }
0105
0106 static const struct pci_device_id thunderx_spi_pci_id_table[] = {
0107     { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xa00b) },
0108     { 0, }
0109 };
0110
0111 MODULE_DEVICE_TABLE(pci, thunderx_spi_pci_id_table);
0112
0113 static struct pci_driver thunderx_spi_driver = {
0114     .name       = DRV_NAME,
0115     .id_table   = thunderx_spi_pci_id_table,
0116     .probe      = thunderx_spi_probe,
0117     .remove     = thunderx_spi_remove,
0118 };
0119
0120 module_pci_driver(thunderx_spi_driver);
0121
0122 MODULE_DESCRIPTION("Cavium, Inc. ThunderX SPI bus driver");
0123 MODULE_AUTHOR("Jan Glauber");
0124 MODULE_LICENSE("GPL");