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0001 // SPDX-License-Identifier: GPL-2.0+
0002 // Cadence XSPI flash controller driver
0003 // Copyright (C) 2020-21 Cadence
0004 
0005 #include <linux/completion.h>
0006 #include <linux/delay.h>
0007 #include <linux/err.h>
0008 #include <linux/errno.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/spi/spi.h>
0019 #include <linux/spi/spi-mem.h>
0020 #include <linux/bitfield.h>
0021 #include <linux/limits.h>
0022 #include <linux/log2.h>
0023 
0024 #define CDNS_XSPI_MAGIC_NUM_VALUE   0x6522
0025 #define CDNS_XSPI_MAX_BANKS     8
0026 #define CDNS_XSPI_NAME          "cadence-xspi"
0027 
0028 /*
0029  * Note: below are additional auxiliary registers to
0030  * configure XSPI controller pin-strap settings
0031  */
0032 
0033 /* PHY DQ timing register */
0034 #define CDNS_XSPI_CCP_PHY_DQ_TIMING     0x0000
0035 
0036 /* PHY DQS timing register */
0037 #define CDNS_XSPI_CCP_PHY_DQS_TIMING        0x0004
0038 
0039 /* PHY gate loopback control register */
0040 #define CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL   0x0008
0041 
0042 /* PHY DLL slave control register */
0043 #define CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL    0x0010
0044 
0045 /* DLL PHY control register */
0046 #define CDNS_XSPI_DLL_PHY_CTRL          0x1034
0047 
0048 /* Command registers */
0049 #define CDNS_XSPI_CMD_REG_0         0x0000
0050 #define CDNS_XSPI_CMD_REG_1         0x0004
0051 #define CDNS_XSPI_CMD_REG_2         0x0008
0052 #define CDNS_XSPI_CMD_REG_3         0x000C
0053 #define CDNS_XSPI_CMD_REG_4         0x0010
0054 #define CDNS_XSPI_CMD_REG_5         0x0014
0055 
0056 /* Command status registers */
0057 #define CDNS_XSPI_CMD_STATUS_REG        0x0044
0058 
0059 /* Controller status register */
0060 #define CDNS_XSPI_CTRL_STATUS_REG       0x0100
0061 #define CDNS_XSPI_INIT_COMPLETED        BIT(16)
0062 #define CDNS_XSPI_INIT_LEGACY           BIT(9)
0063 #define CDNS_XSPI_INIT_FAIL         BIT(8)
0064 #define CDNS_XSPI_CTRL_BUSY         BIT(7)
0065 
0066 /* Controller interrupt status register */
0067 #define CDNS_XSPI_INTR_STATUS_REG       0x0110
0068 #define CDNS_XSPI_STIG_DONE         BIT(23)
0069 #define CDNS_XSPI_SDMA_ERROR            BIT(22)
0070 #define CDNS_XSPI_SDMA_TRIGGER          BIT(21)
0071 #define CDNS_XSPI_CMD_IGNRD_EN          BIT(20)
0072 #define CDNS_XSPI_DDMA_TERR_EN          BIT(18)
0073 #define CDNS_XSPI_CDMA_TREE_EN          BIT(17)
0074 #define CDNS_XSPI_CTRL_IDLE_EN          BIT(16)
0075 
0076 #define CDNS_XSPI_TRD_COMP_INTR_STATUS      0x0120
0077 #define CDNS_XSPI_TRD_ERR_INTR_STATUS       0x0130
0078 #define CDNS_XSPI_TRD_ERR_INTR_EN       0x0134
0079 
0080 /* Controller interrupt enable register */
0081 #define CDNS_XSPI_INTR_ENABLE_REG       0x0114
0082 #define CDNS_XSPI_INTR_EN           BIT(31)
0083 #define CDNS_XSPI_STIG_DONE_EN          BIT(23)
0084 #define CDNS_XSPI_SDMA_ERROR_EN         BIT(22)
0085 #define CDNS_XSPI_SDMA_TRIGGER_EN       BIT(21)
0086 
0087 #define CDNS_XSPI_INTR_MASK (CDNS_XSPI_INTR_EN | \
0088     CDNS_XSPI_STIG_DONE_EN  | \
0089     CDNS_XSPI_SDMA_ERROR_EN | \
0090     CDNS_XSPI_SDMA_TRIGGER_EN)
0091 
0092 /* Controller config register */
0093 #define CDNS_XSPI_CTRL_CONFIG_REG       0x0230
0094 #define CDNS_XSPI_CTRL_WORK_MODE        GENMASK(6, 5)
0095 
0096 #define CDNS_XSPI_WORK_MODE_DIRECT      0
0097 #define CDNS_XSPI_WORK_MODE_STIG        1
0098 #define CDNS_XSPI_WORK_MODE_ACMD        3
0099 
0100 /* SDMA trigger transaction registers */
0101 #define CDNS_XSPI_SDMA_SIZE_REG         0x0240
0102 #define CDNS_XSPI_SDMA_TRD_INFO_REG     0x0244
0103 #define CDNS_XSPI_SDMA_DIR          BIT(8)
0104 
0105 /* Controller features register */
0106 #define CDNS_XSPI_CTRL_FEATURES_REG     0x0F04
0107 #define CDNS_XSPI_NUM_BANKS         GENMASK(25, 24)
0108 #define CDNS_XSPI_DMA_DATA_WIDTH        BIT(21)
0109 #define CDNS_XSPI_NUM_THREADS           GENMASK(3, 0)
0110 
0111 /* Controller version register */
0112 #define CDNS_XSPI_CTRL_VERSION_REG      0x0F00
0113 #define CDNS_XSPI_MAGIC_NUM         GENMASK(31, 16)
0114 #define CDNS_XSPI_CTRL_REV          GENMASK(7, 0)
0115 
0116 /* STIG Profile 1.0 instruction fields (split into registers) */
0117 #define CDNS_XSPI_CMD_INSTR_TYPE        GENMASK(6, 0)
0118 #define CDNS_XSPI_CMD_P1_R1_ADDR0       GENMASK(31, 24)
0119 #define CDNS_XSPI_CMD_P1_R2_ADDR1       GENMASK(7, 0)
0120 #define CDNS_XSPI_CMD_P1_R2_ADDR2       GENMASK(15, 8)
0121 #define CDNS_XSPI_CMD_P1_R2_ADDR3       GENMASK(23, 16)
0122 #define CDNS_XSPI_CMD_P1_R2_ADDR4       GENMASK(31, 24)
0123 #define CDNS_XSPI_CMD_P1_R3_ADDR5       GENMASK(7, 0)
0124 #define CDNS_XSPI_CMD_P1_R3_CMD         GENMASK(23, 16)
0125 #define CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES  GENMASK(30, 28)
0126 #define CDNS_XSPI_CMD_P1_R4_ADDR_IOS        GENMASK(1, 0)
0127 #define CDNS_XSPI_CMD_P1_R4_CMD_IOS     GENMASK(9, 8)
0128 #define CDNS_XSPI_CMD_P1_R4_BANK        GENMASK(14, 12)
0129 
0130 /* STIG data sequence instruction fields (split into registers) */
0131 #define CDNS_XSPI_CMD_DSEQ_R2_DCNT_L        GENMASK(31, 16)
0132 #define CDNS_XSPI_CMD_DSEQ_R3_DCNT_H        GENMASK(15, 0)
0133 #define CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY  GENMASK(25, 20)
0134 #define CDNS_XSPI_CMD_DSEQ_R4_BANK      GENMASK(14, 12)
0135 #define CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS      GENMASK(9, 8)
0136 #define CDNS_XSPI_CMD_DSEQ_R4_DIR       BIT(4)
0137 
0138 /* STIG command status fields */
0139 #define CDNS_XSPI_CMD_STATUS_COMPLETED      BIT(15)
0140 #define CDNS_XSPI_CMD_STATUS_FAILED     BIT(14)
0141 #define CDNS_XSPI_CMD_STATUS_DQS_ERROR      BIT(3)
0142 #define CDNS_XSPI_CMD_STATUS_CRC_ERROR      BIT(2)
0143 #define CDNS_XSPI_CMD_STATUS_BUS_ERROR      BIT(1)
0144 #define CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR  BIT(0)
0145 
0146 #define CDNS_XSPI_STIG_DONE_FLAG        BIT(0)
0147 #define CDNS_XSPI_TRD_STATUS            0x0104
0148 
0149 /* Helper macros for filling command registers */
0150 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase) ( \
0151     FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, (data_phase) ? \
0152         CDNS_XSPI_STIG_INSTR_TYPE_1 : CDNS_XSPI_STIG_INSTR_TYPE_0) | \
0153     FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
0154 
0155 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op) ( \
0156     FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8)  & 0xFF) | \
0157     FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR2, ((op)->addr.val >> 16) & 0xFF) | \
0158     FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR3, ((op)->addr.val >> 24) & 0xFF) | \
0159     FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR4, ((op)->addr.val >> 32) & 0xFF))
0160 
0161 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op) ( \
0162     FIELD_PREP(CDNS_XSPI_CMD_P1_R3_ADDR5, ((op)->addr.val >> 40) & 0xFF) | \
0163     FIELD_PREP(CDNS_XSPI_CMD_P1_R3_CMD, (op)->cmd.opcode) | \
0164     FIELD_PREP(CDNS_XSPI_CMD_P1_R3_NUM_ADDR_BYTES, (op)->addr.nbytes))
0165 
0166 #define CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op, chipsel) ( \
0167     FIELD_PREP(CDNS_XSPI_CMD_P1_R4_ADDR_IOS, ilog2((op)->addr.buswidth)) | \
0168     FIELD_PREP(CDNS_XSPI_CMD_P1_R4_CMD_IOS, ilog2((op)->cmd.buswidth)) | \
0169     FIELD_PREP(CDNS_XSPI_CMD_P1_R4_BANK, chipsel))
0170 
0171 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op) \
0172     FIELD_PREP(CDNS_XSPI_CMD_INSTR_TYPE, CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ)
0173 
0174 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op) \
0175     FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R2_DCNT_L, (op)->data.nbytes & 0xFFFF)
0176 
0177 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \
0178     FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \
0179         ((op)->data.nbytes >> 16) & 0xffff) | \
0180     FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, (op)->dummy.nbytes * 8))
0181 
0182 #define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \
0183     FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \
0184     FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DATA_IOS, \
0185         ilog2((op)->data.buswidth)) | \
0186     FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_DIR, \
0187         ((op)->data.dir == SPI_MEM_DATA_IN) ? \
0188         CDNS_XSPI_STIG_CMD_DIR_READ : CDNS_XSPI_STIG_CMD_DIR_WRITE))
0189 
0190 enum cdns_xspi_stig_instr_type {
0191     CDNS_XSPI_STIG_INSTR_TYPE_0,
0192     CDNS_XSPI_STIG_INSTR_TYPE_1,
0193     CDNS_XSPI_STIG_INSTR_TYPE_DATA_SEQ = 127,
0194 };
0195 
0196 enum cdns_xspi_sdma_dir {
0197     CDNS_XSPI_SDMA_DIR_READ,
0198     CDNS_XSPI_SDMA_DIR_WRITE,
0199 };
0200 
0201 enum cdns_xspi_stig_cmd_dir {
0202     CDNS_XSPI_STIG_CMD_DIR_READ,
0203     CDNS_XSPI_STIG_CMD_DIR_WRITE,
0204 };
0205 
0206 struct cdns_xspi_dev {
0207     struct platform_device *pdev;
0208     struct device *dev;
0209 
0210     void __iomem *iobase;
0211     void __iomem *auxbase;
0212     void __iomem *sdmabase;
0213 
0214     int irq;
0215     int cur_cs;
0216     unsigned int sdmasize;
0217 
0218     struct completion cmd_complete;
0219     struct completion auto_cmd_complete;
0220     struct completion sdma_complete;
0221     bool sdma_error;
0222 
0223     void *in_buffer;
0224     const void *out_buffer;
0225 
0226     u8 hw_num_banks;
0227 };
0228 
0229 static int cdns_xspi_wait_for_controller_idle(struct cdns_xspi_dev *cdns_xspi)
0230 {
0231     u32 ctrl_stat;
0232 
0233     return readl_relaxed_poll_timeout(cdns_xspi->iobase +
0234                       CDNS_XSPI_CTRL_STATUS_REG,
0235                       ctrl_stat,
0236                       ((ctrl_stat &
0237                         CDNS_XSPI_CTRL_BUSY) == 0),
0238                       100, 1000);
0239 }
0240 
0241 static void cdns_xspi_trigger_command(struct cdns_xspi_dev *cdns_xspi,
0242                       u32 cmd_regs[6])
0243 {
0244     writel(cmd_regs[5], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_5);
0245     writel(cmd_regs[4], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_4);
0246     writel(cmd_regs[3], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_3);
0247     writel(cmd_regs[2], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_2);
0248     writel(cmd_regs[1], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_1);
0249     writel(cmd_regs[0], cdns_xspi->iobase + CDNS_XSPI_CMD_REG_0);
0250 }
0251 
0252 static int cdns_xspi_check_command_status(struct cdns_xspi_dev *cdns_xspi)
0253 {
0254     int ret = 0;
0255     u32 cmd_status = readl(cdns_xspi->iobase + CDNS_XSPI_CMD_STATUS_REG);
0256 
0257     if (cmd_status & CDNS_XSPI_CMD_STATUS_COMPLETED) {
0258         if ((cmd_status & CDNS_XSPI_CMD_STATUS_FAILED) != 0) {
0259             if (cmd_status & CDNS_XSPI_CMD_STATUS_DQS_ERROR) {
0260                 dev_err(cdns_xspi->dev,
0261                     "Incorrect DQS pulses detected\n");
0262                 ret = -EPROTO;
0263             }
0264             if (cmd_status & CDNS_XSPI_CMD_STATUS_CRC_ERROR) {
0265                 dev_err(cdns_xspi->dev,
0266                     "CRC error received\n");
0267                 ret = -EPROTO;
0268             }
0269             if (cmd_status & CDNS_XSPI_CMD_STATUS_BUS_ERROR) {
0270                 dev_err(cdns_xspi->dev,
0271                     "Error resp on system DMA interface\n");
0272                 ret = -EPROTO;
0273             }
0274             if (cmd_status & CDNS_XSPI_CMD_STATUS_INV_SEQ_ERROR) {
0275                 dev_err(cdns_xspi->dev,
0276                     "Invalid command sequence detected\n");
0277                 ret = -EPROTO;
0278             }
0279         }
0280     } else {
0281         dev_err(cdns_xspi->dev, "Fatal err - command not completed\n");
0282         ret = -EPROTO;
0283     }
0284 
0285     return ret;
0286 }
0287 
0288 static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
0289                      bool enabled)
0290 {
0291     u32 intr_enable;
0292 
0293     intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
0294     if (enabled)
0295         intr_enable |= CDNS_XSPI_INTR_MASK;
0296     else
0297         intr_enable &= ~CDNS_XSPI_INTR_MASK;
0298     writel(intr_enable, cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
0299 }
0300 
0301 static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
0302 {
0303     u32 ctrl_ver;
0304     u32 ctrl_features;
0305     u16 hw_magic_num;
0306 
0307     ctrl_ver = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_VERSION_REG);
0308     hw_magic_num = FIELD_GET(CDNS_XSPI_MAGIC_NUM, ctrl_ver);
0309     if (hw_magic_num != CDNS_XSPI_MAGIC_NUM_VALUE) {
0310         dev_err(cdns_xspi->dev,
0311             "Incorrect XSPI magic number: %x, expected: %x\n",
0312             hw_magic_num, CDNS_XSPI_MAGIC_NUM_VALUE);
0313         return -EIO;
0314     }
0315 
0316     ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
0317     cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
0318     cdns_xspi_set_interrupts(cdns_xspi, false);
0319 
0320     return 0;
0321 }
0322 
0323 static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
0324 {
0325     u32 sdma_size, sdma_trd_info;
0326     u8 sdma_dir;
0327 
0328     sdma_size = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_SIZE_REG);
0329     sdma_trd_info = readl(cdns_xspi->iobase + CDNS_XSPI_SDMA_TRD_INFO_REG);
0330     sdma_dir = FIELD_GET(CDNS_XSPI_SDMA_DIR, sdma_trd_info);
0331 
0332     switch (sdma_dir) {
0333     case CDNS_XSPI_SDMA_DIR_READ:
0334         ioread8_rep(cdns_xspi->sdmabase,
0335                 cdns_xspi->in_buffer, sdma_size);
0336         break;
0337 
0338     case CDNS_XSPI_SDMA_DIR_WRITE:
0339         iowrite8_rep(cdns_xspi->sdmabase,
0340                  cdns_xspi->out_buffer, sdma_size);
0341         break;
0342     }
0343 }
0344 
0345 static int cdns_xspi_send_stig_command(struct cdns_xspi_dev *cdns_xspi,
0346                        const struct spi_mem_op *op,
0347                        bool data_phase)
0348 {
0349     u32 cmd_regs[6];
0350     u32 cmd_status;
0351     int ret;
0352 
0353     ret = cdns_xspi_wait_for_controller_idle(cdns_xspi);
0354     if (ret < 0)
0355         return -EIO;
0356 
0357     writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
0358            cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
0359 
0360     cdns_xspi_set_interrupts(cdns_xspi, true);
0361     cdns_xspi->sdma_error = false;
0362 
0363     memset(cmd_regs, 0, sizeof(cmd_regs));
0364     cmd_regs[1] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_1(op, data_phase);
0365     cmd_regs[2] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_2(op);
0366     cmd_regs[3] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_3(op);
0367     cmd_regs[4] = CDNS_XSPI_CMD_FLD_P1_INSTR_CMD_4(op,
0368                                cdns_xspi->cur_cs);
0369 
0370     cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
0371 
0372     if (data_phase) {
0373         cmd_regs[0] = CDNS_XSPI_STIG_DONE_FLAG;
0374         cmd_regs[1] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_1(op);
0375         cmd_regs[2] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_2(op);
0376         cmd_regs[3] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op);
0377         cmd_regs[4] = CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op,
0378                                cdns_xspi->cur_cs);
0379 
0380         cdns_xspi->in_buffer = op->data.buf.in;
0381         cdns_xspi->out_buffer = op->data.buf.out;
0382 
0383         cdns_xspi_trigger_command(cdns_xspi, cmd_regs);
0384 
0385         wait_for_completion(&cdns_xspi->sdma_complete);
0386         if (cdns_xspi->sdma_error) {
0387             cdns_xspi_set_interrupts(cdns_xspi, false);
0388             return -EIO;
0389         }
0390         cdns_xspi_sdma_handle(cdns_xspi);
0391     }
0392 
0393     wait_for_completion(&cdns_xspi->cmd_complete);
0394     cdns_xspi_set_interrupts(cdns_xspi, false);
0395 
0396     cmd_status = cdns_xspi_check_command_status(cdns_xspi);
0397     if (cmd_status)
0398         return -EPROTO;
0399 
0400     return 0;
0401 }
0402 
0403 static int cdns_xspi_mem_op(struct cdns_xspi_dev *cdns_xspi,
0404                 struct spi_mem *mem,
0405                 const struct spi_mem_op *op)
0406 {
0407     enum spi_mem_data_dir dir = op->data.dir;
0408 
0409     if (cdns_xspi->cur_cs != mem->spi->chip_select)
0410         cdns_xspi->cur_cs = mem->spi->chip_select;
0411 
0412     return cdns_xspi_send_stig_command(cdns_xspi, op,
0413                        (dir != SPI_MEM_NO_DATA));
0414 }
0415 
0416 static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
0417                     const struct spi_mem_op *op)
0418 {
0419     struct cdns_xspi_dev *cdns_xspi =
0420         spi_master_get_devdata(mem->spi->master);
0421     int ret = 0;
0422 
0423     ret = cdns_xspi_mem_op(cdns_xspi, mem, op);
0424 
0425     return ret;
0426 }
0427 
0428 static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
0429 {
0430     struct cdns_xspi_dev *cdns_xspi =
0431         spi_master_get_devdata(mem->spi->master);
0432 
0433     op->data.nbytes = clamp_val(op->data.nbytes, 0, cdns_xspi->sdmasize);
0434 
0435     return 0;
0436 }
0437 
0438 static const struct spi_controller_mem_ops cadence_xspi_mem_ops = {
0439     .exec_op = cdns_xspi_mem_op_execute,
0440     .adjust_op_size = cdns_xspi_adjust_mem_op_size,
0441 };
0442 
0443 static irqreturn_t cdns_xspi_irq_handler(int this_irq, void *dev)
0444 {
0445     struct cdns_xspi_dev *cdns_xspi = dev;
0446     u32 irq_status;
0447     irqreturn_t result = IRQ_NONE;
0448 
0449     irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
0450     writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
0451 
0452     if (irq_status &
0453         (CDNS_XSPI_SDMA_ERROR | CDNS_XSPI_SDMA_TRIGGER |
0454          CDNS_XSPI_STIG_DONE)) {
0455         if (irq_status & CDNS_XSPI_SDMA_ERROR) {
0456             dev_err(cdns_xspi->dev,
0457                 "Slave DMA transaction error\n");
0458             cdns_xspi->sdma_error = true;
0459             complete(&cdns_xspi->sdma_complete);
0460         }
0461 
0462         if (irq_status & CDNS_XSPI_SDMA_TRIGGER)
0463             complete(&cdns_xspi->sdma_complete);
0464 
0465         if (irq_status & CDNS_XSPI_STIG_DONE)
0466             complete(&cdns_xspi->cmd_complete);
0467 
0468         result = IRQ_HANDLED;
0469     }
0470 
0471     irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS);
0472     if (irq_status) {
0473         writel(irq_status,
0474                cdns_xspi->iobase + CDNS_XSPI_TRD_COMP_INTR_STATUS);
0475 
0476         complete(&cdns_xspi->auto_cmd_complete);
0477 
0478         result = IRQ_HANDLED;
0479     }
0480 
0481     return result;
0482 }
0483 
0484 static int cdns_xspi_of_get_plat_data(struct platform_device *pdev)
0485 {
0486     struct device_node *node_prop = pdev->dev.of_node;
0487     struct device_node *node_child;
0488     unsigned int cs;
0489 
0490     for_each_child_of_node(node_prop, node_child) {
0491         if (!of_device_is_available(node_child))
0492             continue;
0493 
0494         if (of_property_read_u32(node_child, "reg", &cs)) {
0495             dev_err(&pdev->dev, "Couldn't get memory chip select\n");
0496             of_node_put(node_child);
0497             return -ENXIO;
0498         } else if (cs >= CDNS_XSPI_MAX_BANKS) {
0499             dev_err(&pdev->dev, "reg (cs) parameter value too large\n");
0500             of_node_put(node_child);
0501             return -ENXIO;
0502         }
0503     }
0504 
0505     return 0;
0506 }
0507 
0508 static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
0509 {
0510     struct device *dev = cdns_xspi->dev;
0511 
0512     dev_info(dev, "PHY configuration\n");
0513     dev_info(dev, "   * xspi_dll_phy_ctrl: %08x\n",
0514          readl(cdns_xspi->iobase + CDNS_XSPI_DLL_PHY_CTRL));
0515     dev_info(dev, "   * phy_dq_timing: %08x\n",
0516          readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQ_TIMING));
0517     dev_info(dev, "   * phy_dqs_timing: %08x\n",
0518          readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DQS_TIMING));
0519     dev_info(dev, "   * phy_gate_loopback_ctrl: %08x\n",
0520          readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_GATE_LPBCK_CTRL));
0521     dev_info(dev, "   * phy_dll_slave_ctrl: %08x\n",
0522          readl(cdns_xspi->auxbase + CDNS_XSPI_CCP_PHY_DLL_SLAVE_CTRL));
0523 }
0524 
0525 static int cdns_xspi_probe(struct platform_device *pdev)
0526 {
0527     struct device *dev = &pdev->dev;
0528     struct spi_master *master = NULL;
0529     struct cdns_xspi_dev *cdns_xspi = NULL;
0530     struct resource *res;
0531     int ret;
0532 
0533     master = devm_spi_alloc_master(dev, sizeof(*cdns_xspi));
0534     if (!master)
0535         return -ENOMEM;
0536 
0537     master->mode_bits = SPI_3WIRE | SPI_TX_DUAL  | SPI_TX_QUAD  |
0538         SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
0539         SPI_MODE_0  | SPI_MODE_3;
0540 
0541     master->mem_ops = &cadence_xspi_mem_ops;
0542     master->dev.of_node = pdev->dev.of_node;
0543     master->bus_num = -1;
0544 
0545     platform_set_drvdata(pdev, master);
0546 
0547     cdns_xspi = spi_master_get_devdata(master);
0548     cdns_xspi->pdev = pdev;
0549     cdns_xspi->dev = &pdev->dev;
0550     cdns_xspi->cur_cs = 0;
0551 
0552     init_completion(&cdns_xspi->cmd_complete);
0553     init_completion(&cdns_xspi->auto_cmd_complete);
0554     init_completion(&cdns_xspi->sdma_complete);
0555 
0556     ret = cdns_xspi_of_get_plat_data(pdev);
0557     if (ret)
0558         return -ENODEV;
0559 
0560     cdns_xspi->iobase = devm_platform_ioremap_resource_byname(pdev, "io");
0561     if (IS_ERR(cdns_xspi->iobase)) {
0562         dev_err(dev, "Failed to remap controller base address\n");
0563         return PTR_ERR(cdns_xspi->iobase);
0564     }
0565 
0566     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sdma");
0567     cdns_xspi->sdmabase = devm_ioremap_resource(dev, res);
0568     if (IS_ERR(cdns_xspi->sdmabase)) {
0569         dev_err(dev, "Failed to remap SDMA address\n");
0570         return PTR_ERR(cdns_xspi->sdmabase);
0571     }
0572     cdns_xspi->sdmasize = resource_size(res);
0573 
0574     cdns_xspi->auxbase = devm_platform_ioremap_resource_byname(pdev, "aux");
0575     if (IS_ERR(cdns_xspi->auxbase)) {
0576         dev_err(dev, "Failed to remap AUX address\n");
0577         return PTR_ERR(cdns_xspi->auxbase);
0578     }
0579 
0580     cdns_xspi->irq = platform_get_irq(pdev, 0);
0581     if (cdns_xspi->irq < 0)
0582         return -ENXIO;
0583 
0584     ret = devm_request_irq(dev, cdns_xspi->irq, cdns_xspi_irq_handler,
0585                    IRQF_SHARED, pdev->name, cdns_xspi);
0586     if (ret) {
0587         dev_err(dev, "Failed to request IRQ: %d\n", cdns_xspi->irq);
0588         return ret;
0589     }
0590 
0591     cdns_xspi_print_phy_config(cdns_xspi);
0592 
0593     ret = cdns_xspi_controller_init(cdns_xspi);
0594     if (ret) {
0595         dev_err(dev, "Failed to initialize controller\n");
0596         return ret;
0597     }
0598 
0599     master->num_chipselect = 1 << cdns_xspi->hw_num_banks;
0600 
0601     ret = devm_spi_register_master(dev, master);
0602     if (ret) {
0603         dev_err(dev, "Failed to register SPI master\n");
0604         return ret;
0605     }
0606 
0607     dev_info(dev, "Successfully registered SPI master\n");
0608 
0609     return 0;
0610 }
0611 
0612 #ifdef CONFIG_OF
0613 static const struct of_device_id cdns_xspi_of_match[] = {
0614     {
0615         .compatible = "cdns,xspi-nor",
0616     },
0617     { /* end of table */}
0618 };
0619 MODULE_DEVICE_TABLE(of, cdns_xspi_of_match);
0620 #else
0621 #define cdns_xspi_of_match NULL
0622 #endif /* CONFIG_OF */
0623 
0624 static struct platform_driver cdns_xspi_platform_driver = {
0625     .probe          = cdns_xspi_probe,
0626     .remove         = NULL,
0627     .driver = {
0628         .name = CDNS_XSPI_NAME,
0629         .of_match_table = cdns_xspi_of_match,
0630     },
0631 };
0632 
0633 module_platform_driver(cdns_xspi_platform_driver);
0634 
0635 MODULE_DESCRIPTION("Cadence XSPI Controller Driver");
0636 MODULE_LICENSE("GPL v2");
0637 MODULE_ALIAS("platform:" CDNS_XSPI_NAME);
0638 MODULE_AUTHOR("Konrad Kociolek <konrad@cadence.com>");
0639 MODULE_AUTHOR("Jayshri Pawar <jpawar@cadence.com>");
0640 MODULE_AUTHOR("Parshuram Thombare <pthombar@cadence.com>");
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