drivers/spi/spi-bcm63xx-hsspi.c

0001 /*
0002  * Broadcom BCM63XX High Speed SPI Controller driver
0003  *
0004  * Copyright 2000-2010 Broadcom Corporation
0005  * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
0006  *
0007  * Licensed under the GNU/GPL. See COPYING for details.
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/clk.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/delay.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/err.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/spi/spi.h>
0021 #include <linux/mutex.h>
0022 #include <linux/of.h>
0023 #include <linux/reset.h>
0024 #include <linux/pm_runtime.h>
0025
0026 #define HSSPI_GLOBAL_CTRL_REG           0x0
0027 #define GLOBAL_CTRL_CS_POLARITY_SHIFT       0
0028 #define GLOBAL_CTRL_CS_POLARITY_MASK        0x000000ff
0029 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT      8
0030 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK       0x0000ff00
0031 #define GLOBAL_CTRL_CLK_GATE_SSOFF      BIT(16)
0032 #define GLOBAL_CTRL_CLK_POLARITY        BIT(17)
0033 #define GLOBAL_CTRL_MOSI_IDLE           BIT(18)
0034
0035 #define HSSPI_GLOBAL_EXT_TRIGGER_REG        0x4
0036
0037 #define HSSPI_INT_STATUS_REG            0x8
0038 #define HSSPI_INT_STATUS_MASKED_REG     0xc
0039 #define HSSPI_INT_MASK_REG          0x10
0040
0041 #define HSSPI_PINGx_CMD_DONE(i)         BIT((i * 8) + 0)
0042 #define HSSPI_PINGx_RX_OVER(i)          BIT((i * 8) + 1)
0043 #define HSSPI_PINGx_TX_UNDER(i)         BIT((i * 8) + 2)
0044 #define HSSPI_PINGx_POLL_TIMEOUT(i)     BIT((i * 8) + 3)
0045 #define HSSPI_PINGx_CTRL_INVAL(i)       BIT((i * 8) + 4)
0046
0047 #define HSSPI_INT_CLEAR_ALL         0xff001f1f
0048
0049 #define HSSPI_PINGPONG_COMMAND_REG(x)       (0x80 + (x) * 0x40)
0050 #define PINGPONG_CMD_COMMAND_MASK       0xf
0051 #define PINGPONG_COMMAND_NOOP           0
0052 #define PINGPONG_COMMAND_START_NOW      1
0053 #define PINGPONG_COMMAND_START_TRIGGER      2
0054 #define PINGPONG_COMMAND_HALT           3
0055 #define PINGPONG_COMMAND_FLUSH          4
0056 #define PINGPONG_CMD_PROFILE_SHIFT      8
0057 #define PINGPONG_CMD_SS_SHIFT           12
0058
0059 #define HSSPI_PINGPONG_STATUS_REG(x)        (0x84 + (x) * 0x40)
0060
0061 #define HSSPI_PROFILE_CLK_CTRL_REG(x)       (0x100 + (x) * 0x20)
0062 #define CLK_CTRL_FREQ_CTRL_MASK         0x0000ffff
0063 #define CLK_CTRL_SPI_CLK_2X_SEL         BIT(14)
0064 #define CLK_CTRL_ACCUM_RST_ON_LOOP      BIT(15)
0065
0066 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x)    (0x104 + (x) * 0x20)
0067 #define SIGNAL_CTRL_LATCH_RISING        BIT(12)
0068 #define SIGNAL_CTRL_LAUNCH_RISING       BIT(13)
0069 #define SIGNAL_CTRL_ASYNC_INPUT_PATH        BIT(16)
0070
0071 #define HSSPI_PROFILE_MODE_CTRL_REG(x)      (0x108 + (x) * 0x20)
0072 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT   8
0073 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT   12
0074 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT   16
0075 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT   18
0076 #define MODE_CTRL_MODE_3WIRE            BIT(20)
0077 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT     24
0078
0079 #define HSSPI_FIFO_REG(x)           (0x200 + (x) * 0x200)
0080
0081
0082 #define HSSPI_OP_MULTIBIT           BIT(11)
0083 #define HSSPI_OP_CODE_SHIFT         13
0084 #define HSSPI_OP_SLEEP              (0 << HSSPI_OP_CODE_SHIFT)
0085 #define HSSPI_OP_READ_WRITE         (1 << HSSPI_OP_CODE_SHIFT)
0086 #define HSSPI_OP_WRITE              (2 << HSSPI_OP_CODE_SHIFT)
0087 #define HSSPI_OP_READ               (3 << HSSPI_OP_CODE_SHIFT)
0088 #define HSSPI_OP_SETIRQ             (4 << HSSPI_OP_CODE_SHIFT)
0089
0090 #define HSSPI_BUFFER_LEN            512
0091 #define HSSPI_OPCODE_LEN            2
0092
0093 #define HSSPI_MAX_PREPEND_LEN           15
0094
0095 #define HSSPI_MAX_SYNC_CLOCK            30000000
0096
0097 #define HSSPI_SPI_MAX_CS            8
0098 #define HSSPI_BUS_NUM               1 /* 0 is legacy SPI */
0099
0100 struct bcm63xx_hsspi {
0101     struct completion done;
0102     struct mutex bus_mutex;
0103
0104     struct platform_device *pdev;
0105     struct clk *clk;
0106     struct clk *pll_clk;
0107     void __iomem *regs;
0108     u8 __iomem *fifo;
0109
0110     u32 speed_hz;
0111     u8 cs_polarity;
0112 };
0113
0114 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
0115                  bool active)
0116 {
0117     u32 reg;
0118
0119     mutex_lock(&bs->bus_mutex);
0120     reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
0121
0122     reg &= ~BIT(cs);
0123     if (active == !(bs->cs_polarity & BIT(cs)))
0124         reg |= BIT(cs);
0125
0126     __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
0127     mutex_unlock(&bs->bus_mutex);
0128 }
0129
0130 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
0131                   struct spi_device *spi, int hz)
0132 {
0133     unsigned int profile = spi->chip_select;
0134     u32 reg;
0135
0136     reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
0137     __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
0138              bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
0139
0140     reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
0141     if (hz > HSSPI_MAX_SYNC_CLOCK)
0142         reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
0143     else
0144         reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
0145     __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
0146
0147     mutex_lock(&bs->bus_mutex);
0148     /* setup clock polarity */
0149     reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
0150     reg &= ~GLOBAL_CTRL_CLK_POLARITY;
0151     if (spi->mode & SPI_CPOL)
0152         reg |= GLOBAL_CTRL_CLK_POLARITY;
0153     __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
0154     mutex_unlock(&bs->bus_mutex);
0155 }
0156
0157 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
0158 {
0159     struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
0160     unsigned int chip_select = spi->chip_select;
0161     u16 opcode = 0;
0162     int pending = t->len;
0163     int step_size = HSSPI_BUFFER_LEN;
0164     const u8 *tx = t->tx_buf;
0165     u8 *rx = t->rx_buf;
0166
0167     bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
0168     bcm63xx_hsspi_set_cs(bs, spi->chip_select, true);
0169
0170     if (tx && rx)
0171         opcode = HSSPI_OP_READ_WRITE;
0172     else if (tx)
0173         opcode = HSSPI_OP_WRITE;
0174     else if (rx)
0175         opcode = HSSPI_OP_READ;
0176
0177     if (opcode != HSSPI_OP_READ)
0178         step_size -= HSSPI_OPCODE_LEN;
0179
0180     if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
0181         (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL))
0182         opcode |= HSSPI_OP_MULTIBIT;
0183
0184     __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT |
0185              1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff,
0186              bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
0187
0188     while (pending > 0) {
0189         int curr_step = min_t(int, step_size, pending);
0190
0191         reinit_completion(&bs->done);
0192         if (tx) {
0193             memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
0194             tx += curr_step;
0195         }
0196
0197         __raw_writew(opcode | curr_step, bs->fifo);
0198
0199         /* enable interrupt */
0200         __raw_writel(HSSPI_PINGx_CMD_DONE(0),
0201                  bs->regs + HSSPI_INT_MASK_REG);
0202
0203         /* start the transfer */
0204         __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT |
0205                  chip_select << PINGPONG_CMD_PROFILE_SHIFT |
0206                  PINGPONG_COMMAND_START_NOW,
0207                  bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
0208
0209         if (wait_for_completion_timeout(&bs->done, HZ) == 0) {
0210             dev_err(&bs->pdev->dev, "transfer timed out!\n");
0211             return -ETIMEDOUT;
0212         }
0213
0214         if (rx) {
0215             memcpy_fromio(rx, bs->fifo, curr_step);
0216             rx += curr_step;
0217         }
0218
0219         pending -= curr_step;
0220     }
0221
0222     return 0;
0223 }
0224
0225 static int bcm63xx_hsspi_setup(struct spi_device *spi)
0226 {
0227     struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
0228     u32 reg;
0229
0230     reg = __raw_readl(bs->regs +
0231               HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
0232     reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
0233     if (spi->mode & SPI_CPHA)
0234         reg |= SIGNAL_CTRL_LAUNCH_RISING;
0235     else
0236         reg |= SIGNAL_CTRL_LATCH_RISING;
0237     __raw_writel(reg, bs->regs +
0238              HSSPI_PROFILE_SIGNAL_CTRL_REG(spi->chip_select));
0239
0240     mutex_lock(&bs->bus_mutex);
0241     reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
0242
0243     /* only change actual polarities if there is no transfer */
0244     if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
0245         if (spi->mode & SPI_CS_HIGH)
0246             reg |= BIT(spi->chip_select);
0247         else
0248             reg &= ~BIT(spi->chip_select);
0249         __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
0250     }
0251
0252     if (spi->mode & SPI_CS_HIGH)
0253         bs->cs_polarity |= BIT(spi->chip_select);
0254     else
0255         bs->cs_polarity &= ~BIT(spi->chip_select);
0256
0257     mutex_unlock(&bs->bus_mutex);
0258
0259     return 0;
0260 }
0261
0262 static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
0263                       struct spi_message *msg)
0264 {
0265     struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
0266     struct spi_transfer *t;
0267     struct spi_device *spi = msg->spi;
0268     int status = -EINVAL;
0269     int dummy_cs;
0270     u32 reg;
0271
0272     /* This controller does not support keeping CS active during idle.
0273      * To work around this, we use the following ugly hack:
0274      *
0275      * a. Invert the target chip select's polarity so it will be active.
0276      * b. Select a "dummy" chip select to use as the hardware target.
0277      * c. Invert the dummy chip select's polarity so it will be inactive
0278      *    during the actual transfers.
0279      * d. Tell the hardware to send to the dummy chip select. Thanks to
0280      *    the multiplexed nature of SPI the actual target will receive
0281      *    the transfer and we see its response.
0282      *
0283      * e. At the end restore the polarities again to their default values.
0284      */
0285
0286     dummy_cs = !spi->chip_select;
0287     bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
0288
0289     list_for_each_entry(t, &msg->transfers, transfer_list) {
0290         status = bcm63xx_hsspi_do_txrx(spi, t);
0291         if (status)
0292             break;
0293
0294         msg->actual_length += t->len;
0295
0296         spi_transfer_delay_exec(t);
0297
0298         if (t->cs_change)
0299             bcm63xx_hsspi_set_cs(bs, spi->chip_select, false);
0300     }
0301
0302     mutex_lock(&bs->bus_mutex);
0303     reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
0304     reg &= ~GLOBAL_CTRL_CS_POLARITY_MASK;
0305     reg |= bs->cs_polarity;
0306     __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
0307     mutex_unlock(&bs->bus_mutex);
0308
0309     msg->status = status;
0310     spi_finalize_current_message(master);
0311
0312     return 0;
0313 }
0314
0315 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
0316 {
0317     struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
0318
0319     if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
0320         return IRQ_NONE;
0321
0322     __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
0323     __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
0324
0325     complete(&bs->done);
0326
0327     return IRQ_HANDLED;
0328 }
0329
0330 static int bcm63xx_hsspi_probe(struct platform_device *pdev)
0331 {
0332     struct spi_master *master;
0333     struct bcm63xx_hsspi *bs;
0334     void __iomem *regs;
0335     struct device *dev = &pdev->dev;
0336     struct clk *clk, *pll_clk = NULL;
0337     int irq, ret;
0338     u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
0339     struct reset_control *reset;
0340
0341     irq = platform_get_irq(pdev, 0);
0342     if (irq < 0)
0343         return irq;
0344
0345     regs = devm_platform_ioremap_resource(pdev, 0);
0346     if (IS_ERR(regs))
0347         return PTR_ERR(regs);
0348
0349     clk = devm_clk_get(dev, "hsspi");
0350
0351     if (IS_ERR(clk))
0352         return PTR_ERR(clk);
0353
0354     reset = devm_reset_control_get_optional_exclusive(dev, NULL);
0355     if (IS_ERR(reset))
0356         return PTR_ERR(reset);
0357
0358     ret = clk_prepare_enable(clk);
0359     if (ret)
0360         return ret;
0361
0362     ret = reset_control_reset(reset);
0363     if (ret) {
0364         dev_err(dev, "unable to reset device: %d\n", ret);
0365         goto out_disable_clk;
0366     }
0367
0368     rate = clk_get_rate(clk);
0369     if (!rate) {
0370         pll_clk = devm_clk_get(dev, "pll");
0371
0372         if (IS_ERR(pll_clk)) {
0373             ret = PTR_ERR(pll_clk);
0374             goto out_disable_clk;
0375         }
0376
0377         ret = clk_prepare_enable(pll_clk);
0378         if (ret)
0379             goto out_disable_clk;
0380
0381         rate = clk_get_rate(pll_clk);
0382         if (!rate) {
0383             ret = -EINVAL;
0384             goto out_disable_pll_clk;
0385         }
0386     }
0387
0388     master = spi_alloc_master(&pdev->dev, sizeof(*bs));
0389     if (!master) {
0390         ret = -ENOMEM;
0391         goto out_disable_pll_clk;
0392     }
0393
0394     bs = spi_master_get_devdata(master);
0395     bs->pdev = pdev;
0396     bs->clk = clk;
0397     bs->pll_clk = pll_clk;
0398     bs->regs = regs;
0399     bs->speed_hz = rate;
0400     bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
0401
0402     mutex_init(&bs->bus_mutex);
0403     init_completion(&bs->done);
0404
0405     master->dev.of_node = dev->of_node;
0406     if (!dev->of_node)
0407         master->bus_num = HSSPI_BUS_NUM;
0408
0409     of_property_read_u32(dev->of_node, "num-cs", &num_cs);
0410     if (num_cs > 8) {
0411         dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
0412              num_cs);
0413         num_cs = HSSPI_SPI_MAX_CS;
0414     }
0415     master->num_chipselect = num_cs;
0416     master->setup = bcm63xx_hsspi_setup;
0417     master->transfer_one_message = bcm63xx_hsspi_transfer_one;
0418     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
0419                 SPI_RX_DUAL | SPI_TX_DUAL;
0420     master->bits_per_word_mask = SPI_BPW_MASK(8);
0421     master->auto_runtime_pm = true;
0422
0423     platform_set_drvdata(pdev, master);
0424
0425     /* Initialize the hardware */
0426     __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
0427
0428     /* clean up any pending interrupts */
0429     __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
0430
0431     /* read out default CS polarities */
0432     reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
0433     bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
0434     __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
0435              bs->regs + HSSPI_GLOBAL_CTRL_REG);
0436
0437     ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
0438                    pdev->name, bs);
0439
0440     if (ret)
0441         goto out_put_master;
0442
0443     pm_runtime_enable(&pdev->dev);
0444
0445     /* register and we are done */
0446     ret = devm_spi_register_master(dev, master);
0447     if (ret)
0448         goto out_pm_disable;
0449
0450     return 0;
0451
0452 out_pm_disable:
0453     pm_runtime_disable(&pdev->dev);
0454 out_put_master:
0455     spi_master_put(master);
0456 out_disable_pll_clk:
0457     clk_disable_unprepare(pll_clk);
0458 out_disable_clk:
0459     clk_disable_unprepare(clk);
0460     return ret;
0461 }
0462
0463
0464 static int bcm63xx_hsspi_remove(struct platform_device *pdev)
0465 {
0466     struct spi_master *master = platform_get_drvdata(pdev);
0467     struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
0468
0469     /* reset the hardware and block queue progress */
0470     __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
0471     clk_disable_unprepare(bs->pll_clk);
0472     clk_disable_unprepare(bs->clk);
0473
0474     return 0;
0475 }
0476
0477 #ifdef CONFIG_PM_SLEEP
0478 static int bcm63xx_hsspi_suspend(struct device *dev)
0479 {
0480     struct spi_master *master = dev_get_drvdata(dev);
0481     struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
0482
0483     spi_master_suspend(master);
0484     clk_disable_unprepare(bs->pll_clk);
0485     clk_disable_unprepare(bs->clk);
0486
0487     return 0;
0488 }
0489
0490 static int bcm63xx_hsspi_resume(struct device *dev)
0491 {
0492     struct spi_master *master = dev_get_drvdata(dev);
0493     struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
0494     int ret;
0495
0496     ret = clk_prepare_enable(bs->clk);
0497     if (ret)
0498         return ret;
0499
0500     if (bs->pll_clk) {
0501         ret = clk_prepare_enable(bs->pll_clk);
0502         if (ret) {
0503             clk_disable_unprepare(bs->clk);
0504             return ret;
0505         }
0506     }
0507
0508     spi_master_resume(master);
0509
0510     return 0;
0511 }
0512 #endif
0513
0514 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
0515              bcm63xx_hsspi_resume);
0516
0517 static const struct of_device_id bcm63xx_hsspi_of_match[] = {
0518     { .compatible = "brcm,bcm6328-hsspi", },
0519     { },
0520 };
0521 MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
0522
0523 static struct platform_driver bcm63xx_hsspi_driver = {
0524     .driver = {
0525         .name   = "bcm63xx-hsspi",
0526         .pm = &bcm63xx_hsspi_pm_ops,
0527         .of_match_table = bcm63xx_hsspi_of_match,
0528     },
0529     .probe      = bcm63xx_hsspi_probe,
0530     .remove     = bcm63xx_hsspi_remove,
0531 };
0532
0533 module_platform_driver(bcm63xx_hsspi_driver);
0534
0535 MODULE_ALIAS("platform:bcm63xx_hsspi");
0536 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
0537 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
0538 MODULE_LICENSE("GPL");