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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Broadcom BCM2835 auxiliary SPI Controllers
0004  *
0005  * the driver does not rely on the native chipselects at all
0006  * but only uses the gpio type chipselects
0007  *
0008  * Based on: spi-bcm2835.c
0009  *
0010  * Copyright (C) 2015 Martin Sperl
0011  */
0012 
0013 #include <linux/clk.h>
0014 #include <linux/completion.h>
0015 #include <linux/debugfs.h>
0016 #include <linux/delay.h>
0017 #include <linux/err.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/io.h>
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_address.h>
0024 #include <linux/of_device.h>
0025 #include <linux/of_irq.h>
0026 #include <linux/regmap.h>
0027 #include <linux/spi/spi.h>
0028 #include <linux/spinlock.h>
0029 
0030 /* define polling limits */
0031 static unsigned int polling_limit_us = 30;
0032 module_param(polling_limit_us, uint, 0664);
0033 MODULE_PARM_DESC(polling_limit_us,
0034          "time in us to run a transfer in polling mode - if zero no polling is used\n");
0035 
0036 /*
0037  * spi register defines
0038  *
0039  * note there is garbage in the "official" documentation,
0040  * so some data is taken from the file:
0041  *   brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h
0042  * inside of:
0043  *   http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz
0044  */
0045 
0046 /* SPI register offsets */
0047 #define BCM2835_AUX_SPI_CNTL0   0x00
0048 #define BCM2835_AUX_SPI_CNTL1   0x04
0049 #define BCM2835_AUX_SPI_STAT    0x08
0050 #define BCM2835_AUX_SPI_PEEK    0x0C
0051 #define BCM2835_AUX_SPI_IO  0x20
0052 #define BCM2835_AUX_SPI_TXHOLD  0x30
0053 
0054 /* Bitfields in CNTL0 */
0055 #define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF00000
0056 #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF
0057 #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT   20
0058 #define BCM2835_AUX_SPI_CNTL0_CS    0x000E0000
0059 #define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x00010000
0060 #define BCM2835_AUX_SPI_CNTL0_VAR_CS    0x00008000
0061 #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x00004000
0062 #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD  0x00003000
0063 #define BCM2835_AUX_SPI_CNTL0_ENABLE    0x00000800
0064 #define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x00000400
0065 #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x00000200
0066 #define BCM2835_AUX_SPI_CNTL0_OUT_RISING    0x00000100
0067 #define BCM2835_AUX_SPI_CNTL0_CPOL  0x00000080
0068 #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT  0x00000040
0069 #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN  0x0000003F
0070 
0071 /* Bitfields in CNTL1 */
0072 #define BCM2835_AUX_SPI_CNTL1_CSHIGH    0x00000700
0073 #define BCM2835_AUX_SPI_CNTL1_TXEMPTY   0x00000080
0074 #define BCM2835_AUX_SPI_CNTL1_IDLE  0x00000040
0075 #define BCM2835_AUX_SPI_CNTL1_MSBF_IN   0x00000002
0076 #define BCM2835_AUX_SPI_CNTL1_KEEP_IN   0x00000001
0077 
0078 /* Bitfields in STAT */
0079 #define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF000000
0080 #define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF0000
0081 #define BCM2835_AUX_SPI_STAT_TX_FULL    0x00000400
0082 #define BCM2835_AUX_SPI_STAT_TX_EMPTY   0x00000200
0083 #define BCM2835_AUX_SPI_STAT_RX_FULL    0x00000100
0084 #define BCM2835_AUX_SPI_STAT_RX_EMPTY   0x00000080
0085 #define BCM2835_AUX_SPI_STAT_BUSY   0x00000040
0086 #define BCM2835_AUX_SPI_STAT_BITCOUNT   0x0000003F
0087 
0088 struct bcm2835aux_spi {
0089     void __iomem *regs;
0090     struct clk *clk;
0091     int irq;
0092     u32 cntl[2];
0093     const u8 *tx_buf;
0094     u8 *rx_buf;
0095     int tx_len;
0096     int rx_len;
0097     int pending;
0098 
0099     u64 count_transfer_polling;
0100     u64 count_transfer_irq;
0101     u64 count_transfer_irq_after_poll;
0102 
0103     struct dentry *debugfs_dir;
0104 };
0105 
0106 #if defined(CONFIG_DEBUG_FS)
0107 static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
0108                       const char *dname)
0109 {
0110     char name[64];
0111     struct dentry *dir;
0112 
0113     /* get full name */
0114     snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);
0115 
0116     /* the base directory */
0117     dir = debugfs_create_dir(name, NULL);
0118     bs->debugfs_dir = dir;
0119 
0120     /* the counters */
0121     debugfs_create_u64("count_transfer_polling", 0444, dir,
0122                &bs->count_transfer_polling);
0123     debugfs_create_u64("count_transfer_irq", 0444, dir,
0124                &bs->count_transfer_irq);
0125     debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,
0126                &bs->count_transfer_irq_after_poll);
0127 }
0128 
0129 static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
0130 {
0131     debugfs_remove_recursive(bs->debugfs_dir);
0132     bs->debugfs_dir = NULL;
0133 }
0134 #else
0135 static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,
0136                       const char *dname)
0137 {
0138 }
0139 
0140 static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)
0141 {
0142 }
0143 #endif /* CONFIG_DEBUG_FS */
0144 
0145 static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned int reg)
0146 {
0147     return readl(bs->regs + reg);
0148 }
0149 
0150 static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned int reg,
0151                  u32 val)
0152 {
0153     writel(val, bs->regs + reg);
0154 }
0155 
0156 static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)
0157 {
0158     u32 data;
0159     int count = min(bs->rx_len, 3);
0160 
0161     data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);
0162     if (bs->rx_buf) {
0163         switch (count) {
0164         case 3:
0165             *bs->rx_buf++ = (data >> 16) & 0xff;
0166             fallthrough;
0167         case 2:
0168             *bs->rx_buf++ = (data >> 8) & 0xff;
0169             fallthrough;
0170         case 1:
0171             *bs->rx_buf++ = (data >> 0) & 0xff;
0172             /* fallthrough - no default */
0173         }
0174     }
0175     bs->rx_len -= count;
0176     bs->pending -= count;
0177 }
0178 
0179 static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)
0180 {
0181     u32 data;
0182     u8 byte;
0183     int count;
0184     int i;
0185 
0186     /* gather up to 3 bytes to write to the FIFO */
0187     count = min(bs->tx_len, 3);
0188     data = 0;
0189     for (i = 0; i < count; i++) {
0190         byte = bs->tx_buf ? *bs->tx_buf++ : 0;
0191         data |= byte << (8 * (2 - i));
0192     }
0193 
0194     /* and set the variable bit-length */
0195     data |= (count * 8) << 24;
0196 
0197     /* and decrement length */
0198     bs->tx_len -= count;
0199     bs->pending += count;
0200 
0201     /* write to the correct TX-register */
0202     if (bs->tx_len)
0203         bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);
0204     else
0205         bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);
0206 }
0207 
0208 static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)
0209 {
0210     /* disable spi clearing fifo and interrupts */
0211     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);
0212     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,
0213               BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
0214 }
0215 
0216 static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
0217 {
0218     u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);
0219 
0220     /* check if we have data to read */
0221     for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);
0222          stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))
0223         bcm2835aux_rd_fifo(bs);
0224 
0225     /* check if we have data to write */
0226     while (bs->tx_len &&
0227            (bs->pending < 12) &&
0228            (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
0229           BCM2835_AUX_SPI_STAT_TX_FULL))) {
0230         bcm2835aux_wr_fifo(bs);
0231     }
0232 }
0233 
0234 static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
0235 {
0236     struct spi_master *master = dev_id;
0237     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0238 
0239     /* IRQ may be shared, so return if our interrupts are disabled */
0240     if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
0241           (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))
0242         return IRQ_NONE;
0243 
0244     /* do common fifo handling */
0245     bcm2835aux_spi_transfer_helper(bs);
0246 
0247     if (!bs->tx_len) {
0248         /* disable tx fifo empty interrupt */
0249         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
0250             BCM2835_AUX_SPI_CNTL1_IDLE);
0251     }
0252 
0253     /* and if rx_len is 0 then disable interrupts and wake up completion */
0254     if (!bs->rx_len) {
0255         bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
0256         spi_finalize_current_transfer(master);
0257     }
0258 
0259     return IRQ_HANDLED;
0260 }
0261 
0262 static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
0263                          struct spi_device *spi,
0264                          struct spi_transfer *tfr)
0265 {
0266     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0267 
0268     /* enable interrupts */
0269     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
0270         BCM2835_AUX_SPI_CNTL1_TXEMPTY |
0271         BCM2835_AUX_SPI_CNTL1_IDLE);
0272 
0273     /* and wait for finish... */
0274     return 1;
0275 }
0276 
0277 static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
0278                        struct spi_device *spi,
0279                        struct spi_transfer *tfr)
0280 {
0281     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0282 
0283     /* update statistics */
0284     bs->count_transfer_irq++;
0285 
0286     /* fill in registers and fifos before enabling interrupts */
0287     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
0288     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
0289 
0290     /* fill in tx fifo with data before enabling interrupts */
0291     while ((bs->tx_len) &&
0292            (bs->pending < 12) &&
0293            (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &
0294           BCM2835_AUX_SPI_STAT_TX_FULL))) {
0295         bcm2835aux_wr_fifo(bs);
0296     }
0297 
0298     /* now run the interrupt mode */
0299     return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
0300 }
0301 
0302 static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
0303                         struct spi_device *spi,
0304                     struct spi_transfer *tfr)
0305 {
0306     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0307     unsigned long timeout;
0308 
0309     /* update statistics */
0310     bs->count_transfer_polling++;
0311 
0312     /* configure spi */
0313     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
0314     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
0315 
0316     /* set the timeout to at least 2 jiffies */
0317     timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;
0318 
0319     /* loop until finished the transfer */
0320     while (bs->rx_len) {
0321 
0322         /* do common fifo handling */
0323         bcm2835aux_spi_transfer_helper(bs);
0324 
0325         /* there is still data pending to read check the timeout */
0326         if (bs->rx_len && time_after(jiffies, timeout)) {
0327             dev_dbg_ratelimited(&spi->dev,
0328                         "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",
0329                         jiffies - timeout,
0330                         bs->tx_len, bs->rx_len);
0331             /* forward to interrupt handler */
0332             bs->count_transfer_irq_after_poll++;
0333             return __bcm2835aux_spi_transfer_one_irq(master,
0334                                    spi, tfr);
0335         }
0336     }
0337 
0338     /* and return without waiting for completion */
0339     return 0;
0340 }
0341 
0342 static int bcm2835aux_spi_transfer_one(struct spi_master *master,
0343                        struct spi_device *spi,
0344                        struct spi_transfer *tfr)
0345 {
0346     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0347     unsigned long spi_hz, clk_hz, speed;
0348     unsigned long hz_per_byte, byte_limit;
0349 
0350     /* calculate the registers to handle
0351      *
0352      * note that we use the variable data mode, which
0353      * is not optimal for longer transfers as we waste registers
0354      * resulting (potentially) in more interrupts when transferring
0355      * more than 12 bytes
0356      */
0357 
0358     /* set clock */
0359     spi_hz = tfr->speed_hz;
0360     clk_hz = clk_get_rate(bs->clk);
0361 
0362     if (spi_hz >= clk_hz / 2) {
0363         speed = 0;
0364     } else if (spi_hz) {
0365         speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;
0366         if (speed >  BCM2835_AUX_SPI_CNTL0_SPEED_MAX)
0367             speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
0368     } else { /* the slowest we can go */
0369         speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;
0370     }
0371     /* mask out old speed from previous spi_transfer */
0372     bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);
0373     /* set the new speed */
0374     bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;
0375 
0376     tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));
0377 
0378     /* set transmit buffers and length */
0379     bs->tx_buf = tfr->tx_buf;
0380     bs->rx_buf = tfr->rx_buf;
0381     bs->tx_len = tfr->len;
0382     bs->rx_len = tfr->len;
0383     bs->pending = 0;
0384 
0385     /* Calculate the estimated time in us the transfer runs.  Note that
0386      * there are 2 idle clocks cycles after each chunk getting
0387      * transferred - in our case the chunk size is 3 bytes, so we
0388      * approximate this by 9 cycles/byte.  This is used to find the number
0389      * of Hz per byte per polling limit.  E.g., we can transfer 1 byte in
0390      * 30 µs per 300,000 Hz of bus clock.
0391      */
0392     hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;
0393     byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;
0394 
0395     /* run in polling mode for short transfers */
0396     if (tfr->len < byte_limit)
0397         return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
0398 
0399     /* run in interrupt mode for all others */
0400     return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
0401 }
0402 
0403 static int bcm2835aux_spi_prepare_message(struct spi_master *master,
0404                       struct spi_message *msg)
0405 {
0406     struct spi_device *spi = msg->spi;
0407     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0408 
0409     bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
0410               BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
0411               BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
0412     bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
0413 
0414     /* handle all the modes */
0415     if (spi->mode & SPI_CPOL) {
0416         bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
0417         bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;
0418     } else {
0419         bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;
0420     }
0421     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
0422     bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);
0423 
0424     return 0;
0425 }
0426 
0427 static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
0428                         struct spi_message *msg)
0429 {
0430     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0431 
0432     bcm2835aux_spi_reset_hw(bs);
0433 
0434     return 0;
0435 }
0436 
0437 static void bcm2835aux_spi_handle_err(struct spi_master *master,
0438                       struct spi_message *msg)
0439 {
0440     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0441 
0442     bcm2835aux_spi_reset_hw(bs);
0443 }
0444 
0445 static int bcm2835aux_spi_setup(struct spi_device *spi)
0446 {
0447     /* sanity check for native cs */
0448     if (spi->mode & SPI_NO_CS)
0449         return 0;
0450 
0451     if (spi->cs_gpiod)
0452         return 0;
0453 
0454     /* for dt-backwards compatibility: only support native on CS0
0455      * known things not supported with broken native CS:
0456      * * multiple chip-selects: cs0-cs2 are all
0457      *     simultaniously asserted whenever there is a transfer
0458      *     this even includes SPI_NO_CS
0459      * * SPI_CS_HIGH: cs are always asserted low
0460      * * cs_change: cs is deasserted after each spi_transfer
0461      * * cs_delay_usec: cs is always deasserted one SCK cycle
0462      *     after the last transfer
0463      * probably more...
0464      */
0465     dev_warn(&spi->dev,
0466          "Native CS is not supported - please configure cs-gpio in device-tree\n");
0467 
0468     if (spi->chip_select == 0)
0469         return 0;
0470 
0471     dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");
0472 
0473     return -EINVAL;
0474 }
0475 
0476 static int bcm2835aux_spi_probe(struct platform_device *pdev)
0477 {
0478     struct spi_master *master;
0479     struct bcm2835aux_spi *bs;
0480     unsigned long clk_hz;
0481     int err;
0482 
0483     master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
0484     if (!master)
0485         return -ENOMEM;
0486 
0487     platform_set_drvdata(pdev, master);
0488     master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
0489     master->bits_per_word_mask = SPI_BPW_MASK(8);
0490     /* even though the driver never officially supported native CS
0491      * allow a single native CS for legacy DT support purposes when
0492      * no cs-gpio is configured.
0493      * Known limitations for native cs are:
0494      * * multiple chip-selects: cs0-cs2 are all simultaniously asserted
0495      *     whenever there is a transfer -  this even includes SPI_NO_CS
0496      * * SPI_CS_HIGH: is ignores - cs are always asserted low
0497      * * cs_change: cs is deasserted after each spi_transfer
0498      * * cs_delay_usec: cs is always deasserted one SCK cycle after
0499      *     a spi_transfer
0500      */
0501     master->num_chipselect = 1;
0502     master->setup = bcm2835aux_spi_setup;
0503     master->transfer_one = bcm2835aux_spi_transfer_one;
0504     master->handle_err = bcm2835aux_spi_handle_err;
0505     master->prepare_message = bcm2835aux_spi_prepare_message;
0506     master->unprepare_message = bcm2835aux_spi_unprepare_message;
0507     master->dev.of_node = pdev->dev.of_node;
0508     master->use_gpio_descriptors = true;
0509 
0510     bs = spi_master_get_devdata(master);
0511 
0512     /* the main area */
0513     bs->regs = devm_platform_ioremap_resource(pdev, 0);
0514     if (IS_ERR(bs->regs))
0515         return PTR_ERR(bs->regs);
0516 
0517     bs->clk = devm_clk_get(&pdev->dev, NULL);
0518     if (IS_ERR(bs->clk)) {
0519         err = PTR_ERR(bs->clk);
0520         dev_err(&pdev->dev, "could not get clk: %d\n", err);
0521         return err;
0522     }
0523 
0524     bs->irq = platform_get_irq(pdev, 0);
0525     if (bs->irq <= 0)
0526         return bs->irq ? bs->irq : -ENODEV;
0527 
0528     /* this also enables the HW block */
0529     err = clk_prepare_enable(bs->clk);
0530     if (err) {
0531         dev_err(&pdev->dev, "could not prepare clock: %d\n", err);
0532         return err;
0533     }
0534 
0535     /* just checking if the clock returns a sane value */
0536     clk_hz = clk_get_rate(bs->clk);
0537     if (!clk_hz) {
0538         dev_err(&pdev->dev, "clock returns 0 Hz\n");
0539         err = -ENODEV;
0540         goto out_clk_disable;
0541     }
0542 
0543     /* reset SPI-HW block */
0544     bcm2835aux_spi_reset_hw(bs);
0545 
0546     err = devm_request_irq(&pdev->dev, bs->irq,
0547                    bcm2835aux_spi_interrupt,
0548                    IRQF_SHARED,
0549                    dev_name(&pdev->dev), master);
0550     if (err) {
0551         dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
0552         goto out_clk_disable;
0553     }
0554 
0555     err = spi_register_master(master);
0556     if (err) {
0557         dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
0558         goto out_clk_disable;
0559     }
0560 
0561     bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));
0562 
0563     return 0;
0564 
0565 out_clk_disable:
0566     clk_disable_unprepare(bs->clk);
0567     return err;
0568 }
0569 
0570 static int bcm2835aux_spi_remove(struct platform_device *pdev)
0571 {
0572     struct spi_master *master = platform_get_drvdata(pdev);
0573     struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
0574 
0575     bcm2835aux_debugfs_remove(bs);
0576 
0577     spi_unregister_master(master);
0578 
0579     bcm2835aux_spi_reset_hw(bs);
0580 
0581     /* disable the HW block by releasing the clock */
0582     clk_disable_unprepare(bs->clk);
0583 
0584     return 0;
0585 }
0586 
0587 static const struct of_device_id bcm2835aux_spi_match[] = {
0588     { .compatible = "brcm,bcm2835-aux-spi", },
0589     {}
0590 };
0591 MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);
0592 
0593 static struct platform_driver bcm2835aux_spi_driver = {
0594     .driver     = {
0595         .name       = "spi-bcm2835aux",
0596         .of_match_table = bcm2835aux_spi_match,
0597     },
0598     .probe      = bcm2835aux_spi_probe,
0599     .remove     = bcm2835aux_spi_remove,
0600 };
0601 module_platform_driver(bcm2835aux_spi_driver);
0602 
0603 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");
0604 MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");
0605 MODULE_LICENSE("GPL");
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