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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for Broadcom BRCMSTB, NSP,  NS2, Cygnus SPI Controllers
0004  *
0005  * Copyright 2016 Broadcom
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/ioport.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 #include <linux/spi/spi.h>
0022 #include <linux/spi/spi-mem.h>
0023 #include <linux/sysfs.h>
0024 #include <linux/types.h>
0025 #include "spi-bcm-qspi.h"
0026 
0027 #define DRIVER_NAME "bcm_qspi"
0028 
0029 
0030 /* BSPI register offsets */
0031 #define BSPI_REVISION_ID            0x000
0032 #define BSPI_SCRATCH                0x004
0033 #define BSPI_MAST_N_BOOT_CTRL           0x008
0034 #define BSPI_BUSY_STATUS            0x00c
0035 #define BSPI_INTR_STATUS            0x010
0036 #define BSPI_B0_STATUS              0x014
0037 #define BSPI_B0_CTRL                0x018
0038 #define BSPI_B1_STATUS              0x01c
0039 #define BSPI_B1_CTRL                0x020
0040 #define BSPI_STRAP_OVERRIDE_CTRL        0x024
0041 #define BSPI_FLEX_MODE_ENABLE           0x028
0042 #define BSPI_BITS_PER_CYCLE         0x02c
0043 #define BSPI_BITS_PER_PHASE         0x030
0044 #define BSPI_CMD_AND_MODE_BYTE          0x034
0045 #define BSPI_BSPI_FLASH_UPPER_ADDR_BYTE 0x038
0046 #define BSPI_BSPI_XOR_VALUE         0x03c
0047 #define BSPI_BSPI_XOR_ENABLE            0x040
0048 #define BSPI_BSPI_PIO_MODE_ENABLE       0x044
0049 #define BSPI_BSPI_PIO_IODIR         0x048
0050 #define BSPI_BSPI_PIO_DATA          0x04c
0051 
0052 /* RAF register offsets */
0053 #define BSPI_RAF_START_ADDR         0x100
0054 #define BSPI_RAF_NUM_WORDS          0x104
0055 #define BSPI_RAF_CTRL               0x108
0056 #define BSPI_RAF_FULLNESS           0x10c
0057 #define BSPI_RAF_WATERMARK          0x110
0058 #define BSPI_RAF_STATUS         0x114
0059 #define BSPI_RAF_READ_DATA          0x118
0060 #define BSPI_RAF_WORD_CNT           0x11c
0061 #define BSPI_RAF_CURR_ADDR          0x120
0062 
0063 /* Override mode masks */
0064 #define BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE   BIT(0)
0065 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL  BIT(1)
0066 #define BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE BIT(2)
0067 #define BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD  BIT(3)
0068 #define BSPI_STRAP_OVERRIDE_CTRL_ENDAIN_MODE    BIT(4)
0069 
0070 #define BSPI_ADDRLEN_3BYTES         3
0071 #define BSPI_ADDRLEN_4BYTES         4
0072 
0073 #define BSPI_RAF_STATUS_FIFO_EMPTY_MASK BIT(1)
0074 
0075 #define BSPI_RAF_CTRL_START_MASK        BIT(0)
0076 #define BSPI_RAF_CTRL_CLEAR_MASK        BIT(1)
0077 
0078 #define BSPI_BPP_MODE_SELECT_MASK       BIT(8)
0079 #define BSPI_BPP_ADDR_SELECT_MASK       BIT(16)
0080 
0081 #define BSPI_READ_LENGTH            256
0082 
0083 /* MSPI register offsets */
0084 #define MSPI_SPCR0_LSB              0x000
0085 #define MSPI_SPCR0_MSB              0x004
0086 #define MSPI_SPCR0_MSB_CPHA         BIT(0)
0087 #define MSPI_SPCR0_MSB_CPOL         BIT(1)
0088 #define MSPI_SPCR0_MSB_BITS_SHIFT       0x2
0089 #define MSPI_SPCR1_LSB              0x008
0090 #define MSPI_SPCR1_MSB              0x00c
0091 #define MSPI_NEWQP              0x010
0092 #define MSPI_ENDQP              0x014
0093 #define MSPI_SPCR2              0x018
0094 #define MSPI_MSPI_STATUS            0x020
0095 #define MSPI_CPTQP              0x024
0096 #define MSPI_SPCR3              0x028
0097 #define MSPI_REV                0x02c
0098 #define MSPI_TXRAM              0x040
0099 #define MSPI_RXRAM              0x0c0
0100 #define MSPI_CDRAM              0x140
0101 #define MSPI_WRITE_LOCK         0x180
0102 
0103 #define MSPI_MASTER_BIT         BIT(7)
0104 
0105 #define MSPI_NUM_CDRAM              16
0106 #define MSPI_CDRAM_OUTP             BIT(8)
0107 #define MSPI_CDRAM_CONT_BIT         BIT(7)
0108 #define MSPI_CDRAM_BITSE_BIT            BIT(6)
0109 #define MSPI_CDRAM_DT_BIT           BIT(5)
0110 #define MSPI_CDRAM_PCS              0xf
0111 
0112 #define MSPI_SPCR2_SPE              BIT(6)
0113 #define MSPI_SPCR2_CONT_AFTER_CMD       BIT(7)
0114 
0115 #define MSPI_SPCR3_FASTBR           BIT(0)
0116 #define MSPI_SPCR3_FASTDT           BIT(1)
0117 #define MSPI_SPCR3_SYSCLKSEL_MASK       GENMASK(11, 10)
0118 #define MSPI_SPCR3_SYSCLKSEL_27         (MSPI_SPCR3_SYSCLKSEL_MASK & \
0119                          ~(BIT(10) | BIT(11)))
0120 #define MSPI_SPCR3_SYSCLKSEL_108        (MSPI_SPCR3_SYSCLKSEL_MASK & \
0121                          BIT(11))
0122 #define MSPI_SPCR3_TXRXDAM_MASK         GENMASK(4, 2)
0123 #define MSPI_SPCR3_DAM_8BYTE            0
0124 #define MSPI_SPCR3_DAM_16BYTE           (BIT(2) | BIT(4))
0125 #define MSPI_SPCR3_DAM_32BYTE           (BIT(3) | BIT(5))
0126 #define MSPI_SPCR3_HALFDUPLEX           BIT(6)
0127 #define MSPI_SPCR3_HDOUTTYPE            BIT(7)
0128 #define MSPI_SPCR3_DATA_REG_SZ          BIT(8)
0129 #define MSPI_SPCR3_CPHARX           BIT(9)
0130 
0131 #define MSPI_MSPI_STATUS_SPIF           BIT(0)
0132 
0133 #define INTR_BASE_BIT_SHIFT         0x02
0134 #define INTR_COUNT              0x07
0135 
0136 #define NUM_CHIPSELECT              4
0137 #define QSPI_SPBR_MAX               255U
0138 #define MSPI_BASE_FREQ              27000000UL
0139 
0140 #define OPCODE_DIOR             0xBB
0141 #define OPCODE_QIOR             0xEB
0142 #define OPCODE_DIOR_4B              0xBC
0143 #define OPCODE_QIOR_4B              0xEC
0144 
0145 #define MAX_CMD_SIZE                6
0146 
0147 #define ADDR_4MB_MASK               GENMASK(22, 0)
0148 
0149 /* stop at end of transfer, no other reason */
0150 #define TRANS_STATUS_BREAK_NONE     0
0151 /* stop at end of spi_message */
0152 #define TRANS_STATUS_BREAK_EOM          1
0153 /* stop at end of spi_transfer if delay */
0154 #define TRANS_STATUS_BREAK_DELAY        2
0155 /* stop at end of spi_transfer if cs_change */
0156 #define TRANS_STATUS_BREAK_CS_CHANGE        4
0157 /* stop if we run out of bytes */
0158 #define TRANS_STATUS_BREAK_NO_BYTES     8
0159 
0160 /* events that make us stop filling TX slots */
0161 #define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM |     \
0162                    TRANS_STATUS_BREAK_DELAY |       \
0163                    TRANS_STATUS_BREAK_CS_CHANGE)
0164 
0165 /* events that make us deassert CS */
0166 #define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM |       \
0167                      TRANS_STATUS_BREAK_CS_CHANGE)
0168 
0169 /*
0170  * Used for writing and reading data in the right order
0171  * to TXRAM and RXRAM when used as 32-bit registers respectively
0172  */
0173 #define swap4bytes(__val) \
0174     ((((__val) >> 24) & 0x000000FF) | (((__val) >>  8) & 0x0000FF00) | \
0175      (((__val) <<  8) & 0x00FF0000) | (((__val) << 24) & 0xFF000000))
0176 
0177 struct bcm_qspi_parms {
0178     u32 speed_hz;
0179     u8 mode;
0180     u8 bits_per_word;
0181 };
0182 
0183 struct bcm_xfer_mode {
0184     bool flex_mode;
0185     unsigned int width;
0186     unsigned int addrlen;
0187     unsigned int hp;
0188 };
0189 
0190 enum base_type {
0191     MSPI,
0192     BSPI,
0193     CHIP_SELECT,
0194     BASEMAX,
0195 };
0196 
0197 enum irq_source {
0198     SINGLE_L2,
0199     MUXED_L1,
0200 };
0201 
0202 struct bcm_qspi_irq {
0203     const char *irq_name;
0204     const irq_handler_t irq_handler;
0205     int irq_source;
0206     u32 mask;
0207 };
0208 
0209 struct bcm_qspi_dev_id {
0210     const struct bcm_qspi_irq *irqp;
0211     void *dev;
0212 };
0213 
0214 
0215 struct qspi_trans {
0216     struct spi_transfer *trans;
0217     int byte;
0218     bool mspi_last_trans;
0219 };
0220 
0221 struct bcm_qspi {
0222     struct platform_device *pdev;
0223     struct spi_master *master;
0224     struct clk *clk;
0225     u32 base_clk;
0226     u32 max_speed_hz;
0227     void __iomem *base[BASEMAX];
0228 
0229     /* Some SoCs provide custom interrupt status register(s) */
0230     struct bcm_qspi_soc_intc    *soc_intc;
0231 
0232     struct bcm_qspi_parms last_parms;
0233     struct qspi_trans  trans_pos;
0234     int curr_cs;
0235     int bspi_maj_rev;
0236     int bspi_min_rev;
0237     int bspi_enabled;
0238     const struct spi_mem_op *bspi_rf_op;
0239     u32 bspi_rf_op_idx;
0240     u32 bspi_rf_op_len;
0241     u32 bspi_rf_op_status;
0242     struct bcm_xfer_mode xfer_mode;
0243     u32 s3_strap_override_ctrl;
0244     bool bspi_mode;
0245     bool big_endian;
0246     int num_irqs;
0247     struct bcm_qspi_dev_id *dev_ids;
0248     struct completion mspi_done;
0249     struct completion bspi_done;
0250     u8 mspi_maj_rev;
0251     u8 mspi_min_rev;
0252     bool mspi_spcr3_sysclk;
0253 };
0254 
0255 static inline bool has_bspi(struct bcm_qspi *qspi)
0256 {
0257     return qspi->bspi_mode;
0258 }
0259 
0260 /* hardware supports spcr3 and fast baud-rate  */
0261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
0262 {
0263     if (!has_bspi(qspi) &&
0264         ((qspi->mspi_maj_rev >= 1) &&
0265          (qspi->mspi_min_rev >= 5)))
0266         return true;
0267 
0268     return false;
0269 }
0270 
0271 /* hardware supports sys clk 108Mhz  */
0272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
0273 {
0274     if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
0275         ((qspi->mspi_maj_rev >= 1) &&
0276          (qspi->mspi_min_rev >= 6))))
0277         return true;
0278 
0279     return false;
0280 }
0281 
0282 static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
0283 {
0284     if (bcm_qspi_has_fastbr(qspi))
0285         return (bcm_qspi_has_sysclk_108(qspi) ? 4 : 1);
0286     else
0287         return 8;
0288 }
0289 
0290 static u32 bcm_qspi_calc_spbr(u32 clk_speed_hz,
0291                   const struct bcm_qspi_parms *xp)
0292 {
0293     u32 spbr = 0;
0294 
0295     /* SPBR = System Clock/(2 * SCK Baud Rate) */
0296     if (xp->speed_hz)
0297         spbr = clk_speed_hz / (xp->speed_hz * 2);
0298 
0299     return spbr;
0300 }
0301 
0302 /* Read qspi controller register*/
0303 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
0304                 unsigned int offset)
0305 {
0306     return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
0307 }
0308 
0309 /* Write qspi controller register*/
0310 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
0311                   unsigned int offset, unsigned int data)
0312 {
0313     bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
0314 }
0315 
0316 /* BSPI helpers */
0317 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
0318 {
0319     int i;
0320 
0321     /* this should normally finish within 10us */
0322     for (i = 0; i < 1000; i++) {
0323         if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
0324             return 0;
0325         udelay(1);
0326     }
0327     dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
0328     return -EIO;
0329 }
0330 
0331 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
0332 {
0333     if (qspi->bspi_maj_rev < 4)
0334         return true;
0335     return false;
0336 }
0337 
0338 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
0339 {
0340     bcm_qspi_bspi_busy_poll(qspi);
0341     /* Force rising edge for the b0/b1 'flush' field */
0342     bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
0343     bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
0344     bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
0345     bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
0346 }
0347 
0348 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
0349 {
0350     return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
0351                 BSPI_RAF_STATUS_FIFO_EMPTY_MASK);
0352 }
0353 
0354 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
0355 {
0356     u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
0357 
0358     /* BSPI v3 LR is LE only, convert data to host endianness */
0359     if (bcm_qspi_bspi_ver_three(qspi))
0360         data = le32_to_cpu(data);
0361 
0362     return data;
0363 }
0364 
0365 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
0366 {
0367     bcm_qspi_bspi_busy_poll(qspi);
0368     bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
0369                BSPI_RAF_CTRL_START_MASK);
0370 }
0371 
0372 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
0373 {
0374     bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
0375                BSPI_RAF_CTRL_CLEAR_MASK);
0376     bcm_qspi_bspi_flush_prefetch_buffers(qspi);
0377 }
0378 
0379 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
0380 {
0381     u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
0382     u32 data = 0;
0383 
0384     dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
0385         qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
0386     while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
0387         data = bcm_qspi_bspi_lr_read_fifo(qspi);
0388         if (likely(qspi->bspi_rf_op_len >= 4) &&
0389             IS_ALIGNED((uintptr_t)buf, 4)) {
0390             buf[qspi->bspi_rf_op_idx++] = data;
0391             qspi->bspi_rf_op_len -= 4;
0392         } else {
0393             /* Read out remaining bytes, make sure*/
0394             u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
0395 
0396             data = cpu_to_le32(data);
0397             while (qspi->bspi_rf_op_len) {
0398                 *cbuf++ = (u8)data;
0399                 data >>= 8;
0400                 qspi->bspi_rf_op_len--;
0401             }
0402         }
0403     }
0404 }
0405 
0406 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
0407                       int bpp, int bpc, int flex_mode)
0408 {
0409     bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
0410     bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
0411     bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
0412     bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
0413     bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
0414 }
0415 
0416 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
0417                        const struct spi_mem_op *op, int hp)
0418 {
0419     int bpc = 0, bpp = 0;
0420     u8 command = op->cmd.opcode;
0421     int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
0422     int addrlen = op->addr.nbytes;
0423     int flex_mode = 1;
0424 
0425     dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
0426         width, addrlen, hp);
0427 
0428     if (addrlen == BSPI_ADDRLEN_4BYTES)
0429         bpp = BSPI_BPP_ADDR_SELECT_MASK;
0430 
0431     if (op->dummy.nbytes)
0432         bpp |= (op->dummy.nbytes * 8) / op->dummy.buswidth;
0433 
0434     switch (width) {
0435     case SPI_NBITS_SINGLE:
0436         if (addrlen == BSPI_ADDRLEN_3BYTES)
0437             /* default mode, does not need flex_cmd */
0438             flex_mode = 0;
0439         break;
0440     case SPI_NBITS_DUAL:
0441         bpc = 0x00000001;
0442         if (hp) {
0443             bpc |= 0x00010100; /* address and mode are 2-bit */
0444             bpp = BSPI_BPP_MODE_SELECT_MASK;
0445         }
0446         break;
0447     case SPI_NBITS_QUAD:
0448         bpc = 0x00000002;
0449         if (hp) {
0450             bpc |= 0x00020200; /* address and mode are 4-bit */
0451             bpp |= BSPI_BPP_MODE_SELECT_MASK;
0452         }
0453         break;
0454     default:
0455         return -EINVAL;
0456     }
0457 
0458     bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
0459 
0460     return 0;
0461 }
0462 
0463 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
0464                       const struct spi_mem_op *op, int hp)
0465 {
0466     int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
0467     int addrlen = op->addr.nbytes;
0468     u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
0469 
0470     dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
0471         width, addrlen, hp);
0472 
0473     switch (width) {
0474     case SPI_NBITS_SINGLE:
0475         /* clear quad/dual mode */
0476         data &= ~(BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD |
0477               BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL);
0478         break;
0479     case SPI_NBITS_QUAD:
0480         /* clear dual mode and set quad mode */
0481         data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
0482         data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
0483         break;
0484     case SPI_NBITS_DUAL:
0485         /* clear quad mode set dual mode */
0486         data &= ~BSPI_STRAP_OVERRIDE_CTRL_DATA_QUAD;
0487         data |= BSPI_STRAP_OVERRIDE_CTRL_DATA_DUAL;
0488         break;
0489     default:
0490         return -EINVAL;
0491     }
0492 
0493     if (addrlen == BSPI_ADDRLEN_4BYTES)
0494         /* set 4byte mode*/
0495         data |= BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
0496     else
0497         /* clear 4 byte mode */
0498         data &= ~BSPI_STRAP_OVERRIDE_CTRL_ADDR_4BYTE;
0499 
0500     /* set the override mode */
0501     data |= BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
0502     bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
0503     bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
0504 
0505     return 0;
0506 }
0507 
0508 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
0509                   const struct spi_mem_op *op, int hp)
0510 {
0511     int error = 0;
0512     int width = op->data.buswidth ? op->data.buswidth : SPI_NBITS_SINGLE;
0513     int addrlen = op->addr.nbytes;
0514 
0515     /* default mode */
0516     qspi->xfer_mode.flex_mode = true;
0517 
0518     if (!bcm_qspi_bspi_ver_three(qspi)) {
0519         u32 val, mask;
0520 
0521         val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
0522         mask = BSPI_STRAP_OVERRIDE_CTRL_OVERRIDE;
0523         if (val & mask || qspi->s3_strap_override_ctrl & mask) {
0524             qspi->xfer_mode.flex_mode = false;
0525             bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
0526             error = bcm_qspi_bspi_set_override(qspi, op, hp);
0527         }
0528     }
0529 
0530     if (qspi->xfer_mode.flex_mode)
0531         error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
0532 
0533     if (error) {
0534         dev_warn(&qspi->pdev->dev,
0535              "INVALID COMBINATION: width=%d addrlen=%d hp=%d\n",
0536              width, addrlen, hp);
0537     } else if (qspi->xfer_mode.width != width ||
0538            qspi->xfer_mode.addrlen != addrlen ||
0539            qspi->xfer_mode.hp != hp) {
0540         qspi->xfer_mode.width = width;
0541         qspi->xfer_mode.addrlen = addrlen;
0542         qspi->xfer_mode.hp = hp;
0543         dev_dbg(&qspi->pdev->dev,
0544             "cs:%d %d-lane output, %d-byte address%s\n",
0545             qspi->curr_cs,
0546             qspi->xfer_mode.width,
0547             qspi->xfer_mode.addrlen,
0548             qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
0549     }
0550 
0551     return error;
0552 }
0553 
0554 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
0555 {
0556     if (!has_bspi(qspi))
0557         return;
0558 
0559     qspi->bspi_enabled = 1;
0560     if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
0561         return;
0562 
0563     bcm_qspi_bspi_flush_prefetch_buffers(qspi);
0564     udelay(1);
0565     bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
0566     udelay(1);
0567 }
0568 
0569 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
0570 {
0571     if (!has_bspi(qspi))
0572         return;
0573 
0574     qspi->bspi_enabled = 0;
0575     if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
0576         return;
0577 
0578     bcm_qspi_bspi_busy_poll(qspi);
0579     bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
0580     udelay(1);
0581 }
0582 
0583 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
0584 {
0585     u32 rd = 0;
0586     u32 wr = 0;
0587 
0588     if (cs >= 0 && qspi->base[CHIP_SELECT]) {
0589         rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
0590         wr = (rd & ~0xff) | (1 << cs);
0591         if (rd == wr)
0592             return;
0593         bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
0594         usleep_range(10, 20);
0595     }
0596 
0597     dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
0598     qspi->curr_cs = cs;
0599 }
0600 
0601 static bool bcmspi_parms_did_change(const struct bcm_qspi_parms * const cur,
0602                     const struct bcm_qspi_parms * const prev)
0603 {
0604     return (cur->speed_hz != prev->speed_hz) ||
0605         (cur->mode != prev->mode) ||
0606         (cur->bits_per_word != prev->bits_per_word);
0607 }
0608 
0609 
0610 /* MSPI helpers */
0611 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
0612                   const struct bcm_qspi_parms *xp)
0613 {
0614     u32 spcr, spbr = 0;
0615 
0616     if (!bcmspi_parms_did_change(xp, &qspi->last_parms))
0617         return;
0618 
0619     if (!qspi->mspi_maj_rev)
0620         /* legacy controller */
0621         spcr = MSPI_MASTER_BIT;
0622     else
0623         spcr = 0;
0624 
0625     /*
0626      * Bits per transfer.  BITS determines the number of data bits
0627      * transferred if the command control bit (BITSE of a
0628      * CDRAM Register) is equal to 1.
0629      * If CDRAM BITSE is equal to 0, 8 data bits are transferred
0630      * regardless
0631      */
0632     if (xp->bits_per_word != 16 && xp->bits_per_word != 64)
0633         spcr |= xp->bits_per_word << MSPI_SPCR0_MSB_BITS_SHIFT;
0634 
0635     spcr |= xp->mode & (MSPI_SPCR0_MSB_CPHA | MSPI_SPCR0_MSB_CPOL);
0636     bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
0637 
0638     if (bcm_qspi_has_fastbr(qspi)) {
0639         spcr = 0;
0640 
0641         /* enable fastbr */
0642         spcr |= MSPI_SPCR3_FASTBR;
0643 
0644         if (xp->mode & SPI_3WIRE)
0645             spcr |= MSPI_SPCR3_HALFDUPLEX |  MSPI_SPCR3_HDOUTTYPE;
0646 
0647         if (bcm_qspi_has_sysclk_108(qspi)) {
0648             /* check requested baud rate before moving to 108Mhz */
0649             spbr = bcm_qspi_calc_spbr(MSPI_BASE_FREQ * 4, xp);
0650             if (spbr > QSPI_SPBR_MAX) {
0651                 /* use SYSCLK_27Mhz for slower baud rates */
0652                 spcr &= ~MSPI_SPCR3_SYSCLKSEL_MASK;
0653                 qspi->base_clk = MSPI_BASE_FREQ;
0654             } else {
0655                 /* SYSCLK_108Mhz */
0656                 spcr |= MSPI_SPCR3_SYSCLKSEL_108;
0657                 qspi->base_clk = MSPI_BASE_FREQ * 4;
0658             }
0659         }
0660 
0661         if (xp->bits_per_word > 16) {
0662             /* data_reg_size 1 (64bit) */
0663             spcr |= MSPI_SPCR3_DATA_REG_SZ;
0664             /* TxRx RAM data access mode 2 for 32B and set fastdt */
0665             spcr |= MSPI_SPCR3_DAM_32BYTE  | MSPI_SPCR3_FASTDT;
0666             /*
0667              *  Set length of delay after transfer
0668              *  DTL from 0(256) to 1
0669              */
0670             bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1);
0671         } else {
0672             /* data_reg_size[8] = 0 */
0673             spcr &= ~(MSPI_SPCR3_DATA_REG_SZ);
0674 
0675             /*
0676              * TxRx RAM access mode 8B
0677              * and disable fastdt
0678              */
0679             spcr &= ~(MSPI_SPCR3_DAM_32BYTE);
0680         }
0681         bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
0682     }
0683 
0684     /* SCK Baud Rate = System Clock/(2 * SPBR) */
0685     qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
0686     spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp);
0687     spbr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
0688     bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
0689 
0690     qspi->last_parms = *xp;
0691 }
0692 
0693 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
0694                   struct spi_device *spi,
0695                   struct spi_transfer *trans)
0696 {
0697     struct bcm_qspi_parms xp;
0698 
0699     xp.speed_hz = trans->speed_hz;
0700     xp.bits_per_word = trans->bits_per_word;
0701     xp.mode = spi->mode;
0702 
0703     bcm_qspi_hw_set_parms(qspi, &xp);
0704 }
0705 
0706 static int bcm_qspi_setup(struct spi_device *spi)
0707 {
0708     struct bcm_qspi_parms *xp;
0709 
0710     if (spi->bits_per_word > 64)
0711         return -EINVAL;
0712 
0713     xp = spi_get_ctldata(spi);
0714     if (!xp) {
0715         xp = kzalloc(sizeof(*xp), GFP_KERNEL);
0716         if (!xp)
0717             return -ENOMEM;
0718         spi_set_ctldata(spi, xp);
0719     }
0720     xp->speed_hz = spi->max_speed_hz;
0721     xp->mode = spi->mode;
0722 
0723     if (spi->bits_per_word)
0724         xp->bits_per_word = spi->bits_per_word;
0725     else
0726         xp->bits_per_word = 8;
0727 
0728     return 0;
0729 }
0730 
0731 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
0732                        struct qspi_trans *qt)
0733 {
0734     if (qt->mspi_last_trans &&
0735         spi_transfer_is_last(qspi->master, qt->trans))
0736         return true;
0737     else
0738         return false;
0739 }
0740 
0741 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
0742                     struct qspi_trans *qt, int flags)
0743 {
0744     int ret = TRANS_STATUS_BREAK_NONE;
0745 
0746     /* count the last transferred bytes */
0747     if (qt->trans->bits_per_word <= 8)
0748         qt->byte++;
0749     else if (qt->trans->bits_per_word <= 16)
0750         qt->byte += 2;
0751     else if (qt->trans->bits_per_word <= 32)
0752         qt->byte += 4;
0753     else if (qt->trans->bits_per_word <= 64)
0754         qt->byte += 8;
0755 
0756     if (qt->byte >= qt->trans->len) {
0757         /* we're at the end of the spi_transfer */
0758         /* in TX mode, need to pause for a delay or CS change */
0759         if (qt->trans->delay.value &&
0760             (flags & TRANS_STATUS_BREAK_DELAY))
0761             ret |= TRANS_STATUS_BREAK_DELAY;
0762         if (qt->trans->cs_change &&
0763             (flags & TRANS_STATUS_BREAK_CS_CHANGE))
0764             ret |= TRANS_STATUS_BREAK_CS_CHANGE;
0765 
0766         if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
0767             ret |= TRANS_STATUS_BREAK_EOM;
0768         else
0769             ret |= TRANS_STATUS_BREAK_NO_BYTES;
0770 
0771         qt->trans = NULL;
0772     }
0773 
0774     dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
0775         qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
0776     return ret;
0777 }
0778 
0779 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
0780 {
0781     u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
0782 
0783     /* mask out reserved bits */
0784     return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
0785 }
0786 
0787 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
0788 {
0789     u32 reg_offset = MSPI_RXRAM;
0790     u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
0791     u32 msb_offset = reg_offset + (slot << 3);
0792 
0793     return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
0794         ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
0795 }
0796 
0797 static inline u32 read_rxram_slot_u32(struct bcm_qspi *qspi, int slot)
0798 {
0799     u32 reg_offset = MSPI_RXRAM;
0800     u32 offset = reg_offset + (slot << 3);
0801     u32 val;
0802 
0803     val = bcm_qspi_read(qspi, MSPI, offset);
0804     val = swap4bytes(val);
0805 
0806     return val;
0807 }
0808 
0809 static inline u64 read_rxram_slot_u64(struct bcm_qspi *qspi, int slot)
0810 {
0811     u32 reg_offset = MSPI_RXRAM;
0812     u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
0813     u32 msb_offset = reg_offset + (slot << 3);
0814     u32 msb, lsb;
0815 
0816     msb = bcm_qspi_read(qspi, MSPI, msb_offset);
0817     msb = swap4bytes(msb);
0818     lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
0819     lsb = swap4bytes(lsb);
0820 
0821     return ((u64)msb << 32 | lsb);
0822 }
0823 
0824 static void read_from_hw(struct bcm_qspi *qspi, int slots)
0825 {
0826     struct qspi_trans tp;
0827     int slot;
0828 
0829     bcm_qspi_disable_bspi(qspi);
0830 
0831     if (slots > MSPI_NUM_CDRAM) {
0832         /* should never happen */
0833         dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
0834         return;
0835     }
0836 
0837     tp = qspi->trans_pos;
0838 
0839     for (slot = 0; slot < slots; slot++) {
0840         if (tp.trans->bits_per_word <= 8) {
0841             u8 *buf = tp.trans->rx_buf;
0842 
0843             if (buf)
0844                 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
0845             dev_dbg(&qspi->pdev->dev, "RD %02x\n",
0846                 buf ? buf[tp.byte] : 0x0);
0847         } else if (tp.trans->bits_per_word <= 16) {
0848             u16 *buf = tp.trans->rx_buf;
0849 
0850             if (buf)
0851                 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
0852                                       slot);
0853             dev_dbg(&qspi->pdev->dev, "RD %04x\n",
0854                 buf ? buf[tp.byte / 2] : 0x0);
0855         } else if (tp.trans->bits_per_word <= 32) {
0856             u32 *buf = tp.trans->rx_buf;
0857 
0858             if (buf)
0859                 buf[tp.byte / 4] = read_rxram_slot_u32(qspi,
0860                                       slot);
0861             dev_dbg(&qspi->pdev->dev, "RD %08x\n",
0862                 buf ? buf[tp.byte / 4] : 0x0);
0863 
0864         } else if (tp.trans->bits_per_word <= 64) {
0865             u64 *buf = tp.trans->rx_buf;
0866 
0867             if (buf)
0868                 buf[tp.byte / 8] = read_rxram_slot_u64(qspi,
0869                                       slot);
0870             dev_dbg(&qspi->pdev->dev, "RD %llx\n",
0871                 buf ? buf[tp.byte / 8] : 0x0);
0872 
0873 
0874         }
0875 
0876         update_qspi_trans_byte_count(qspi, &tp,
0877                          TRANS_STATUS_BREAK_NONE);
0878     }
0879 
0880     qspi->trans_pos = tp;
0881 }
0882 
0883 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
0884                        u8 val)
0885 {
0886     u32 reg_offset = MSPI_TXRAM + (slot << 3);
0887 
0888     /* mask out reserved bits */
0889     bcm_qspi_write(qspi, MSPI, reg_offset, val);
0890 }
0891 
0892 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
0893                     u16 val)
0894 {
0895     u32 reg_offset = MSPI_TXRAM;
0896     u32 msb_offset = reg_offset + (slot << 3);
0897     u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
0898 
0899     bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
0900     bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
0901 }
0902 
0903 static inline void write_txram_slot_u32(struct bcm_qspi *qspi, int slot,
0904                     u32 val)
0905 {
0906     u32 reg_offset = MSPI_TXRAM;
0907     u32 msb_offset = reg_offset + (slot << 3);
0908 
0909     bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val));
0910 }
0911 
0912 static inline void write_txram_slot_u64(struct bcm_qspi *qspi, int slot,
0913                     u64 val)
0914 {
0915     u32 reg_offset = MSPI_TXRAM;
0916     u32 msb_offset = reg_offset + (slot << 3);
0917     u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
0918     u32 msb = upper_32_bits(val);
0919     u32 lsb = lower_32_bits(val);
0920 
0921     bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb));
0922     bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb));
0923 }
0924 
0925 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
0926 {
0927     return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
0928 }
0929 
0930 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
0931 {
0932     bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
0933 }
0934 
0935 /* Return number of slots written */
0936 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
0937 {
0938     struct qspi_trans tp;
0939     int slot = 0, tstatus = 0;
0940     u32 mspi_cdram = 0;
0941 
0942     bcm_qspi_disable_bspi(qspi);
0943     tp = qspi->trans_pos;
0944     bcm_qspi_update_parms(qspi, spi, tp.trans);
0945 
0946     /* Run until end of transfer or reached the max data */
0947     while (!tstatus && slot < MSPI_NUM_CDRAM) {
0948         mspi_cdram = MSPI_CDRAM_CONT_BIT;
0949         if (tp.trans->bits_per_word <= 8) {
0950             const u8 *buf = tp.trans->tx_buf;
0951             u8 val = buf ? buf[tp.byte] : 0x00;
0952 
0953             write_txram_slot_u8(qspi, slot, val);
0954             dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
0955         } else if (tp.trans->bits_per_word <= 16) {
0956             const u16 *buf = tp.trans->tx_buf;
0957             u16 val = buf ? buf[tp.byte / 2] : 0x0000;
0958 
0959             write_txram_slot_u16(qspi, slot, val);
0960             dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
0961         } else if (tp.trans->bits_per_word <= 32) {
0962             const u32 *buf = tp.trans->tx_buf;
0963             u32 val = buf ? buf[tp.byte/4] : 0x0;
0964 
0965             write_txram_slot_u32(qspi, slot, val);
0966             dev_dbg(&qspi->pdev->dev, "WR %08x\n", val);
0967         } else if (tp.trans->bits_per_word <= 64) {
0968             const u64 *buf = tp.trans->tx_buf;
0969             u64 val = (buf ? buf[tp.byte/8] : 0x0);
0970 
0971             /* use the length of delay from SPCR1_LSB */
0972             if (bcm_qspi_has_fastbr(qspi))
0973                 mspi_cdram |= MSPI_CDRAM_DT_BIT;
0974 
0975             write_txram_slot_u64(qspi, slot, val);
0976             dev_dbg(&qspi->pdev->dev, "WR %llx\n", val);
0977         }
0978 
0979         mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
0980                    MSPI_CDRAM_BITSE_BIT);
0981 
0982         /* set 3wrire halfduplex mode data from master to slave */
0983         if ((spi->mode & SPI_3WIRE) && tp.trans->tx_buf)
0984             mspi_cdram |= MSPI_CDRAM_OUTP;
0985 
0986         if (has_bspi(qspi))
0987             mspi_cdram &= ~1;
0988         else
0989             mspi_cdram |= (~(1 << spi->chip_select) &
0990                        MSPI_CDRAM_PCS);
0991 
0992         write_cdram_slot(qspi, slot, mspi_cdram);
0993 
0994         tstatus = update_qspi_trans_byte_count(qspi, &tp,
0995                                TRANS_STATUS_BREAK_TX);
0996         slot++;
0997     }
0998 
0999     if (!slot) {
1000         dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
1001         goto done;
1002     }
1003 
1004     dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
1005     bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1006     bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
1007 
1008     /*
1009      *  case 1) EOM =1, cs_change =0: SSb inactive
1010      *  case 2) EOM =1, cs_change =1: SSb stay active
1011      *  case 3) EOM =0, cs_change =0: SSb stay active
1012      *  case 4) EOM =0, cs_change =1: SSb inactive
1013      */
1014     if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
1015          == TRANS_STATUS_BREAK_CS_CHANGE) ||
1016         ((tstatus & TRANS_STATUS_BREAK_DESELECT)
1017          == TRANS_STATUS_BREAK_EOM)) {
1018         mspi_cdram = read_cdram_slot(qspi, slot - 1) &
1019             ~MSPI_CDRAM_CONT_BIT;
1020         write_cdram_slot(qspi, slot - 1, mspi_cdram);
1021     }
1022 
1023     if (has_bspi(qspi))
1024         bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
1025 
1026     /* Must flush previous writes before starting MSPI operation */
1027     mb();
1028     /* Set cont | spe | spifie */
1029     bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
1030 
1031 done:
1032     return slot;
1033 }
1034 
1035 static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
1036                      const struct spi_mem_op *op)
1037 {
1038     struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
1039     u32 addr = 0, len, rdlen, len_words, from = 0;
1040     int ret = 0;
1041     unsigned long timeo = msecs_to_jiffies(100);
1042     struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1043 
1044     if (bcm_qspi_bspi_ver_three(qspi))
1045         if (op->addr.nbytes == BSPI_ADDRLEN_4BYTES)
1046             return -EIO;
1047 
1048     from = op->addr.val;
1049     if (!spi->cs_gpiod)
1050         bcm_qspi_chip_select(qspi, spi->chip_select);
1051     bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1052 
1053     /*
1054      * when using flex mode we need to send
1055      * the upper address byte to bspi
1056      */
1057     if (!bcm_qspi_bspi_ver_three(qspi)) {
1058         addr = from & 0xff000000;
1059         bcm_qspi_write(qspi, BSPI,
1060                    BSPI_BSPI_FLASH_UPPER_ADDR_BYTE, addr);
1061     }
1062 
1063     if (!qspi->xfer_mode.flex_mode)
1064         addr = from;
1065     else
1066         addr = from & 0x00ffffff;
1067 
1068     if (bcm_qspi_bspi_ver_three(qspi) == true)
1069         addr = (addr + 0xc00000) & 0xffffff;
1070 
1071     /*
1072      * read into the entire buffer by breaking the reads
1073      * into RAF buffer read lengths
1074      */
1075     len = op->data.nbytes;
1076     qspi->bspi_rf_op_idx = 0;
1077 
1078     do {
1079         if (len > BSPI_READ_LENGTH)
1080             rdlen = BSPI_READ_LENGTH;
1081         else
1082             rdlen = len;
1083 
1084         reinit_completion(&qspi->bspi_done);
1085         bcm_qspi_enable_bspi(qspi);
1086         len_words = (rdlen + 3) >> 2;
1087         qspi->bspi_rf_op = op;
1088         qspi->bspi_rf_op_status = 0;
1089         qspi->bspi_rf_op_len = rdlen;
1090         dev_dbg(&qspi->pdev->dev,
1091             "bspi xfr addr 0x%x len 0x%x", addr, rdlen);
1092         bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
1093         bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
1094         bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
1095         if (qspi->soc_intc) {
1096             /*
1097              * clear soc MSPI and BSPI interrupts and enable
1098              * BSPI interrupts.
1099              */
1100             soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_BSPI_DONE);
1101             soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE, true);
1102         }
1103 
1104         /* Must flush previous writes before starting BSPI operation */
1105         mb();
1106         bcm_qspi_bspi_lr_start(qspi);
1107         if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
1108             dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
1109             ret = -ETIMEDOUT;
1110             break;
1111         }
1112 
1113         /* set msg return length */
1114         addr += rdlen;
1115         len -= rdlen;
1116     } while (len);
1117 
1118     return ret;
1119 }
1120 
1121 static int bcm_qspi_transfer_one(struct spi_master *master,
1122                  struct spi_device *spi,
1123                  struct spi_transfer *trans)
1124 {
1125     struct bcm_qspi *qspi = spi_master_get_devdata(master);
1126     int slots;
1127     unsigned long timeo = msecs_to_jiffies(100);
1128 
1129     if (!spi->cs_gpiod)
1130         bcm_qspi_chip_select(qspi, spi->chip_select);
1131     qspi->trans_pos.trans = trans;
1132     qspi->trans_pos.byte = 0;
1133 
1134     while (qspi->trans_pos.byte < trans->len) {
1135         reinit_completion(&qspi->mspi_done);
1136 
1137         slots = write_to_hw(qspi, spi);
1138         if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
1139             dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
1140             return -ETIMEDOUT;
1141         }
1142 
1143         read_from_hw(qspi, slots);
1144     }
1145     bcm_qspi_enable_bspi(qspi);
1146 
1147     return 0;
1148 }
1149 
1150 static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
1151                      const struct spi_mem_op *op)
1152 {
1153     struct spi_master *master = spi->master;
1154     struct bcm_qspi *qspi = spi_master_get_devdata(master);
1155     struct spi_transfer t[2];
1156     u8 cmd[6] = { };
1157     int ret, i;
1158 
1159     memset(cmd, 0, sizeof(cmd));
1160     memset(t, 0, sizeof(t));
1161 
1162     /* tx */
1163     /* opcode is in cmd[0] */
1164     cmd[0] = op->cmd.opcode;
1165     for (i = 0; i < op->addr.nbytes; i++)
1166         cmd[1 + i] = op->addr.val >> (8 * (op->addr.nbytes - i - 1));
1167 
1168     t[0].tx_buf = cmd;
1169     t[0].len = op->addr.nbytes + op->dummy.nbytes + 1;
1170     t[0].bits_per_word = spi->bits_per_word;
1171     t[0].tx_nbits = op->cmd.buswidth;
1172     /* lets mspi know that this is not last transfer */
1173     qspi->trans_pos.mspi_last_trans = false;
1174     ret = bcm_qspi_transfer_one(master, spi, &t[0]);
1175 
1176     /* rx */
1177     qspi->trans_pos.mspi_last_trans = true;
1178     if (!ret) {
1179         /* rx */
1180         t[1].rx_buf = op->data.buf.in;
1181         t[1].len = op->data.nbytes;
1182         t[1].rx_nbits =  op->data.buswidth;
1183         t[1].bits_per_word = spi->bits_per_word;
1184         ret = bcm_qspi_transfer_one(master, spi, &t[1]);
1185     }
1186 
1187     return ret;
1188 }
1189 
1190 static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
1191                 const struct spi_mem_op *op)
1192 {
1193     struct spi_device *spi = mem->spi;
1194     struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
1195     int ret = 0;
1196     bool mspi_read = false;
1197     u32 addr = 0, len;
1198     u_char *buf;
1199 
1200     if (!op->data.nbytes || !op->addr.nbytes || op->addr.nbytes > 4 ||
1201         op->data.dir != SPI_MEM_DATA_IN)
1202         return -ENOTSUPP;
1203 
1204     buf = op->data.buf.in;
1205     addr = op->addr.val;
1206     len = op->data.nbytes;
1207 
1208     if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
1209         /*
1210          * The address coming into this function is a raw flash offset.
1211          * But for BSPI <= V3, we need to convert it to a remapped BSPI
1212          * address. If it crosses a 4MB boundary, just revert back to
1213          * using MSPI.
1214          */
1215         addr = (addr + 0xc00000) & 0xffffff;
1216 
1217         if ((~ADDR_4MB_MASK & addr) ^
1218             (~ADDR_4MB_MASK & (addr + len - 1)))
1219             mspi_read = true;
1220     }
1221 
1222     /* non-aligned and very short transfers are handled by MSPI */
1223     if (!IS_ALIGNED((uintptr_t)addr, 4) || !IS_ALIGNED((uintptr_t)buf, 4) ||
1224         len < 4)
1225         mspi_read = true;
1226 
1227     if (!has_bspi(qspi) || mspi_read)
1228         return bcm_qspi_mspi_exec_mem_op(spi, op);
1229 
1230     ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
1231 
1232     if (!ret)
1233         ret = bcm_qspi_bspi_exec_mem_op(spi, op);
1234 
1235     return ret;
1236 }
1237 
1238 static void bcm_qspi_cleanup(struct spi_device *spi)
1239 {
1240     struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
1241 
1242     kfree(xp);
1243 }
1244 
1245 static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
1246 {
1247     struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1248     struct bcm_qspi *qspi = qspi_dev_id->dev;
1249     u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1250 
1251     if (status & MSPI_MSPI_STATUS_SPIF) {
1252         struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1253         /* clear interrupt */
1254         status &= ~MSPI_MSPI_STATUS_SPIF;
1255         bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1256         if (qspi->soc_intc)
1257             soc_intc->bcm_qspi_int_ack(soc_intc, MSPI_DONE);
1258         complete(&qspi->mspi_done);
1259         return IRQ_HANDLED;
1260     }
1261 
1262     return IRQ_NONE;
1263 }
1264 
1265 static irqreturn_t bcm_qspi_bspi_lr_l2_isr(int irq, void *dev_id)
1266 {
1267     struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1268     struct bcm_qspi *qspi = qspi_dev_id->dev;
1269     struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1270     u32 status = qspi_dev_id->irqp->mask;
1271 
1272     if (qspi->bspi_enabled && qspi->bspi_rf_op) {
1273         bcm_qspi_bspi_lr_data_read(qspi);
1274         if (qspi->bspi_rf_op_len == 0) {
1275             qspi->bspi_rf_op = NULL;
1276             if (qspi->soc_intc) {
1277                 /* disable soc BSPI interrupt */
1278                 soc_intc->bcm_qspi_int_set(soc_intc, BSPI_DONE,
1279                                false);
1280                 /* indicate done */
1281                 status = INTR_BSPI_LR_SESSION_DONE_MASK;
1282             }
1283 
1284             if (qspi->bspi_rf_op_status)
1285                 bcm_qspi_bspi_lr_clear(qspi);
1286             else
1287                 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1288         }
1289 
1290         if (qspi->soc_intc)
1291             /* clear soc BSPI interrupt */
1292             soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_DONE);
1293     }
1294 
1295     status &= INTR_BSPI_LR_SESSION_DONE_MASK;
1296     if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
1297         complete(&qspi->bspi_done);
1298 
1299     return IRQ_HANDLED;
1300 }
1301 
1302 static irqreturn_t bcm_qspi_bspi_lr_err_l2_isr(int irq, void *dev_id)
1303 {
1304     struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1305     struct bcm_qspi *qspi = qspi_dev_id->dev;
1306     struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1307 
1308     dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1309     qspi->bspi_rf_op_status = -EIO;
1310     if (qspi->soc_intc)
1311         /* clear soc interrupt */
1312         soc_intc->bcm_qspi_int_ack(soc_intc, BSPI_ERR);
1313 
1314     complete(&qspi->bspi_done);
1315     return IRQ_HANDLED;
1316 }
1317 
1318 static irqreturn_t bcm_qspi_l1_isr(int irq, void *dev_id)
1319 {
1320     struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
1321     struct bcm_qspi *qspi = qspi_dev_id->dev;
1322     struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1323     irqreturn_t ret = IRQ_NONE;
1324 
1325     if (soc_intc) {
1326         u32 status = soc_intc->bcm_qspi_get_int_status(soc_intc);
1327 
1328         if (status & MSPI_DONE)
1329             ret = bcm_qspi_mspi_l2_isr(irq, dev_id);
1330         else if (status & BSPI_DONE)
1331             ret = bcm_qspi_bspi_lr_l2_isr(irq, dev_id);
1332         else if (status & BSPI_ERR)
1333             ret = bcm_qspi_bspi_lr_err_l2_isr(irq, dev_id);
1334     }
1335 
1336     return ret;
1337 }
1338 
1339 static const struct bcm_qspi_irq qspi_irq_tab[] = {
1340     {
1341         .irq_name = "spi_lr_fullness_reached",
1342         .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1343         .mask = INTR_BSPI_LR_FULLNESS_REACHED_MASK,
1344     },
1345     {
1346         .irq_name = "spi_lr_session_aborted",
1347         .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1348         .mask = INTR_BSPI_LR_SESSION_ABORTED_MASK,
1349     },
1350     {
1351         .irq_name = "spi_lr_impatient",
1352         .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1353         .mask = INTR_BSPI_LR_IMPATIENT_MASK,
1354     },
1355     {
1356         .irq_name = "spi_lr_session_done",
1357         .irq_handler = bcm_qspi_bspi_lr_l2_isr,
1358         .mask = INTR_BSPI_LR_SESSION_DONE_MASK,
1359     },
1360 #ifdef QSPI_INT_DEBUG
1361     /* this interrupt is for debug purposes only, dont request irq */
1362     {
1363         .irq_name = "spi_lr_overread",
1364         .irq_handler = bcm_qspi_bspi_lr_err_l2_isr,
1365         .mask = INTR_BSPI_LR_OVERREAD_MASK,
1366     },
1367 #endif
1368     {
1369         .irq_name = "mspi_done",
1370         .irq_handler = bcm_qspi_mspi_l2_isr,
1371         .mask = INTR_MSPI_DONE_MASK,
1372     },
1373     {
1374         .irq_name = "mspi_halted",
1375         .irq_handler = bcm_qspi_mspi_l2_isr,
1376         .mask = INTR_MSPI_HALTED_MASK,
1377     },
1378     {
1379         /* single muxed L1 interrupt source */
1380         .irq_name = "spi_l1_intr",
1381         .irq_handler = bcm_qspi_l1_isr,
1382         .irq_source = MUXED_L1,
1383         .mask = QSPI_INTERRUPTS_ALL,
1384     },
1385 };
1386 
1387 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1388 {
1389     u32 val = 0;
1390 
1391     val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1392     qspi->bspi_maj_rev = (val >> 8) & 0xff;
1393     qspi->bspi_min_rev = val & 0xff;
1394     if (!(bcm_qspi_bspi_ver_three(qspi))) {
1395         /* Force mapping of BSPI address -> flash offset */
1396         bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1397         bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1398     }
1399     qspi->bspi_enabled = 1;
1400     bcm_qspi_disable_bspi(qspi);
1401     bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1402     bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1403 }
1404 
1405 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1406 {
1407     struct bcm_qspi_parms parms;
1408 
1409     bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1410     bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1411     bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1412     bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1413     bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1414 
1415     parms.mode = SPI_MODE_3;
1416     parms.bits_per_word = 8;
1417     parms.speed_hz = qspi->max_speed_hz;
1418     bcm_qspi_hw_set_parms(qspi, &parms);
1419 
1420     if (has_bspi(qspi))
1421         bcm_qspi_bspi_init(qspi);
1422 }
1423 
1424 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1425 {
1426     u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1427 
1428     bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1429     if (has_bspi(qspi))
1430         bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1431 
1432     /* clear interrupt */
1433     bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1434 }
1435 
1436 static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
1437     .exec_op = bcm_qspi_exec_mem_op,
1438 };
1439 
1440 struct bcm_qspi_data {
1441     bool    has_mspi_rev;
1442     bool    has_spcr3_sysclk;
1443 };
1444 
1445 static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
1446     .has_mspi_rev   = false,
1447     .has_spcr3_sysclk = false,
1448 };
1449 
1450 static const struct bcm_qspi_data bcm_qspi_rev_data = {
1451     .has_mspi_rev   = true,
1452     .has_spcr3_sysclk = false,
1453 };
1454 
1455 static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
1456     .has_mspi_rev   = true,
1457     .has_spcr3_sysclk = true,
1458 };
1459 
1460 static const struct of_device_id bcm_qspi_of_match[] = {
1461     {
1462         .compatible = "brcm,spi-bcm7445-qspi",
1463         .data = &bcm_qspi_rev_data,
1464 
1465     },
1466     {
1467         .compatible = "brcm,spi-bcm-qspi",
1468         .data = &bcm_qspi_no_rev_data,
1469     },
1470     {
1471         .compatible = "brcm,spi-bcm7216-qspi",
1472         .data = &bcm_qspi_spcr3_data,
1473     },
1474     {
1475         .compatible = "brcm,spi-bcm7278-qspi",
1476         .data = &bcm_qspi_spcr3_data,
1477     },
1478     {},
1479 };
1480 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
1481 
1482 int bcm_qspi_probe(struct platform_device *pdev,
1483            struct bcm_qspi_soc_intc *soc_intc)
1484 {
1485     const struct of_device_id *of_id = NULL;
1486     const struct bcm_qspi_data *data;
1487     struct device *dev = &pdev->dev;
1488     struct bcm_qspi *qspi;
1489     struct spi_master *master;
1490     struct resource *res;
1491     int irq, ret = 0, num_ints = 0;
1492     u32 val;
1493     u32 rev = 0;
1494     const char *name = NULL;
1495     int num_irqs = ARRAY_SIZE(qspi_irq_tab);
1496 
1497     /* We only support device-tree instantiation */
1498     if (!dev->of_node)
1499         return -ENODEV;
1500 
1501     of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
1502     if (!of_id)
1503         return -ENODEV;
1504 
1505     data = of_id->data;
1506 
1507     master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi));
1508     if (!master) {
1509         dev_err(dev, "error allocating spi_master\n");
1510         return -ENOMEM;
1511     }
1512 
1513     qspi = spi_master_get_devdata(master);
1514 
1515     qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1516     if (IS_ERR(qspi->clk))
1517         return PTR_ERR(qspi->clk);
1518 
1519     qspi->pdev = pdev;
1520     qspi->trans_pos.trans = NULL;
1521     qspi->trans_pos.byte = 0;
1522     qspi->trans_pos.mspi_last_trans = true;
1523     qspi->master = master;
1524 
1525     master->bus_num = -1;
1526     master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD |
1527                 SPI_3WIRE;
1528     master->setup = bcm_qspi_setup;
1529     master->transfer_one = bcm_qspi_transfer_one;
1530     master->mem_ops = &bcm_qspi_mem_ops;
1531     master->cleanup = bcm_qspi_cleanup;
1532     master->dev.of_node = dev->of_node;
1533     master->num_chipselect = NUM_CHIPSELECT;
1534     master->use_gpio_descriptors = true;
1535 
1536     qspi->big_endian = of_device_is_big_endian(dev->of_node);
1537 
1538     if (!of_property_read_u32(dev->of_node, "num-cs", &val))
1539         master->num_chipselect = val;
1540 
1541     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
1542     if (!res)
1543         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1544                            "mspi");
1545 
1546     if (res) {
1547         qspi->base[MSPI]  = devm_ioremap_resource(dev, res);
1548         if (IS_ERR(qspi->base[MSPI]))
1549             return PTR_ERR(qspi->base[MSPI]);
1550     } else {
1551         return 0;
1552     }
1553 
1554     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi");
1555     if (res) {
1556         qspi->base[BSPI]  = devm_ioremap_resource(dev, res);
1557         if (IS_ERR(qspi->base[BSPI]))
1558             return PTR_ERR(qspi->base[BSPI]);
1559         qspi->bspi_mode = true;
1560     } else {
1561         qspi->bspi_mode = false;
1562     }
1563 
1564     dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1565 
1566     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
1567     if (res) {
1568         qspi->base[CHIP_SELECT]  = devm_ioremap_resource(dev, res);
1569         if (IS_ERR(qspi->base[CHIP_SELECT]))
1570             return PTR_ERR(qspi->base[CHIP_SELECT]);
1571     }
1572 
1573     qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1574                 GFP_KERNEL);
1575     if (!qspi->dev_ids)
1576         return -ENOMEM;
1577 
1578     /*
1579      * Some SoCs integrate spi controller (e.g., its interrupt bits)
1580      * in specific ways
1581      */
1582     if (soc_intc) {
1583         qspi->soc_intc = soc_intc;
1584         soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true);
1585     } else {
1586         qspi->soc_intc = NULL;
1587     }
1588 
1589     if (qspi->clk) {
1590         ret = clk_prepare_enable(qspi->clk);
1591         if (ret) {
1592             dev_err(dev, "failed to prepare clock\n");
1593             goto qspi_probe_err;
1594         }
1595         qspi->base_clk = clk_get_rate(qspi->clk);
1596     } else {
1597         qspi->base_clk = MSPI_BASE_FREQ;
1598     }
1599 
1600     if (data->has_mspi_rev) {
1601         rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1602         /* some older revs do not have a MSPI_REV register */
1603         if ((rev & 0xff) == 0xff)
1604             rev = 0;
1605     }
1606 
1607     qspi->mspi_maj_rev = (rev >> 4) & 0xf;
1608     qspi->mspi_min_rev = rev & 0xf;
1609     qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
1610 
1611     qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
1612 
1613     /*
1614      * On SW resets it is possible to have the mask still enabled
1615      * Need to disable the mask and clear the status while we init
1616      */
1617     bcm_qspi_hw_uninit(qspi);
1618 
1619     for (val = 0; val < num_irqs; val++) {
1620         irq = -1;
1621         name = qspi_irq_tab[val].irq_name;
1622         if (qspi_irq_tab[val].irq_source == SINGLE_L2) {
1623             /* get the l2 interrupts */
1624             irq = platform_get_irq_byname_optional(pdev, name);
1625         } else if (!num_ints && soc_intc) {
1626             /* all mspi, bspi intrs muxed to one L1 intr */
1627             irq = platform_get_irq(pdev, 0);
1628         }
1629 
1630         if (irq  >= 0) {
1631             ret = devm_request_irq(&pdev->dev, irq,
1632                            qspi_irq_tab[val].irq_handler, 0,
1633                            name,
1634                            &qspi->dev_ids[val]);
1635             if (ret < 0) {
1636                 dev_err(&pdev->dev, "IRQ %s not found\n", name);
1637                 goto qspi_unprepare_err;
1638             }
1639 
1640             qspi->dev_ids[val].dev = qspi;
1641             qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1642             num_ints++;
1643             dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
1644                 qspi_irq_tab[val].irq_name,
1645                 irq);
1646         }
1647     }
1648 
1649     if (!num_ints) {
1650         dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
1651         ret = -EINVAL;
1652         goto qspi_unprepare_err;
1653     }
1654 
1655     bcm_qspi_hw_init(qspi);
1656     init_completion(&qspi->mspi_done);
1657     init_completion(&qspi->bspi_done);
1658     qspi->curr_cs = -1;
1659 
1660     platform_set_drvdata(pdev, qspi);
1661 
1662     qspi->xfer_mode.width = -1;
1663     qspi->xfer_mode.addrlen = -1;
1664     qspi->xfer_mode.hp = -1;
1665 
1666     ret = spi_register_master(master);
1667     if (ret < 0) {
1668         dev_err(dev, "can't register master\n");
1669         goto qspi_reg_err;
1670     }
1671 
1672     return 0;
1673 
1674 qspi_reg_err:
1675     bcm_qspi_hw_uninit(qspi);
1676 qspi_unprepare_err:
1677     clk_disable_unprepare(qspi->clk);
1678 qspi_probe_err:
1679     kfree(qspi->dev_ids);
1680     return ret;
1681 }
1682 /* probe function to be called by SoC specific platform driver probe */
1683 EXPORT_SYMBOL_GPL(bcm_qspi_probe);
1684 
1685 int bcm_qspi_remove(struct platform_device *pdev)
1686 {
1687     struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1688 
1689     spi_unregister_master(qspi->master);
1690     bcm_qspi_hw_uninit(qspi);
1691     clk_disable_unprepare(qspi->clk);
1692     kfree(qspi->dev_ids);
1693 
1694     return 0;
1695 }
1696 /* function to be called by SoC specific platform driver remove() */
1697 EXPORT_SYMBOL_GPL(bcm_qspi_remove);
1698 
1699 static int __maybe_unused bcm_qspi_suspend(struct device *dev)
1700 {
1701     struct bcm_qspi *qspi = dev_get_drvdata(dev);
1702 
1703     /* store the override strap value */
1704     if (!bcm_qspi_bspi_ver_three(qspi))
1705         qspi->s3_strap_override_ctrl =
1706             bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1707 
1708     spi_master_suspend(qspi->master);
1709     clk_disable_unprepare(qspi->clk);
1710     bcm_qspi_hw_uninit(qspi);
1711 
1712     return 0;
1713 };
1714 
1715 static int __maybe_unused bcm_qspi_resume(struct device *dev)
1716 {
1717     struct bcm_qspi *qspi = dev_get_drvdata(dev);
1718     int ret = 0;
1719 
1720     bcm_qspi_hw_init(qspi);
1721     bcm_qspi_chip_select(qspi, qspi->curr_cs);
1722     if (qspi->soc_intc)
1723         /* enable MSPI interrupt */
1724         qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1725                          true);
1726 
1727     ret = clk_prepare_enable(qspi->clk);
1728     if (!ret)
1729         spi_master_resume(qspi->master);
1730 
1731     return ret;
1732 }
1733 
1734 SIMPLE_DEV_PM_OPS(bcm_qspi_pm_ops, bcm_qspi_suspend, bcm_qspi_resume);
1735 
1736 /* pm_ops to be called by SoC specific platform driver */
1737 EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
1738 
1739 MODULE_AUTHOR("Kamal Dasu");
1740 MODULE_DESCRIPTION("Broadcom QSPI driver");
1741 MODULE_LICENSE("GPL v2");
1742 MODULE_ALIAS("platform:" DRIVER_NAME);