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0008 #include <linux/clk.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spi/spi.h>
0015
0016 #define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
0017 #define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
0018 #define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
0019
0020 #define SPI_ENGINE_REG_VERSION 0x00
0021
0022 #define SPI_ENGINE_REG_RESET 0x40
0023
0024 #define SPI_ENGINE_REG_INT_ENABLE 0x80
0025 #define SPI_ENGINE_REG_INT_PENDING 0x84
0026 #define SPI_ENGINE_REG_INT_SOURCE 0x88
0027
0028 #define SPI_ENGINE_REG_SYNC_ID 0xc0
0029
0030 #define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xd0
0031 #define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xd4
0032 #define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xd8
0033
0034 #define SPI_ENGINE_REG_CMD_FIFO 0xe0
0035 #define SPI_ENGINE_REG_SDO_DATA_FIFO 0xe4
0036 #define SPI_ENGINE_REG_SDI_DATA_FIFO 0xe8
0037 #define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xec
0038
0039 #define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
0040 #define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
0041 #define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
0042 #define SPI_ENGINE_INT_SYNC BIT(3)
0043
0044 #define SPI_ENGINE_CONFIG_CPHA BIT(0)
0045 #define SPI_ENGINE_CONFIG_CPOL BIT(1)
0046 #define SPI_ENGINE_CONFIG_3WIRE BIT(2)
0047
0048 #define SPI_ENGINE_INST_TRANSFER 0x0
0049 #define SPI_ENGINE_INST_ASSERT 0x1
0050 #define SPI_ENGINE_INST_WRITE 0x2
0051 #define SPI_ENGINE_INST_MISC 0x3
0052
0053 #define SPI_ENGINE_CMD_REG_CLK_DIV 0x0
0054 #define SPI_ENGINE_CMD_REG_CONFIG 0x1
0055
0056 #define SPI_ENGINE_MISC_SYNC 0x0
0057 #define SPI_ENGINE_MISC_SLEEP 0x1
0058
0059 #define SPI_ENGINE_TRANSFER_WRITE 0x1
0060 #define SPI_ENGINE_TRANSFER_READ 0x2
0061
0062 #define SPI_ENGINE_CMD(inst, arg1, arg2) \
0063 (((inst) << 12) | ((arg1) << 8) | (arg2))
0064
0065 #define SPI_ENGINE_CMD_TRANSFER(flags, n) \
0066 SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, (flags), (n))
0067 #define SPI_ENGINE_CMD_ASSERT(delay, cs) \
0068 SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, (delay), (cs))
0069 #define SPI_ENGINE_CMD_WRITE(reg, val) \
0070 SPI_ENGINE_CMD(SPI_ENGINE_INST_WRITE, (reg), (val))
0071 #define SPI_ENGINE_CMD_SLEEP(delay) \
0072 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SLEEP, (delay))
0073 #define SPI_ENGINE_CMD_SYNC(id) \
0074 SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, SPI_ENGINE_MISC_SYNC, (id))
0075
0076 struct spi_engine_program {
0077 unsigned int length;
0078 uint16_t instructions[];
0079 };
0080
0081 struct spi_engine {
0082 struct clk *clk;
0083 struct clk *ref_clk;
0084
0085 spinlock_t lock;
0086
0087 void __iomem *base;
0088
0089 struct spi_message *msg;
0090 struct spi_engine_program *p;
0091 unsigned cmd_length;
0092 const uint16_t *cmd_buf;
0093
0094 struct spi_transfer *tx_xfer;
0095 unsigned int tx_length;
0096 const uint8_t *tx_buf;
0097
0098 struct spi_transfer *rx_xfer;
0099 unsigned int rx_length;
0100 uint8_t *rx_buf;
0101
0102 unsigned int sync_id;
0103 unsigned int completed_id;
0104
0105 unsigned int int_enable;
0106 };
0107
0108 static void spi_engine_program_add_cmd(struct spi_engine_program *p,
0109 bool dry, uint16_t cmd)
0110 {
0111 if (!dry)
0112 p->instructions[p->length] = cmd;
0113 p->length++;
0114 }
0115
0116 static unsigned int spi_engine_get_config(struct spi_device *spi)
0117 {
0118 unsigned int config = 0;
0119
0120 if (spi->mode & SPI_CPOL)
0121 config |= SPI_ENGINE_CONFIG_CPOL;
0122 if (spi->mode & SPI_CPHA)
0123 config |= SPI_ENGINE_CONFIG_CPHA;
0124 if (spi->mode & SPI_3WIRE)
0125 config |= SPI_ENGINE_CONFIG_3WIRE;
0126
0127 return config;
0128 }
0129
0130 static unsigned int spi_engine_get_clk_div(struct spi_engine *spi_engine,
0131 struct spi_device *spi, struct spi_transfer *xfer)
0132 {
0133 unsigned int clk_div;
0134
0135 clk_div = DIV_ROUND_UP(clk_get_rate(spi_engine->ref_clk),
0136 xfer->speed_hz * 2);
0137 if (clk_div > 255)
0138 clk_div = 255;
0139 else if (clk_div > 0)
0140 clk_div -= 1;
0141
0142 return clk_div;
0143 }
0144
0145 static void spi_engine_gen_xfer(struct spi_engine_program *p, bool dry,
0146 struct spi_transfer *xfer)
0147 {
0148 unsigned int len = xfer->len;
0149
0150 while (len) {
0151 unsigned int n = min(len, 256U);
0152 unsigned int flags = 0;
0153
0154 if (xfer->tx_buf)
0155 flags |= SPI_ENGINE_TRANSFER_WRITE;
0156 if (xfer->rx_buf)
0157 flags |= SPI_ENGINE_TRANSFER_READ;
0158
0159 spi_engine_program_add_cmd(p, dry,
0160 SPI_ENGINE_CMD_TRANSFER(flags, n - 1));
0161 len -= n;
0162 }
0163 }
0164
0165 static void spi_engine_gen_sleep(struct spi_engine_program *p, bool dry,
0166 struct spi_engine *spi_engine, unsigned int clk_div,
0167 struct spi_transfer *xfer)
0168 {
0169 unsigned int spi_clk = clk_get_rate(spi_engine->ref_clk);
0170 unsigned int t;
0171 int delay;
0172
0173 delay = spi_delay_to_ns(&xfer->delay, xfer);
0174 if (delay < 0)
0175 return;
0176 delay /= 1000;
0177
0178 if (delay == 0)
0179 return;
0180
0181 t = DIV_ROUND_UP(delay * spi_clk, (clk_div + 1) * 2);
0182 while (t) {
0183 unsigned int n = min(t, 256U);
0184
0185 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_SLEEP(n - 1));
0186 t -= n;
0187 }
0188 }
0189
0190 static void spi_engine_gen_cs(struct spi_engine_program *p, bool dry,
0191 struct spi_device *spi, bool assert)
0192 {
0193 unsigned int mask = 0xff;
0194
0195 if (assert)
0196 mask ^= BIT(spi->chip_select);
0197
0198 spi_engine_program_add_cmd(p, dry, SPI_ENGINE_CMD_ASSERT(1, mask));
0199 }
0200
0201 static int spi_engine_compile_message(struct spi_engine *spi_engine,
0202 struct spi_message *msg, bool dry, struct spi_engine_program *p)
0203 {
0204 struct spi_device *spi = msg->spi;
0205 struct spi_transfer *xfer;
0206 int clk_div, new_clk_div;
0207 bool cs_change = true;
0208
0209 clk_div = -1;
0210
0211 spi_engine_program_add_cmd(p, dry,
0212 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CONFIG,
0213 spi_engine_get_config(spi)));
0214
0215 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
0216 new_clk_div = spi_engine_get_clk_div(spi_engine, spi, xfer);
0217 if (new_clk_div != clk_div) {
0218 clk_div = new_clk_div;
0219 spi_engine_program_add_cmd(p, dry,
0220 SPI_ENGINE_CMD_WRITE(SPI_ENGINE_CMD_REG_CLK_DIV,
0221 clk_div));
0222 }
0223
0224 if (cs_change)
0225 spi_engine_gen_cs(p, dry, spi, true);
0226
0227 spi_engine_gen_xfer(p, dry, xfer);
0228 spi_engine_gen_sleep(p, dry, spi_engine, clk_div, xfer);
0229
0230 cs_change = xfer->cs_change;
0231 if (list_is_last(&xfer->transfer_list, &msg->transfers))
0232 cs_change = !cs_change;
0233
0234 if (cs_change)
0235 spi_engine_gen_cs(p, dry, spi, false);
0236 }
0237
0238 return 0;
0239 }
0240
0241 static void spi_engine_xfer_next(struct spi_engine *spi_engine,
0242 struct spi_transfer **_xfer)
0243 {
0244 struct spi_message *msg = spi_engine->msg;
0245 struct spi_transfer *xfer = *_xfer;
0246
0247 if (!xfer) {
0248 xfer = list_first_entry(&msg->transfers,
0249 struct spi_transfer, transfer_list);
0250 } else if (list_is_last(&xfer->transfer_list, &msg->transfers)) {
0251 xfer = NULL;
0252 } else {
0253 xfer = list_next_entry(xfer, transfer_list);
0254 }
0255
0256 *_xfer = xfer;
0257 }
0258
0259 static void spi_engine_tx_next(struct spi_engine *spi_engine)
0260 {
0261 struct spi_transfer *xfer = spi_engine->tx_xfer;
0262
0263 do {
0264 spi_engine_xfer_next(spi_engine, &xfer);
0265 } while (xfer && !xfer->tx_buf);
0266
0267 spi_engine->tx_xfer = xfer;
0268 if (xfer) {
0269 spi_engine->tx_length = xfer->len;
0270 spi_engine->tx_buf = xfer->tx_buf;
0271 } else {
0272 spi_engine->tx_buf = NULL;
0273 }
0274 }
0275
0276 static void spi_engine_rx_next(struct spi_engine *spi_engine)
0277 {
0278 struct spi_transfer *xfer = spi_engine->rx_xfer;
0279
0280 do {
0281 spi_engine_xfer_next(spi_engine, &xfer);
0282 } while (xfer && !xfer->rx_buf);
0283
0284 spi_engine->rx_xfer = xfer;
0285 if (xfer) {
0286 spi_engine->rx_length = xfer->len;
0287 spi_engine->rx_buf = xfer->rx_buf;
0288 } else {
0289 spi_engine->rx_buf = NULL;
0290 }
0291 }
0292
0293 static bool spi_engine_write_cmd_fifo(struct spi_engine *spi_engine)
0294 {
0295 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_CMD_FIFO;
0296 unsigned int n, m, i;
0297 const uint16_t *buf;
0298
0299 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_CMD_FIFO_ROOM);
0300 while (n && spi_engine->cmd_length) {
0301 m = min(n, spi_engine->cmd_length);
0302 buf = spi_engine->cmd_buf;
0303 for (i = 0; i < m; i++)
0304 writel_relaxed(buf[i], addr);
0305 spi_engine->cmd_buf += m;
0306 spi_engine->cmd_length -= m;
0307 n -= m;
0308 }
0309
0310 return spi_engine->cmd_length != 0;
0311 }
0312
0313 static bool spi_engine_write_tx_fifo(struct spi_engine *spi_engine)
0314 {
0315 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDO_DATA_FIFO;
0316 unsigned int n, m, i;
0317 const uint8_t *buf;
0318
0319 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDO_FIFO_ROOM);
0320 while (n && spi_engine->tx_length) {
0321 m = min(n, spi_engine->tx_length);
0322 buf = spi_engine->tx_buf;
0323 for (i = 0; i < m; i++)
0324 writel_relaxed(buf[i], addr);
0325 spi_engine->tx_buf += m;
0326 spi_engine->tx_length -= m;
0327 n -= m;
0328 if (spi_engine->tx_length == 0)
0329 spi_engine_tx_next(spi_engine);
0330 }
0331
0332 return spi_engine->tx_length != 0;
0333 }
0334
0335 static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine)
0336 {
0337 void __iomem *addr = spi_engine->base + SPI_ENGINE_REG_SDI_DATA_FIFO;
0338 unsigned int n, m, i;
0339 uint8_t *buf;
0340
0341 n = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_SDI_FIFO_LEVEL);
0342 while (n && spi_engine->rx_length) {
0343 m = min(n, spi_engine->rx_length);
0344 buf = spi_engine->rx_buf;
0345 for (i = 0; i < m; i++)
0346 buf[i] = readl_relaxed(addr);
0347 spi_engine->rx_buf += m;
0348 spi_engine->rx_length -= m;
0349 n -= m;
0350 if (spi_engine->rx_length == 0)
0351 spi_engine_rx_next(spi_engine);
0352 }
0353
0354 return spi_engine->rx_length != 0;
0355 }
0356
0357 static irqreturn_t spi_engine_irq(int irq, void *devid)
0358 {
0359 struct spi_master *master = devid;
0360 struct spi_engine *spi_engine = spi_master_get_devdata(master);
0361 unsigned int disable_int = 0;
0362 unsigned int pending;
0363
0364 pending = readl_relaxed(spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
0365
0366 if (pending & SPI_ENGINE_INT_SYNC) {
0367 writel_relaxed(SPI_ENGINE_INT_SYNC,
0368 spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
0369 spi_engine->completed_id = readl_relaxed(
0370 spi_engine->base + SPI_ENGINE_REG_SYNC_ID);
0371 }
0372
0373 spin_lock(&spi_engine->lock);
0374
0375 if (pending & SPI_ENGINE_INT_CMD_ALMOST_EMPTY) {
0376 if (!spi_engine_write_cmd_fifo(spi_engine))
0377 disable_int |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
0378 }
0379
0380 if (pending & SPI_ENGINE_INT_SDO_ALMOST_EMPTY) {
0381 if (!spi_engine_write_tx_fifo(spi_engine))
0382 disable_int |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
0383 }
0384
0385 if (pending & (SPI_ENGINE_INT_SDI_ALMOST_FULL | SPI_ENGINE_INT_SYNC)) {
0386 if (!spi_engine_read_rx_fifo(spi_engine))
0387 disable_int |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
0388 }
0389
0390 if (pending & SPI_ENGINE_INT_SYNC) {
0391 if (spi_engine->msg &&
0392 spi_engine->completed_id == spi_engine->sync_id) {
0393 struct spi_message *msg = spi_engine->msg;
0394
0395 kfree(spi_engine->p);
0396 msg->status = 0;
0397 msg->actual_length = msg->frame_length;
0398 spi_engine->msg = NULL;
0399 spi_finalize_current_message(master);
0400 disable_int |= SPI_ENGINE_INT_SYNC;
0401 }
0402 }
0403
0404 if (disable_int) {
0405 spi_engine->int_enable &= ~disable_int;
0406 writel_relaxed(spi_engine->int_enable,
0407 spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
0408 }
0409
0410 spin_unlock(&spi_engine->lock);
0411
0412 return IRQ_HANDLED;
0413 }
0414
0415 static int spi_engine_transfer_one_message(struct spi_master *master,
0416 struct spi_message *msg)
0417 {
0418 struct spi_engine_program p_dry, *p;
0419 struct spi_engine *spi_engine = spi_master_get_devdata(master);
0420 unsigned int int_enable = 0;
0421 unsigned long flags;
0422 size_t size;
0423
0424 p_dry.length = 0;
0425 spi_engine_compile_message(spi_engine, msg, true, &p_dry);
0426
0427 size = sizeof(*p->instructions) * (p_dry.length + 1);
0428 p = kzalloc(sizeof(*p) + size, GFP_KERNEL);
0429 if (!p)
0430 return -ENOMEM;
0431 spi_engine_compile_message(spi_engine, msg, false, p);
0432
0433 spin_lock_irqsave(&spi_engine->lock, flags);
0434 spi_engine->sync_id = (spi_engine->sync_id + 1) & 0xff;
0435 spi_engine_program_add_cmd(p, false,
0436 SPI_ENGINE_CMD_SYNC(spi_engine->sync_id));
0437
0438 spi_engine->msg = msg;
0439 spi_engine->p = p;
0440
0441 spi_engine->cmd_buf = p->instructions;
0442 spi_engine->cmd_length = p->length;
0443 if (spi_engine_write_cmd_fifo(spi_engine))
0444 int_enable |= SPI_ENGINE_INT_CMD_ALMOST_EMPTY;
0445
0446 spi_engine_tx_next(spi_engine);
0447 if (spi_engine_write_tx_fifo(spi_engine))
0448 int_enable |= SPI_ENGINE_INT_SDO_ALMOST_EMPTY;
0449
0450 spi_engine_rx_next(spi_engine);
0451 if (spi_engine->rx_length != 0)
0452 int_enable |= SPI_ENGINE_INT_SDI_ALMOST_FULL;
0453
0454 int_enable |= SPI_ENGINE_INT_SYNC;
0455
0456 writel_relaxed(int_enable,
0457 spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
0458 spi_engine->int_enable = int_enable;
0459 spin_unlock_irqrestore(&spi_engine->lock, flags);
0460
0461 return 0;
0462 }
0463
0464 static int spi_engine_probe(struct platform_device *pdev)
0465 {
0466 struct spi_engine *spi_engine;
0467 struct spi_master *master;
0468 unsigned int version;
0469 int irq;
0470 int ret;
0471
0472 irq = platform_get_irq(pdev, 0);
0473 if (irq <= 0)
0474 return -ENXIO;
0475
0476 spi_engine = devm_kzalloc(&pdev->dev, sizeof(*spi_engine), GFP_KERNEL);
0477 if (!spi_engine)
0478 return -ENOMEM;
0479
0480 master = spi_alloc_master(&pdev->dev, 0);
0481 if (!master)
0482 return -ENOMEM;
0483
0484 spi_master_set_devdata(master, spi_engine);
0485
0486 spin_lock_init(&spi_engine->lock);
0487
0488 spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
0489 if (IS_ERR(spi_engine->clk)) {
0490 ret = PTR_ERR(spi_engine->clk);
0491 goto err_put_master;
0492 }
0493
0494 spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk");
0495 if (IS_ERR(spi_engine->ref_clk)) {
0496 ret = PTR_ERR(spi_engine->ref_clk);
0497 goto err_put_master;
0498 }
0499
0500 ret = clk_prepare_enable(spi_engine->clk);
0501 if (ret)
0502 goto err_put_master;
0503
0504 ret = clk_prepare_enable(spi_engine->ref_clk);
0505 if (ret)
0506 goto err_clk_disable;
0507
0508 spi_engine->base = devm_platform_ioremap_resource(pdev, 0);
0509 if (IS_ERR(spi_engine->base)) {
0510 ret = PTR_ERR(spi_engine->base);
0511 goto err_ref_clk_disable;
0512 }
0513
0514 version = readl(spi_engine->base + SPI_ENGINE_REG_VERSION);
0515 if (SPI_ENGINE_VERSION_MAJOR(version) != 1) {
0516 dev_err(&pdev->dev, "Unsupported peripheral version %u.%u.%c\n",
0517 SPI_ENGINE_VERSION_MAJOR(version),
0518 SPI_ENGINE_VERSION_MINOR(version),
0519 SPI_ENGINE_VERSION_PATCH(version));
0520 ret = -ENODEV;
0521 goto err_ref_clk_disable;
0522 }
0523
0524 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_RESET);
0525 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
0526 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
0527
0528 ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master);
0529 if (ret)
0530 goto err_ref_clk_disable;
0531
0532 master->dev.of_node = pdev->dev.of_node;
0533 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
0534 master->bits_per_word_mask = SPI_BPW_MASK(8);
0535 master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
0536 master->transfer_one_message = spi_engine_transfer_one_message;
0537 master->num_chipselect = 8;
0538
0539 ret = spi_register_master(master);
0540 if (ret)
0541 goto err_free_irq;
0542
0543 platform_set_drvdata(pdev, master);
0544
0545 return 0;
0546 err_free_irq:
0547 free_irq(irq, master);
0548 err_ref_clk_disable:
0549 clk_disable_unprepare(spi_engine->ref_clk);
0550 err_clk_disable:
0551 clk_disable_unprepare(spi_engine->clk);
0552 err_put_master:
0553 spi_master_put(master);
0554 return ret;
0555 }
0556
0557 static int spi_engine_remove(struct platform_device *pdev)
0558 {
0559 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
0560 struct spi_engine *spi_engine = spi_master_get_devdata(master);
0561 int irq = platform_get_irq(pdev, 0);
0562
0563 spi_unregister_master(master);
0564
0565 free_irq(irq, master);
0566
0567 spi_master_put(master);
0568
0569 writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
0570 writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
0571 writel_relaxed(0x01, spi_engine->base + SPI_ENGINE_REG_RESET);
0572
0573 clk_disable_unprepare(spi_engine->ref_clk);
0574 clk_disable_unprepare(spi_engine->clk);
0575
0576 return 0;
0577 }
0578
0579 static const struct of_device_id spi_engine_match_table[] = {
0580 { .compatible = "adi,axi-spi-engine-1.00.a" },
0581 { },
0582 };
0583 MODULE_DEVICE_TABLE(of, spi_engine_match_table);
0584
0585 static struct platform_driver spi_engine_driver = {
0586 .probe = spi_engine_probe,
0587 .remove = spi_engine_remove,
0588 .driver = {
0589 .name = "spi-engine",
0590 .of_match_table = spi_engine_match_table,
0591 },
0592 };
0593 module_platform_driver(spi_engine_driver);
0594
0595 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0596 MODULE_DESCRIPTION("Analog Devices SPI engine peripheral driver");
0597 MODULE_LICENSE("GPL");
