Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * au1550 psc spi controller driver
0004  * may work also with au1200, au1210, au1250
0005  * will not work on au1000, au1100 and au1500 (no full spi controller there)
0006  *
0007  * Copyright (c) 2006 ATRON electronic GmbH
0008  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
0009  */
0010 
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/slab.h>
0014 #include <linux/errno.h>
0015 #include <linux/module.h>
0016 #include <linux/device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/resource.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/spi/spi_bitbang.h>
0021 #include <linux/dma-mapping.h>
0022 #include <linux/completion.h>
0023 #include <asm/mach-au1x00/au1000.h>
0024 #include <asm/mach-au1x00/au1xxx_psc.h>
0025 #include <asm/mach-au1x00/au1xxx_dbdma.h>
0026 
0027 #include <asm/mach-au1x00/au1550_spi.h>
0028 
0029 static unsigned int usedma = 1;
0030 module_param(usedma, uint, 0644);
0031 
0032 /*
0033 #define AU1550_SPI_DEBUG_LOOPBACK
0034 */
0035 
0036 
0037 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
0038 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
0039 
0040 struct au1550_spi {
0041     struct spi_bitbang bitbang;
0042 
0043     volatile psc_spi_t __iomem *regs;
0044     int irq;
0045 
0046     unsigned int len;
0047     unsigned int tx_count;
0048     unsigned int rx_count;
0049     const u8 *tx;
0050     u8 *rx;
0051 
0052     void (*rx_word)(struct au1550_spi *hw);
0053     void (*tx_word)(struct au1550_spi *hw);
0054     int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
0055     irqreturn_t (*irq_callback)(struct au1550_spi *hw);
0056 
0057     struct completion master_done;
0058 
0059     unsigned int usedma;
0060     u32 dma_tx_id;
0061     u32 dma_rx_id;
0062     u32 dma_tx_ch;
0063     u32 dma_rx_ch;
0064 
0065     u8 *dma_rx_tmpbuf;
0066     unsigned int dma_rx_tmpbuf_size;
0067     u32 dma_rx_tmpbuf_addr;
0068 
0069     struct spi_master *master;
0070     struct device *dev;
0071     struct au1550_spi_info *pdata;
0072     struct resource *ioarea;
0073 };
0074 
0075 
0076 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
0077 static dbdev_tab_t au1550_spi_mem_dbdev = {
0078     .dev_id         = DBDMA_MEM_CHAN,
0079     .dev_flags      = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
0080     .dev_tsize      = 0,
0081     .dev_devwidth       = 8,
0082     .dev_physaddr       = 0x00000000,
0083     .dev_intlevel       = 0,
0084     .dev_intpolarity    = 0
0085 };
0086 
0087 static int ddma_memid;  /* id to above mem dma device */
0088 
0089 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
0090 
0091 
0092 /*
0093  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
0094  *  that was specified in platform data structure
0095  *  according to au1550 datasheet:
0096  *    psc_tempclk = psc_mainclk / (2 << DIV)
0097  *    spiclk = psc_tempclk / (2 * (BRG + 1))
0098  *    BRG valid range is 4..63
0099  *    DIV valid range is 0..3
0100  */
0101 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
0102 {
0103     u32 mainclk_hz = hw->pdata->mainclk_hz;
0104     u32 div, brg;
0105 
0106     for (div = 0; div < 4; div++) {
0107         brg = mainclk_hz / speed_hz / (4 << div);
0108         /* now we have BRG+1 in brg, so count with that */
0109         if (brg < (4 + 1)) {
0110             brg = (4 + 1);  /* speed_hz too big */
0111             break;      /* set lowest brg (div is == 0) */
0112         }
0113         if (brg <= (63 + 1))
0114             break;      /* we have valid brg and div */
0115     }
0116     if (div == 4) {
0117         div = 3;        /* speed_hz too small */
0118         brg = (63 + 1);     /* set highest brg and div */
0119     }
0120     brg--;
0121     return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
0122 }
0123 
0124 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
0125 {
0126     hw->regs->psc_spimsk =
0127           PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
0128         | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
0129         | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
0130     wmb(); /* drain writebuffer */
0131 
0132     hw->regs->psc_spievent =
0133           PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
0134         | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
0135         | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
0136     wmb(); /* drain writebuffer */
0137 }
0138 
0139 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
0140 {
0141     u32 pcr;
0142 
0143     hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
0144     wmb(); /* drain writebuffer */
0145     do {
0146         pcr = hw->regs->psc_spipcr;
0147         wmb(); /* drain writebuffer */
0148     } while (pcr != 0);
0149 }
0150 
0151 /*
0152  * dma transfers are used for the most common spi word size of 8-bits
0153  * we cannot easily change already set up dma channels' width, so if we wanted
0154  * dma support for more than 8-bit words (up to 24 bits), we would need to
0155  * setup dma channels from scratch on each spi transfer, based on bits_per_word
0156  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
0157  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
0158  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
0159  */
0160 static void au1550_spi_chipsel(struct spi_device *spi, int value)
0161 {
0162     struct au1550_spi *hw = spi_master_get_devdata(spi->master);
0163     unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
0164     u32 cfg, stat;
0165 
0166     switch (value) {
0167     case BITBANG_CS_INACTIVE:
0168         if (hw->pdata->deactivate_cs)
0169             hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
0170                     cspol);
0171         break;
0172 
0173     case BITBANG_CS_ACTIVE:
0174         au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
0175 
0176         cfg = hw->regs->psc_spicfg;
0177         wmb(); /* drain writebuffer */
0178         hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
0179         wmb(); /* drain writebuffer */
0180 
0181         if (spi->mode & SPI_CPOL)
0182             cfg |= PSC_SPICFG_BI;
0183         else
0184             cfg &= ~PSC_SPICFG_BI;
0185         if (spi->mode & SPI_CPHA)
0186             cfg &= ~PSC_SPICFG_CDE;
0187         else
0188             cfg |= PSC_SPICFG_CDE;
0189 
0190         if (spi->mode & SPI_LSB_FIRST)
0191             cfg |= PSC_SPICFG_MLF;
0192         else
0193             cfg &= ~PSC_SPICFG_MLF;
0194 
0195         if (hw->usedma && spi->bits_per_word <= 8)
0196             cfg &= ~PSC_SPICFG_DD_DISABLE;
0197         else
0198             cfg |= PSC_SPICFG_DD_DISABLE;
0199         cfg = PSC_SPICFG_CLR_LEN(cfg);
0200         cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
0201 
0202         cfg = PSC_SPICFG_CLR_BAUD(cfg);
0203         cfg &= ~PSC_SPICFG_SET_DIV(3);
0204         cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
0205 
0206         hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
0207         wmb(); /* drain writebuffer */
0208         do {
0209             stat = hw->regs->psc_spistat;
0210             wmb(); /* drain writebuffer */
0211         } while ((stat & PSC_SPISTAT_DR) == 0);
0212 
0213         if (hw->pdata->activate_cs)
0214             hw->pdata->activate_cs(hw->pdata, spi->chip_select,
0215                     cspol);
0216         break;
0217     }
0218 }
0219 
0220 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
0221 {
0222     struct au1550_spi *hw = spi_master_get_devdata(spi->master);
0223     unsigned int bpw, hz;
0224     u32 cfg, stat;
0225 
0226     if (t) {
0227         bpw = t->bits_per_word;
0228         hz = t->speed_hz;
0229     } else {
0230         bpw = spi->bits_per_word;
0231         hz = spi->max_speed_hz;
0232     }
0233 
0234     if (!hz)
0235         return -EINVAL;
0236 
0237     au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
0238 
0239     cfg = hw->regs->psc_spicfg;
0240     wmb(); /* drain writebuffer */
0241     hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
0242     wmb(); /* drain writebuffer */
0243 
0244     if (hw->usedma && bpw <= 8)
0245         cfg &= ~PSC_SPICFG_DD_DISABLE;
0246     else
0247         cfg |= PSC_SPICFG_DD_DISABLE;
0248     cfg = PSC_SPICFG_CLR_LEN(cfg);
0249     cfg |= PSC_SPICFG_SET_LEN(bpw);
0250 
0251     cfg = PSC_SPICFG_CLR_BAUD(cfg);
0252     cfg &= ~PSC_SPICFG_SET_DIV(3);
0253     cfg |= au1550_spi_baudcfg(hw, hz);
0254 
0255     hw->regs->psc_spicfg = cfg;
0256     wmb(); /* drain writebuffer */
0257 
0258     if (cfg & PSC_SPICFG_DE_ENABLE) {
0259         do {
0260             stat = hw->regs->psc_spistat;
0261             wmb(); /* drain writebuffer */
0262         } while ((stat & PSC_SPISTAT_DR) == 0);
0263     }
0264 
0265     au1550_spi_reset_fifos(hw);
0266     au1550_spi_mask_ack_all(hw);
0267     return 0;
0268 }
0269 
0270 /*
0271  * for dma spi transfers, we have to setup rx channel, otherwise there is
0272  * no reliable way how to recognize that spi transfer is done
0273  * dma complete callbacks are called before real spi transfer is finished
0274  * and if only tx dma channel is set up (and rx fifo overflow event masked)
0275  * spi master done event irq is not generated unless rx fifo is empty (emptied)
0276  * so we need rx tmp buffer to use for rx dma if user does not provide one
0277  */
0278 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
0279 {
0280     hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
0281     if (!hw->dma_rx_tmpbuf)
0282         return -ENOMEM;
0283     hw->dma_rx_tmpbuf_size = size;
0284     hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
0285             size, DMA_FROM_DEVICE);
0286     if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
0287         kfree(hw->dma_rx_tmpbuf);
0288         hw->dma_rx_tmpbuf = 0;
0289         hw->dma_rx_tmpbuf_size = 0;
0290         return -EFAULT;
0291     }
0292     return 0;
0293 }
0294 
0295 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
0296 {
0297     dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
0298             hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
0299     kfree(hw->dma_rx_tmpbuf);
0300     hw->dma_rx_tmpbuf = 0;
0301     hw->dma_rx_tmpbuf_size = 0;
0302 }
0303 
0304 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
0305 {
0306     struct au1550_spi *hw = spi_master_get_devdata(spi->master);
0307     dma_addr_t dma_tx_addr;
0308     dma_addr_t dma_rx_addr;
0309     u32 res;
0310 
0311     hw->len = t->len;
0312     hw->tx_count = 0;
0313     hw->rx_count = 0;
0314 
0315     hw->tx = t->tx_buf;
0316     hw->rx = t->rx_buf;
0317     dma_tx_addr = t->tx_dma;
0318     dma_rx_addr = t->rx_dma;
0319 
0320     /*
0321      * check if buffers are already dma mapped, map them otherwise:
0322      * - first map the TX buffer, so cache data gets written to memory
0323      * - then map the RX buffer, so that cache entries (with
0324      *   soon-to-be-stale data) get removed
0325      * use rx buffer in place of tx if tx buffer was not provided
0326      * use temp rx buffer (preallocated or realloc to fit) for rx dma
0327      */
0328     if (t->tx_buf) {
0329         if (t->tx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
0330             dma_tx_addr = dma_map_single(hw->dev,
0331                     (void *)t->tx_buf,
0332                     t->len, DMA_TO_DEVICE);
0333             if (dma_mapping_error(hw->dev, dma_tx_addr))
0334                 dev_err(hw->dev, "tx dma map error\n");
0335         }
0336     }
0337 
0338     if (t->rx_buf) {
0339         if (t->rx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
0340             dma_rx_addr = dma_map_single(hw->dev,
0341                     (void *)t->rx_buf,
0342                     t->len, DMA_FROM_DEVICE);
0343             if (dma_mapping_error(hw->dev, dma_rx_addr))
0344                 dev_err(hw->dev, "rx dma map error\n");
0345         }
0346     } else {
0347         if (t->len > hw->dma_rx_tmpbuf_size) {
0348             int ret;
0349 
0350             au1550_spi_dma_rxtmp_free(hw);
0351             ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
0352                     AU1550_SPI_DMA_RXTMP_MINSIZE));
0353             if (ret < 0)
0354                 return ret;
0355         }
0356         hw->rx = hw->dma_rx_tmpbuf;
0357         dma_rx_addr = hw->dma_rx_tmpbuf_addr;
0358         dma_sync_single_for_device(hw->dev, dma_rx_addr,
0359             t->len, DMA_FROM_DEVICE);
0360     }
0361 
0362     if (!t->tx_buf) {
0363         dma_sync_single_for_device(hw->dev, dma_rx_addr,
0364                 t->len, DMA_BIDIRECTIONAL);
0365         hw->tx = hw->rx;
0366     }
0367 
0368     /* put buffers on the ring */
0369     res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
0370                     t->len, DDMA_FLAGS_IE);
0371     if (!res)
0372         dev_err(hw->dev, "rx dma put dest error\n");
0373 
0374     res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
0375                       t->len, DDMA_FLAGS_IE);
0376     if (!res)
0377         dev_err(hw->dev, "tx dma put source error\n");
0378 
0379     au1xxx_dbdma_start(hw->dma_rx_ch);
0380     au1xxx_dbdma_start(hw->dma_tx_ch);
0381 
0382     /* by default enable nearly all events interrupt */
0383     hw->regs->psc_spimsk = PSC_SPIMSK_SD;
0384     wmb(); /* drain writebuffer */
0385 
0386     /* start the transfer */
0387     hw->regs->psc_spipcr = PSC_SPIPCR_MS;
0388     wmb(); /* drain writebuffer */
0389 
0390     wait_for_completion(&hw->master_done);
0391 
0392     au1xxx_dbdma_stop(hw->dma_tx_ch);
0393     au1xxx_dbdma_stop(hw->dma_rx_ch);
0394 
0395     if (!t->rx_buf) {
0396         /* using the temporal preallocated and premapped buffer */
0397         dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
0398             DMA_FROM_DEVICE);
0399     }
0400     /* unmap buffers if mapped above */
0401     if (t->rx_buf && t->rx_dma == 0)
0402         dma_unmap_single(hw->dev, dma_rx_addr, t->len,
0403             DMA_FROM_DEVICE);
0404     if (t->tx_buf && t->tx_dma == 0)
0405         dma_unmap_single(hw->dev, dma_tx_addr, t->len,
0406             DMA_TO_DEVICE);
0407 
0408     return min(hw->rx_count, hw->tx_count);
0409 }
0410 
0411 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
0412 {
0413     u32 stat, evnt;
0414 
0415     stat = hw->regs->psc_spistat;
0416     evnt = hw->regs->psc_spievent;
0417     wmb(); /* drain writebuffer */
0418     if ((stat & PSC_SPISTAT_DI) == 0) {
0419         dev_err(hw->dev, "Unexpected IRQ!\n");
0420         return IRQ_NONE;
0421     }
0422 
0423     if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
0424                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
0425                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
0426             != 0) {
0427         /*
0428          * due to an spi error we consider transfer as done,
0429          * so mask all events until before next transfer start
0430          * and stop the possibly running dma immediately
0431          */
0432         au1550_spi_mask_ack_all(hw);
0433         au1xxx_dbdma_stop(hw->dma_rx_ch);
0434         au1xxx_dbdma_stop(hw->dma_tx_ch);
0435 
0436         /* get number of transferred bytes */
0437         hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
0438         hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
0439 
0440         au1xxx_dbdma_reset(hw->dma_rx_ch);
0441         au1xxx_dbdma_reset(hw->dma_tx_ch);
0442         au1550_spi_reset_fifos(hw);
0443 
0444         if (evnt == PSC_SPIEVNT_RO)
0445             dev_err(hw->dev,
0446                 "dma transfer: receive FIFO overflow!\n");
0447         else
0448             dev_err(hw->dev,
0449                 "dma transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
0450                 evnt, stat);
0451 
0452         complete(&hw->master_done);
0453         return IRQ_HANDLED;
0454     }
0455 
0456     if ((evnt & PSC_SPIEVNT_MD) != 0) {
0457         /* transfer completed successfully */
0458         au1550_spi_mask_ack_all(hw);
0459         hw->rx_count = hw->len;
0460         hw->tx_count = hw->len;
0461         complete(&hw->master_done);
0462     }
0463     return IRQ_HANDLED;
0464 }
0465 
0466 
0467 /* routines to handle different word sizes in pio mode */
0468 #define AU1550_SPI_RX_WORD(size, mask)                  \
0469 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)        \
0470 {                                   \
0471     u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);     \
0472     wmb(); /* drain writebuffer */                  \
0473     if (hw->rx) {                           \
0474         *(u##size *)hw->rx = (u##size)fifoword;         \
0475         hw->rx += (size) / 8;                   \
0476     }                               \
0477     hw->rx_count += (size) / 8;                 \
0478 }
0479 
0480 #define AU1550_SPI_TX_WORD(size, mask)                  \
0481 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)        \
0482 {                                   \
0483     u32 fifoword = 0;                       \
0484     if (hw->tx) {                           \
0485         fifoword = *(u##size *)hw->tx & (u32)(mask);        \
0486         hw->tx += (size) / 8;                   \
0487     }                               \
0488     hw->tx_count += (size) / 8;                 \
0489     if (hw->tx_count >= hw->len)                    \
0490         fifoword |= PSC_SPITXRX_LC;             \
0491     hw->regs->psc_spitxrx = fifoword;               \
0492     wmb(); /* drain writebuffer */                  \
0493 }
0494 
0495 AU1550_SPI_RX_WORD(8, 0xff)
0496 AU1550_SPI_RX_WORD(16, 0xffff)
0497 AU1550_SPI_RX_WORD(32, 0xffffff)
0498 AU1550_SPI_TX_WORD(8, 0xff)
0499 AU1550_SPI_TX_WORD(16, 0xffff)
0500 AU1550_SPI_TX_WORD(32, 0xffffff)
0501 
0502 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
0503 {
0504     u32 stat, mask;
0505     struct au1550_spi *hw = spi_master_get_devdata(spi->master);
0506 
0507     hw->tx = t->tx_buf;
0508     hw->rx = t->rx_buf;
0509     hw->len = t->len;
0510     hw->tx_count = 0;
0511     hw->rx_count = 0;
0512 
0513     /* by default enable nearly all events after filling tx fifo */
0514     mask = PSC_SPIMSK_SD;
0515 
0516     /* fill the transmit FIFO */
0517     while (hw->tx_count < hw->len) {
0518 
0519         hw->tx_word(hw);
0520 
0521         if (hw->tx_count >= hw->len) {
0522             /* mask tx fifo request interrupt as we are done */
0523             mask |= PSC_SPIMSK_TR;
0524         }
0525 
0526         stat = hw->regs->psc_spistat;
0527         wmb(); /* drain writebuffer */
0528         if (stat & PSC_SPISTAT_TF)
0529             break;
0530     }
0531 
0532     /* enable event interrupts */
0533     hw->regs->psc_spimsk = mask;
0534     wmb(); /* drain writebuffer */
0535 
0536     /* start the transfer */
0537     hw->regs->psc_spipcr = PSC_SPIPCR_MS;
0538     wmb(); /* drain writebuffer */
0539 
0540     wait_for_completion(&hw->master_done);
0541 
0542     return min(hw->rx_count, hw->tx_count);
0543 }
0544 
0545 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
0546 {
0547     int busy;
0548     u32 stat, evnt;
0549 
0550     stat = hw->regs->psc_spistat;
0551     evnt = hw->regs->psc_spievent;
0552     wmb(); /* drain writebuffer */
0553     if ((stat & PSC_SPISTAT_DI) == 0) {
0554         dev_err(hw->dev, "Unexpected IRQ!\n");
0555         return IRQ_NONE;
0556     }
0557 
0558     if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
0559                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
0560                 | PSC_SPIEVNT_SD))
0561             != 0) {
0562         /*
0563          * due to an error we consider transfer as done,
0564          * so mask all events until before next transfer start
0565          */
0566         au1550_spi_mask_ack_all(hw);
0567         au1550_spi_reset_fifos(hw);
0568         dev_err(hw->dev,
0569             "pio transfer: unexpected SPI error (event=0x%x stat=0x%x)!\n",
0570             evnt, stat);
0571         complete(&hw->master_done);
0572         return IRQ_HANDLED;
0573     }
0574 
0575     /*
0576      * while there is something to read from rx fifo
0577      * or there is a space to write to tx fifo:
0578      */
0579     do {
0580         busy = 0;
0581         stat = hw->regs->psc_spistat;
0582         wmb(); /* drain writebuffer */
0583 
0584         /*
0585          * Take care to not let the Rx FIFO overflow.
0586          *
0587          * We only write a byte if we have read one at least. Initially,
0588          * the write fifo is full, so we should read from the read fifo
0589          * first.
0590          * In case we miss a word from the read fifo, we should get a
0591          * RO event and should back out.
0592          */
0593         if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
0594             hw->rx_word(hw);
0595             busy = 1;
0596 
0597             if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
0598                 hw->tx_word(hw);
0599         }
0600     } while (busy);
0601 
0602     hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
0603     wmb(); /* drain writebuffer */
0604 
0605     /*
0606      * Restart the SPI transmission in case of a transmit underflow.
0607      * This seems to work despite the notes in the Au1550 data book
0608      * of Figure 8-4 with flowchart for SPI master operation:
0609      *
0610      * """Note 1: An XFR Error Interrupt occurs, unless masked,
0611      * for any of the following events: Tx FIFO Underflow,
0612      * Rx FIFO Overflow, or Multiple-master Error
0613      *    Note 2: In case of a Tx Underflow Error, all zeroes are
0614      * transmitted."""
0615      *
0616      * By simply restarting the spi transfer on Tx Underflow Error,
0617      * we assume that spi transfer was paused instead of zeroes
0618      * transmittion mentioned in the Note 2 of Au1550 data book.
0619      */
0620     if (evnt & PSC_SPIEVNT_TU) {
0621         hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
0622         wmb(); /* drain writebuffer */
0623         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
0624         wmb(); /* drain writebuffer */
0625     }
0626 
0627     if (hw->rx_count >= hw->len) {
0628         /* transfer completed successfully */
0629         au1550_spi_mask_ack_all(hw);
0630         complete(&hw->master_done);
0631     }
0632     return IRQ_HANDLED;
0633 }
0634 
0635 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
0636 {
0637     struct au1550_spi *hw = spi_master_get_devdata(spi->master);
0638 
0639     return hw->txrx_bufs(spi, t);
0640 }
0641 
0642 static irqreturn_t au1550_spi_irq(int irq, void *dev)
0643 {
0644     struct au1550_spi *hw = dev;
0645 
0646     return hw->irq_callback(hw);
0647 }
0648 
0649 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
0650 {
0651     if (bpw <= 8) {
0652         if (hw->usedma) {
0653             hw->txrx_bufs = &au1550_spi_dma_txrxb;
0654             hw->irq_callback = &au1550_spi_dma_irq_callback;
0655         } else {
0656             hw->rx_word = &au1550_spi_rx_word_8;
0657             hw->tx_word = &au1550_spi_tx_word_8;
0658             hw->txrx_bufs = &au1550_spi_pio_txrxb;
0659             hw->irq_callback = &au1550_spi_pio_irq_callback;
0660         }
0661     } else if (bpw <= 16) {
0662         hw->rx_word = &au1550_spi_rx_word_16;
0663         hw->tx_word = &au1550_spi_tx_word_16;
0664         hw->txrx_bufs = &au1550_spi_pio_txrxb;
0665         hw->irq_callback = &au1550_spi_pio_irq_callback;
0666     } else {
0667         hw->rx_word = &au1550_spi_rx_word_32;
0668         hw->tx_word = &au1550_spi_tx_word_32;
0669         hw->txrx_bufs = &au1550_spi_pio_txrxb;
0670         hw->irq_callback = &au1550_spi_pio_irq_callback;
0671     }
0672 }
0673 
0674 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
0675 {
0676     u32 stat, cfg;
0677 
0678     /* set up the PSC for SPI mode */
0679     hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
0680     wmb(); /* drain writebuffer */
0681     hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
0682     wmb(); /* drain writebuffer */
0683 
0684     hw->regs->psc_spicfg = 0;
0685     wmb(); /* drain writebuffer */
0686 
0687     hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
0688     wmb(); /* drain writebuffer */
0689 
0690     do {
0691         stat = hw->regs->psc_spistat;
0692         wmb(); /* drain writebuffer */
0693     } while ((stat & PSC_SPISTAT_SR) == 0);
0694 
0695 
0696     cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
0697     cfg |= PSC_SPICFG_SET_LEN(8);
0698     cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
0699     /* use minimal allowed brg and div values as initial setting: */
0700     cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
0701 
0702 #ifdef AU1550_SPI_DEBUG_LOOPBACK
0703     cfg |= PSC_SPICFG_LB;
0704 #endif
0705 
0706     hw->regs->psc_spicfg = cfg;
0707     wmb(); /* drain writebuffer */
0708 
0709     au1550_spi_mask_ack_all(hw);
0710 
0711     hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
0712     wmb(); /* drain writebuffer */
0713 
0714     do {
0715         stat = hw->regs->psc_spistat;
0716         wmb(); /* drain writebuffer */
0717     } while ((stat & PSC_SPISTAT_DR) == 0);
0718 
0719     au1550_spi_reset_fifos(hw);
0720 }
0721 
0722 
0723 static int au1550_spi_probe(struct platform_device *pdev)
0724 {
0725     struct au1550_spi *hw;
0726     struct spi_master *master;
0727     struct resource *r;
0728     int err = 0;
0729 
0730     master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
0731     if (master == NULL) {
0732         dev_err(&pdev->dev, "No memory for spi_master\n");
0733         err = -ENOMEM;
0734         goto err_nomem;
0735     }
0736 
0737     /* the spi->mode bits understood by this driver: */
0738     master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
0739     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
0740 
0741     hw = spi_master_get_devdata(master);
0742 
0743     hw->master = master;
0744     hw->pdata = dev_get_platdata(&pdev->dev);
0745     hw->dev = &pdev->dev;
0746 
0747     if (hw->pdata == NULL) {
0748         dev_err(&pdev->dev, "No platform data supplied\n");
0749         err = -ENOENT;
0750         goto err_no_pdata;
0751     }
0752 
0753     r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
0754     if (!r) {
0755         dev_err(&pdev->dev, "no IRQ\n");
0756         err = -ENODEV;
0757         goto err_no_iores;
0758     }
0759     hw->irq = r->start;
0760 
0761     hw->usedma = 0;
0762     r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
0763     if (r) {
0764         hw->dma_tx_id = r->start;
0765         r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
0766         if (r) {
0767             hw->dma_rx_id = r->start;
0768             if (usedma && ddma_memid) {
0769                 if (pdev->dev.dma_mask == NULL)
0770                     dev_warn(&pdev->dev, "no dma mask\n");
0771                 else
0772                     hw->usedma = 1;
0773             }
0774         }
0775     }
0776 
0777     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0778     if (!r) {
0779         dev_err(&pdev->dev, "no mmio resource\n");
0780         err = -ENODEV;
0781         goto err_no_iores;
0782     }
0783 
0784     hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
0785                     pdev->name);
0786     if (!hw->ioarea) {
0787         dev_err(&pdev->dev, "Cannot reserve iomem region\n");
0788         err = -ENXIO;
0789         goto err_no_iores;
0790     }
0791 
0792     hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
0793     if (!hw->regs) {
0794         dev_err(&pdev->dev, "cannot ioremap\n");
0795         err = -ENXIO;
0796         goto err_ioremap;
0797     }
0798 
0799     platform_set_drvdata(pdev, hw);
0800 
0801     init_completion(&hw->master_done);
0802 
0803     hw->bitbang.master = hw->master;
0804     hw->bitbang.setup_transfer = au1550_spi_setupxfer;
0805     hw->bitbang.chipselect = au1550_spi_chipsel;
0806     hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
0807 
0808     if (hw->usedma) {
0809         hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
0810             hw->dma_tx_id, NULL, (void *)hw);
0811         if (hw->dma_tx_ch == 0) {
0812             dev_err(&pdev->dev,
0813                 "Cannot allocate tx dma channel\n");
0814             err = -ENXIO;
0815             goto err_no_txdma;
0816         }
0817         au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
0818         if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
0819             AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
0820             dev_err(&pdev->dev,
0821                 "Cannot allocate tx dma descriptors\n");
0822             err = -ENXIO;
0823             goto err_no_txdma_descr;
0824         }
0825 
0826 
0827         hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
0828             ddma_memid, NULL, (void *)hw);
0829         if (hw->dma_rx_ch == 0) {
0830             dev_err(&pdev->dev,
0831                 "Cannot allocate rx dma channel\n");
0832             err = -ENXIO;
0833             goto err_no_rxdma;
0834         }
0835         au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
0836         if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
0837             AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
0838             dev_err(&pdev->dev,
0839                 "Cannot allocate rx dma descriptors\n");
0840             err = -ENXIO;
0841             goto err_no_rxdma_descr;
0842         }
0843 
0844         err = au1550_spi_dma_rxtmp_alloc(hw,
0845             AU1550_SPI_DMA_RXTMP_MINSIZE);
0846         if (err < 0) {
0847             dev_err(&pdev->dev,
0848                 "Cannot allocate initial rx dma tmp buffer\n");
0849             goto err_dma_rxtmp_alloc;
0850         }
0851     }
0852 
0853     au1550_spi_bits_handlers_set(hw, 8);
0854 
0855     err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
0856     if (err) {
0857         dev_err(&pdev->dev, "Cannot claim IRQ\n");
0858         goto err_no_irq;
0859     }
0860 
0861     master->bus_num = pdev->id;
0862     master->num_chipselect = hw->pdata->num_chipselect;
0863 
0864     /*
0865      *  precompute valid range for spi freq - from au1550 datasheet:
0866      *    psc_tempclk = psc_mainclk / (2 << DIV)
0867      *    spiclk = psc_tempclk / (2 * (BRG + 1))
0868      *    BRG valid range is 4..63
0869      *    DIV valid range is 0..3
0870      *  round the min and max frequencies to values that would still
0871      *  produce valid brg and div
0872      */
0873     {
0874         int min_div = (2 << 0) * (2 * (4 + 1));
0875         int max_div = (2 << 3) * (2 * (63 + 1));
0876 
0877         master->max_speed_hz = hw->pdata->mainclk_hz / min_div;
0878         master->min_speed_hz =
0879                 hw->pdata->mainclk_hz / (max_div + 1) + 1;
0880     }
0881 
0882     au1550_spi_setup_psc_as_spi(hw);
0883 
0884     err = spi_bitbang_start(&hw->bitbang);
0885     if (err) {
0886         dev_err(&pdev->dev, "Failed to register SPI master\n");
0887         goto err_register;
0888     }
0889 
0890     dev_info(&pdev->dev,
0891         "spi master registered: bus_num=%d num_chipselect=%d\n",
0892         master->bus_num, master->num_chipselect);
0893 
0894     return 0;
0895 
0896 err_register:
0897     free_irq(hw->irq, hw);
0898 
0899 err_no_irq:
0900     au1550_spi_dma_rxtmp_free(hw);
0901 
0902 err_dma_rxtmp_alloc:
0903 err_no_rxdma_descr:
0904     if (hw->usedma)
0905         au1xxx_dbdma_chan_free(hw->dma_rx_ch);
0906 
0907 err_no_rxdma:
0908 err_no_txdma_descr:
0909     if (hw->usedma)
0910         au1xxx_dbdma_chan_free(hw->dma_tx_ch);
0911 
0912 err_no_txdma:
0913     iounmap((void __iomem *)hw->regs);
0914 
0915 err_ioremap:
0916     release_mem_region(r->start, sizeof(psc_spi_t));
0917 
0918 err_no_iores:
0919 err_no_pdata:
0920     spi_master_put(hw->master);
0921 
0922 err_nomem:
0923     return err;
0924 }
0925 
0926 static int au1550_spi_remove(struct platform_device *pdev)
0927 {
0928     struct au1550_spi *hw = platform_get_drvdata(pdev);
0929 
0930     dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
0931         hw->master->bus_num);
0932 
0933     spi_bitbang_stop(&hw->bitbang);
0934     free_irq(hw->irq, hw);
0935     iounmap((void __iomem *)hw->regs);
0936     release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
0937 
0938     if (hw->usedma) {
0939         au1550_spi_dma_rxtmp_free(hw);
0940         au1xxx_dbdma_chan_free(hw->dma_rx_ch);
0941         au1xxx_dbdma_chan_free(hw->dma_tx_ch);
0942     }
0943 
0944     spi_master_put(hw->master);
0945     return 0;
0946 }
0947 
0948 /* work with hotplug and coldplug */
0949 MODULE_ALIAS("platform:au1550-spi");
0950 
0951 static struct platform_driver au1550_spi_drv = {
0952     .probe = au1550_spi_probe,
0953     .remove = au1550_spi_remove,
0954     .driver = {
0955         .name = "au1550-spi",
0956     },
0957 };
0958 
0959 static int __init au1550_spi_init(void)
0960 {
0961     /*
0962      * create memory device with 8 bits dev_devwidth
0963      * needed for proper byte ordering to spi fifo
0964      */
0965     switch (alchemy_get_cputype()) {
0966     case ALCHEMY_CPU_AU1550:
0967     case ALCHEMY_CPU_AU1200:
0968     case ALCHEMY_CPU_AU1300:
0969         break;
0970     default:
0971         return -ENODEV;
0972     }
0973 
0974     if (usedma) {
0975         ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
0976         if (!ddma_memid)
0977             printk(KERN_ERR "au1550-spi: cannot add memory dbdma device\n");
0978     }
0979     return platform_driver_register(&au1550_spi_drv);
0980 }
0981 module_init(au1550_spi_init);
0982 
0983 static void __exit au1550_spi_exit(void)
0984 {
0985     if (usedma && ddma_memid)
0986         au1xxx_ddma_del_device(ddma_memid);
0987     platform_driver_unregister(&au1550_spi_drv);
0988 }
0989 module_exit(au1550_spi_exit);
0990 
0991 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
0992 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
0993 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!