drivers/spi/spi-ath79.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
0004  *
0005  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
0006  *
0007  * This driver has been based on the spi-gpio.c:
0008  *  Copyright (C) 2006,2008 David Brownell
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/delay.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/io.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/spi/spi-mem.h>
0019 #include <linux/spi/spi_bitbang.h>
0020 #include <linux/bitops.h>
0021 #include <linux/clk.h>
0022 #include <linux/err.h>
0023
0024 #define DRV_NAME    "ath79-spi"
0025
0026 #define ATH79_SPI_RRW_DELAY_FACTOR  12000
0027 #define MHZ             (1000 * 1000)
0028
0029 #define AR71XX_SPI_REG_FS       0x00    /* Function Select */
0030 #define AR71XX_SPI_REG_CTRL     0x04    /* SPI Control */
0031 #define AR71XX_SPI_REG_IOC      0x08    /* SPI I/O Control */
0032 #define AR71XX_SPI_REG_RDS      0x0c    /* Read Data Shift */
0033
0034 #define AR71XX_SPI_FS_GPIO      BIT(0)  /* Enable GPIO mode */
0035
0036 #define AR71XX_SPI_IOC_DO       BIT(0)  /* Data Out pin */
0037 #define AR71XX_SPI_IOC_CLK      BIT(8)  /* CLK pin */
0038 #define AR71XX_SPI_IOC_CS(n)        BIT(16 + (n))
0039
0040 struct ath79_spi {
0041     struct spi_bitbang  bitbang;
0042     u32         ioc_base;
0043     u32         reg_ctrl;
0044     void __iomem        *base;
0045     struct clk      *clk;
0046     unsigned int        rrw_delay;
0047 };
0048
0049 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
0050 {
0051     return ioread32(sp->base + reg);
0052 }
0053
0054 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
0055 {
0056     iowrite32(val, sp->base + reg);
0057 }
0058
0059 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
0060 {
0061     return spi_master_get_devdata(spi->master);
0062 }
0063
0064 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
0065 {
0066     if (nsecs > sp->rrw_delay)
0067         ndelay(nsecs - sp->rrw_delay);
0068 }
0069
0070 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
0071 {
0072     struct ath79_spi *sp = ath79_spidev_to_sp(spi);
0073     int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
0074     u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
0075
0076     if (cs_high)
0077         sp->ioc_base |= cs_bit;
0078     else
0079         sp->ioc_base &= ~cs_bit;
0080
0081     ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
0082 }
0083
0084 static void ath79_spi_enable(struct ath79_spi *sp)
0085 {
0086     /* enable GPIO mode */
0087     ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
0088
0089     /* save CTRL register */
0090     sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
0091     sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
0092
0093     /* clear clk and mosi in the base state */
0094     sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
0095
0096     /* TODO: setup speed? */
0097     ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
0098 }
0099
0100 static void ath79_spi_disable(struct ath79_spi *sp)
0101 {
0102     /* restore CTRL register */
0103     ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
0104     /* disable GPIO mode */
0105     ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
0106 }
0107
0108 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
0109                    u32 word, u8 bits, unsigned flags)
0110 {
0111     struct ath79_spi *sp = ath79_spidev_to_sp(spi);
0112     u32 ioc = sp->ioc_base;
0113
0114     /* clock starts at inactive polarity */
0115     for (word <<= (32 - bits); likely(bits); bits--) {
0116         u32 out;
0117
0118         if (word & (1 << 31))
0119             out = ioc | AR71XX_SPI_IOC_DO;
0120         else
0121             out = ioc & ~AR71XX_SPI_IOC_DO;
0122
0123         /* setup MSB (to slave) on trailing edge */
0124         ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
0125         ath79_spi_delay(sp, nsecs);
0126         ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
0127         ath79_spi_delay(sp, nsecs);
0128         if (bits == 1)
0129             ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
0130
0131         word <<= 1;
0132     }
0133
0134     return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
0135 }
0136
0137 static int ath79_exec_mem_op(struct spi_mem *mem,
0138                  const struct spi_mem_op *op)
0139 {
0140     struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
0141
0142     /* Ensures that reading is performed on device connected to hardware cs0 */
0143     if (mem->spi->chip_select || mem->spi->cs_gpiod)
0144         return -ENOTSUPP;
0145
0146     /* Only use for fast-read op. */
0147     if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||
0148         op->addr.nbytes != 3 || op->dummy.nbytes != 1)
0149         return -ENOTSUPP;
0150
0151     /* disable GPIO mode */
0152     ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
0153
0154     memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);
0155
0156     /* enable GPIO mode */
0157     ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
0158
0159     /* restore IOC register */
0160     ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
0161
0162     return 0;
0163 }
0164
0165 static const struct spi_controller_mem_ops ath79_mem_ops = {
0166     .exec_op = ath79_exec_mem_op,
0167 };
0168
0169 static int ath79_spi_probe(struct platform_device *pdev)
0170 {
0171     struct spi_master *master;
0172     struct ath79_spi *sp;
0173     unsigned long rate;
0174     int ret;
0175
0176     master = spi_alloc_master(&pdev->dev, sizeof(*sp));
0177     if (master == NULL) {
0178         dev_err(&pdev->dev, "failed to allocate spi master\n");
0179         return -ENOMEM;
0180     }
0181
0182     sp = spi_master_get_devdata(master);
0183     master->dev.of_node = pdev->dev.of_node;
0184     platform_set_drvdata(pdev, sp);
0185
0186     master->use_gpio_descriptors = true;
0187     master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
0188     master->flags = SPI_MASTER_GPIO_SS;
0189     master->num_chipselect = 3;
0190     master->mem_ops = &ath79_mem_ops;
0191
0192     sp->bitbang.master = master;
0193     sp->bitbang.chipselect = ath79_spi_chipselect;
0194     sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
0195     sp->bitbang.flags = SPI_CS_HIGH;
0196
0197     sp->base = devm_platform_ioremap_resource(pdev, 0);
0198     if (IS_ERR(sp->base)) {
0199         ret = PTR_ERR(sp->base);
0200         goto err_put_master;
0201     }
0202
0203     sp->clk = devm_clk_get(&pdev->dev, "ahb");
0204     if (IS_ERR(sp->clk)) {
0205         ret = PTR_ERR(sp->clk);
0206         goto err_put_master;
0207     }
0208
0209     ret = clk_prepare_enable(sp->clk);
0210     if (ret)
0211         goto err_put_master;
0212
0213     rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
0214     if (!rate) {
0215         ret = -EINVAL;
0216         goto err_clk_disable;
0217     }
0218
0219     sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
0220     dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
0221         sp->rrw_delay);
0222
0223     ath79_spi_enable(sp);
0224     ret = spi_bitbang_start(&sp->bitbang);
0225     if (ret)
0226         goto err_disable;
0227
0228     return 0;
0229
0230 err_disable:
0231     ath79_spi_disable(sp);
0232 err_clk_disable:
0233     clk_disable_unprepare(sp->clk);
0234 err_put_master:
0235     spi_master_put(sp->bitbang.master);
0236
0237     return ret;
0238 }
0239
0240 static int ath79_spi_remove(struct platform_device *pdev)
0241 {
0242     struct ath79_spi *sp = platform_get_drvdata(pdev);
0243
0244     spi_bitbang_stop(&sp->bitbang);
0245     ath79_spi_disable(sp);
0246     clk_disable_unprepare(sp->clk);
0247     spi_master_put(sp->bitbang.master);
0248
0249     return 0;
0250 }
0251
0252 static void ath79_spi_shutdown(struct platform_device *pdev)
0253 {
0254     ath79_spi_remove(pdev);
0255 }
0256
0257 static const struct of_device_id ath79_spi_of_match[] = {
0258     { .compatible = "qca,ar7100-spi", },
0259     { },
0260 };
0261 MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
0262
0263 static struct platform_driver ath79_spi_driver = {
0264     .probe      = ath79_spi_probe,
0265     .remove     = ath79_spi_remove,
0266     .shutdown   = ath79_spi_shutdown,
0267     .driver     = {
0268         .name   = DRV_NAME,
0269         .of_match_table = ath79_spi_of_match,
0270     },
0271 };
0272 module_platform_driver(ath79_spi_driver);
0273
0274 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
0275 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
0276 MODULE_LICENSE("GPL v2");
0277 MODULE_ALIAS("platform:" DRV_NAME);