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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * ASPEED FMC/SPI Memory Controller Driver
0004  *
0005  * Copyright (c) 2015-2022, IBM Corporation.
0006  * Copyright (c) 2020, ASPEED Corporation.
0007  */
0008 
0009 #include <linux/clk.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_platform.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spi/spi.h>
0015 #include <linux/spi/spi-mem.h>
0016 
0017 #define DEVICE_NAME "spi-aspeed-smc"
0018 
0019 /* Type setting Register */
0020 #define CONFIG_REG          0x0
0021 #define   CONFIG_TYPE_SPI       0x2
0022 
0023 /* CE Control Register */
0024 #define CE_CTRL_REG         0x4
0025 
0026 /* CEx Control Register */
0027 #define CE0_CTRL_REG            0x10
0028 #define   CTRL_IO_MODE_MASK     GENMASK(30, 28)
0029 #define   CTRL_IO_SINGLE_DATA           0x0
0030 #define   CTRL_IO_DUAL_DATA     BIT(29)
0031 #define   CTRL_IO_QUAD_DATA     BIT(30)
0032 #define   CTRL_COMMAND_SHIFT        16
0033 #define   CTRL_IO_ADDRESS_4B        BIT(13) /* AST2400 SPI only */
0034 #define   CTRL_IO_DUMMY_SET(dummy)                  \
0035     (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
0036 #define   CTRL_FREQ_SEL_SHIFT       8
0037 #define   CTRL_FREQ_SEL_MASK        GENMASK(11, CTRL_FREQ_SEL_SHIFT)
0038 #define   CTRL_CE_STOP_ACTIVE       BIT(2)
0039 #define   CTRL_IO_MODE_CMD_MASK     GENMASK(1, 0)
0040 #define   CTRL_IO_MODE_NORMAL       0x0
0041 #define   CTRL_IO_MODE_READ     0x1
0042 #define   CTRL_IO_MODE_WRITE        0x2
0043 #define   CTRL_IO_MODE_USER     0x3
0044 
0045 #define   CTRL_IO_CMD_MASK      0xf0ff40c3
0046 
0047 /* CEx Address Decoding Range Register */
0048 #define CE0_SEGMENT_ADDR_REG        0x30
0049 
0050 /* CEx Read timing compensation register */
0051 #define CE0_TIMING_COMPENSATION_REG 0x94
0052 
0053 enum aspeed_spi_ctl_reg_value {
0054     ASPEED_SPI_BASE,
0055     ASPEED_SPI_READ,
0056     ASPEED_SPI_WRITE,
0057     ASPEED_SPI_MAX,
0058 };
0059 
0060 struct aspeed_spi;
0061 
0062 struct aspeed_spi_chip {
0063     struct aspeed_spi   *aspi;
0064     u32          cs;
0065     void __iomem        *ctl;
0066     void __iomem        *ahb_base;
0067     u32          ahb_window_size;
0068     u32          ctl_val[ASPEED_SPI_MAX];
0069     u32          clk_freq;
0070 };
0071 
0072 struct aspeed_spi_data {
0073     u32 ctl0;
0074     u32 max_cs;
0075     bool    hastype;
0076     u32 mode_bits;
0077     u32 we0;
0078     u32 timing;
0079     u32 hclk_mask;
0080     u32 hdiv_max;
0081 
0082     u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
0083     u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
0084     u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
0085     int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
0086              const u8 *golden_buf, u8 *test_buf);
0087 };
0088 
0089 #define ASPEED_SPI_MAX_NUM_CS   5
0090 
0091 struct aspeed_spi {
0092     const struct aspeed_spi_data    *data;
0093 
0094     void __iomem        *regs;
0095     void __iomem        *ahb_base;
0096     u32          ahb_base_phy;
0097     u32          ahb_window_size;
0098     struct device       *dev;
0099 
0100     struct clk      *clk;
0101     u32          clk_freq;
0102 
0103     struct aspeed_spi_chip   chips[ASPEED_SPI_MAX_NUM_CS];
0104 };
0105 
0106 static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
0107 {
0108     switch (op->data.buswidth) {
0109     case 1:
0110         return CTRL_IO_SINGLE_DATA;
0111     case 2:
0112         return CTRL_IO_DUAL_DATA;
0113     case 4:
0114         return CTRL_IO_QUAD_DATA;
0115     default:
0116         return CTRL_IO_SINGLE_DATA;
0117     }
0118 }
0119 
0120 static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
0121 {
0122     u32 ctl;
0123 
0124     if (io_mode > 0) {
0125         ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
0126         ctl |= io_mode;
0127         writel(ctl, chip->ctl);
0128     }
0129 }
0130 
0131 static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
0132 {
0133     u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
0134 
0135     ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
0136     writel(ctl, chip->ctl);
0137 
0138     ctl &= ~CTRL_CE_STOP_ACTIVE;
0139     writel(ctl, chip->ctl);
0140 }
0141 
0142 static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
0143 {
0144     u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
0145         CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
0146 
0147     writel(ctl, chip->ctl);
0148 
0149     /* Restore defaults */
0150     writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
0151 }
0152 
0153 static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
0154 {
0155     size_t offset = 0;
0156 
0157     if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
0158         IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
0159         ioread32_rep(src, buf, len >> 2);
0160         offset = len & ~0x3;
0161         len -= offset;
0162     }
0163     ioread8_rep(src, (u8 *)buf + offset, len);
0164     return 0;
0165 }
0166 
0167 static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
0168 {
0169     size_t offset = 0;
0170 
0171     if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
0172         IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
0173         iowrite32_rep(dst, buf, len >> 2);
0174         offset = len & ~0x3;
0175         len -= offset;
0176     }
0177     iowrite8_rep(dst, (const u8 *)buf + offset, len);
0178     return 0;
0179 }
0180 
0181 static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
0182                     u64 offset, u32 opcode)
0183 {
0184     __be32 temp;
0185     u32 cmdaddr;
0186 
0187     switch (addr_nbytes) {
0188     case 3:
0189         cmdaddr = offset & 0xFFFFFF;
0190         cmdaddr |= opcode << 24;
0191 
0192         temp = cpu_to_be32(cmdaddr);
0193         aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
0194         break;
0195     case 4:
0196         temp = cpu_to_be32(offset);
0197         aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
0198         aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
0199         break;
0200     default:
0201         WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
0202         return -EOPNOTSUPP;
0203     }
0204     return 0;
0205 }
0206 
0207 static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
0208                    const struct spi_mem_op *op)
0209 {
0210     aspeed_spi_start_user(chip);
0211     aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
0212     aspeed_spi_read_from_ahb(op->data.buf.in,
0213                  chip->ahb_base, op->data.nbytes);
0214     aspeed_spi_stop_user(chip);
0215     return 0;
0216 }
0217 
0218 static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
0219                 const struct spi_mem_op *op)
0220 {
0221     aspeed_spi_start_user(chip);
0222     aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
0223     aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
0224                 op->data.nbytes);
0225     aspeed_spi_stop_user(chip);
0226     return 0;
0227 }
0228 
0229 static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
0230                     const struct spi_mem_op *op,
0231                     u64 offset, size_t len, void *buf)
0232 {
0233     int io_mode = aspeed_spi_get_io_mode(op);
0234     u8 dummy = 0xFF;
0235     int i;
0236     int ret;
0237 
0238     aspeed_spi_start_user(chip);
0239 
0240     ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
0241     if (ret < 0)
0242         return ret;
0243 
0244     if (op->dummy.buswidth && op->dummy.nbytes) {
0245         for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
0246             aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
0247     }
0248 
0249     aspeed_spi_set_io_mode(chip, io_mode);
0250 
0251     aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
0252     aspeed_spi_stop_user(chip);
0253     return 0;
0254 }
0255 
0256 static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
0257                      const struct spi_mem_op *op)
0258 {
0259     int ret;
0260 
0261     aspeed_spi_start_user(chip);
0262     ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
0263     if (ret < 0)
0264         return ret;
0265     aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
0266     aspeed_spi_stop_user(chip);
0267     return 0;
0268 }
0269 
0270 /* support for 1-1-1, 1-1-2 or 1-1-4 */
0271 static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
0272 {
0273     if (op->cmd.buswidth > 1)
0274         return false;
0275 
0276     if (op->addr.nbytes != 0) {
0277         if (op->addr.buswidth > 1)
0278             return false;
0279         if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
0280             return false;
0281     }
0282 
0283     if (op->dummy.nbytes != 0) {
0284         if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
0285             return false;
0286     }
0287 
0288     if (op->data.nbytes != 0 && op->data.buswidth > 4)
0289         return false;
0290 
0291     return spi_mem_default_supports_op(mem, op);
0292 }
0293 
0294 static const struct aspeed_spi_data ast2400_spi_data;
0295 
0296 static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
0297 {
0298     struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
0299     struct aspeed_spi_chip *chip = &aspi->chips[mem->spi->chip_select];
0300     u32 addr_mode, addr_mode_backup;
0301     u32 ctl_val;
0302     int ret = 0;
0303 
0304     dev_dbg(aspi->dev,
0305         "CE%d %s OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x len:%#x",
0306         chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
0307         op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
0308         op->dummy.buswidth, op->data.buswidth,
0309         op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
0310 
0311     addr_mode = readl(aspi->regs + CE_CTRL_REG);
0312     addr_mode_backup = addr_mode;
0313 
0314     ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
0315     ctl_val &= ~CTRL_IO_CMD_MASK;
0316 
0317     ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
0318 
0319     /* 4BYTE address mode */
0320     if (op->addr.nbytes) {
0321         if (op->addr.nbytes == 4)
0322             addr_mode |= (0x11 << chip->cs);
0323         else
0324             addr_mode &= ~(0x11 << chip->cs);
0325 
0326         if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
0327             ctl_val |= CTRL_IO_ADDRESS_4B;
0328     }
0329 
0330     if (op->dummy.nbytes)
0331         ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
0332 
0333     if (op->data.nbytes)
0334         ctl_val |= aspeed_spi_get_io_mode(op);
0335 
0336     if (op->data.dir == SPI_MEM_DATA_OUT)
0337         ctl_val |= CTRL_IO_MODE_WRITE;
0338     else
0339         ctl_val |= CTRL_IO_MODE_READ;
0340 
0341     if (addr_mode != addr_mode_backup)
0342         writel(addr_mode, aspi->regs + CE_CTRL_REG);
0343     writel(ctl_val, chip->ctl);
0344 
0345     if (op->data.dir == SPI_MEM_DATA_IN) {
0346         if (!op->addr.nbytes)
0347             ret = aspeed_spi_read_reg(chip, op);
0348         else
0349             ret = aspeed_spi_read_user(chip, op, op->addr.val,
0350                            op->data.nbytes, op->data.buf.in);
0351     } else {
0352         if (!op->addr.nbytes)
0353             ret = aspeed_spi_write_reg(chip, op);
0354         else
0355             ret = aspeed_spi_write_user(chip, op);
0356     }
0357 
0358     /* Restore defaults */
0359     if (addr_mode != addr_mode_backup)
0360         writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
0361     writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
0362     return ret;
0363 }
0364 
0365 static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
0366 {
0367     int ret;
0368 
0369     ret = do_aspeed_spi_exec_op(mem, op);
0370     if (ret)
0371         dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
0372     return ret;
0373 }
0374 
0375 static const char *aspeed_spi_get_name(struct spi_mem *mem)
0376 {
0377     struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
0378     struct device *dev = aspi->dev;
0379 
0380     return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select);
0381 }
0382 
0383 struct aspeed_spi_window {
0384     u32 cs;
0385     u32 offset;
0386     u32 size;
0387 };
0388 
0389 static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
0390                    struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS])
0391 {
0392     const struct aspeed_spi_data *data = aspi->data;
0393     u32 reg_val;
0394     u32 cs;
0395 
0396     for (cs = 0; cs < aspi->data->max_cs; cs++) {
0397         reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
0398         windows[cs].cs = cs;
0399         windows[cs].size = data->segment_end(aspi, reg_val) -
0400             data->segment_start(aspi, reg_val);
0401         windows[cs].offset = cs ? windows[cs - 1].offset + windows[cs - 1].size : 0;
0402         dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
0403              windows[cs].offset, windows[cs].size);
0404     }
0405 }
0406 
0407 /*
0408  * On the AST2600, some CE windows are closed by default at reset but
0409  * U-Boot should open all.
0410  */
0411 static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
0412 {
0413     struct aspeed_spi *aspi = chip->aspi;
0414     struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
0415     struct aspeed_spi_window *win = &windows[chip->cs];
0416 
0417     /* No segment registers for the AST2400 SPI controller */
0418     if (aspi->data == &ast2400_spi_data) {
0419         win->offset = 0;
0420         win->size = aspi->ahb_window_size;
0421     } else {
0422         aspeed_spi_get_windows(aspi, windows);
0423     }
0424 
0425     chip->ahb_base = aspi->ahb_base + win->offset;
0426     chip->ahb_window_size = win->size;
0427 
0428     dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
0429         chip->cs, aspi->ahb_base_phy + win->offset,
0430         aspi->ahb_base_phy + win->offset + win->size - 1,
0431         win->size >> 20);
0432 
0433     return chip->ahb_window_size ? 0 : -1;
0434 }
0435 
0436 static int aspeed_spi_set_window(struct aspeed_spi *aspi,
0437                  const struct aspeed_spi_window *win)
0438 {
0439     u32 start = aspi->ahb_base_phy + win->offset;
0440     u32 end = start + win->size;
0441     void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
0442     u32 seg_val_backup = readl(seg_reg);
0443     u32 seg_val = aspi->data->segment_reg(aspi, start, end);
0444 
0445     if (seg_val == seg_val_backup)
0446         return 0;
0447 
0448     writel(seg_val, seg_reg);
0449 
0450     /*
0451      * Restore initial value if something goes wrong else we could
0452      * loose access to the chip.
0453      */
0454     if (seg_val != readl(seg_reg)) {
0455         dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
0456             win->cs, start, end - 1, win->size >> 20);
0457         writel(seg_val_backup, seg_reg);
0458         return -EIO;
0459     }
0460 
0461     if (win->size)
0462         dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
0463             win->cs, start, end - 1,  win->size >> 20);
0464     else
0465         dev_dbg(aspi->dev, "CE%d window closed", win->cs);
0466 
0467     return 0;
0468 }
0469 
0470 /*
0471  * Yet to be done when possible :
0472  * - Align mappings on flash size (we don't have the info)
0473  * - ioremap each window, not strictly necessary since the overall window
0474  *   is correct.
0475  */
0476 static const struct aspeed_spi_data ast2500_spi_data;
0477 static const struct aspeed_spi_data ast2600_spi_data;
0478 static const struct aspeed_spi_data ast2600_fmc_data;
0479 
0480 static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
0481                      u32 local_offset, u32 size)
0482 {
0483     struct aspeed_spi *aspi = chip->aspi;
0484     struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
0485     struct aspeed_spi_window *win = &windows[chip->cs];
0486     int ret;
0487 
0488     /* No segment registers for the AST2400 SPI controller */
0489     if (aspi->data == &ast2400_spi_data)
0490         return 0;
0491 
0492     /*
0493      * Due to an HW issue on the AST2500 SPI controller, the CE0
0494      * window size should be smaller than the maximum 128MB.
0495      */
0496     if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
0497         size = 120 << 20;
0498         dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
0499              chip->cs, size >> 20);
0500     }
0501 
0502     /*
0503      * The decoding size of AST2600 SPI controller should set at
0504      * least 2MB.
0505      */
0506     if ((aspi->data == &ast2600_spi_data || aspi->data == &ast2600_fmc_data) &&
0507         size < SZ_2M) {
0508         size = SZ_2M;
0509         dev_info(aspi->dev, "CE%d window resized to %dMB (AST2600 Decoding)",
0510              chip->cs, size >> 20);
0511     }
0512 
0513     aspeed_spi_get_windows(aspi, windows);
0514 
0515     /* Adjust this chip window */
0516     win->offset += local_offset;
0517     win->size = size;
0518 
0519     if (win->offset + win->size > aspi->ahb_window_size) {
0520         win->size = aspi->ahb_window_size - win->offset;
0521         dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
0522     }
0523 
0524     ret = aspeed_spi_set_window(aspi, win);
0525     if (ret)
0526         return ret;
0527 
0528     /* Update chip mapping info */
0529     chip->ahb_base = aspi->ahb_base + win->offset;
0530     chip->ahb_window_size = win->size;
0531 
0532     /*
0533      * Also adjust next chip window to make sure that it does not
0534      * overlap with the current window.
0535      */
0536     if (chip->cs < aspi->data->max_cs - 1) {
0537         struct aspeed_spi_window *next = &windows[chip->cs + 1];
0538 
0539         /* Change offset and size to keep the same end address */
0540         if ((next->offset + next->size) > (win->offset + win->size))
0541             next->size = (next->offset + next->size) - (win->offset + win->size);
0542         else
0543             next->size = 0;
0544         next->offset = win->offset + win->size;
0545 
0546         aspeed_spi_set_window(aspi, next);
0547     }
0548     return 0;
0549 }
0550 
0551 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
0552 
0553 static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
0554 {
0555     struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
0556     struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
0557     struct spi_mem_op *op = &desc->info.op_tmpl;
0558     u32 ctl_val;
0559     int ret = 0;
0560 
0561     dev_dbg(aspi->dev,
0562         "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n",
0563         chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
0564         desc->info.offset, desc->info.offset + desc->info.length,
0565         op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
0566         op->dummy.buswidth, op->data.buswidth,
0567         op->addr.nbytes, op->dummy.nbytes);
0568 
0569     chip->clk_freq = desc->mem->spi->max_speed_hz;
0570 
0571     /* Only for reads */
0572     if (op->data.dir != SPI_MEM_DATA_IN)
0573         return -EOPNOTSUPP;
0574 
0575     aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
0576 
0577     if (desc->info.length > chip->ahb_window_size)
0578         dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
0579              chip->cs, chip->ahb_window_size >> 20);
0580 
0581     /* Define the default IO read settings */
0582     ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
0583     ctl_val |= aspeed_spi_get_io_mode(op) |
0584         op->cmd.opcode << CTRL_COMMAND_SHIFT |
0585         CTRL_IO_MODE_READ;
0586 
0587     if (op->dummy.nbytes)
0588         ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
0589 
0590     /* Tune 4BYTE address mode */
0591     if (op->addr.nbytes) {
0592         u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
0593 
0594         if (op->addr.nbytes == 4)
0595             addr_mode |= (0x11 << chip->cs);
0596         else
0597             addr_mode &= ~(0x11 << chip->cs);
0598         writel(addr_mode, aspi->regs + CE_CTRL_REG);
0599 
0600         /* AST2400 SPI controller sets 4BYTE address mode in
0601          * CE0 Control Register
0602          */
0603         if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
0604             ctl_val |= CTRL_IO_ADDRESS_4B;
0605     }
0606 
0607     /* READ mode is the controller default setting */
0608     chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
0609     writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
0610 
0611     ret = aspeed_spi_do_calibration(chip);
0612 
0613     dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
0614          chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
0615 
0616     return ret;
0617 }
0618 
0619 static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
0620                       u64 offset, size_t len, void *buf)
0621 {
0622     struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
0623     struct aspeed_spi_chip *chip = &aspi->chips[desc->mem->spi->chip_select];
0624 
0625     /* Switch to USER command mode if mapping window is too small */
0626     if (chip->ahb_window_size < offset + len) {
0627         int ret;
0628 
0629         ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
0630         if (ret < 0)
0631             return ret;
0632     } else {
0633         memcpy_fromio(buf, chip->ahb_base + offset, len);
0634     }
0635 
0636     return len;
0637 }
0638 
0639 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
0640     .supports_op = aspeed_spi_supports_op,
0641     .exec_op = aspeed_spi_exec_op,
0642     .get_name = aspeed_spi_get_name,
0643     .dirmap_create = aspeed_spi_dirmap_create,
0644     .dirmap_read = aspeed_spi_dirmap_read,
0645 };
0646 
0647 static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
0648 {
0649     u32 reg;
0650 
0651     reg = readl(aspi->regs + CONFIG_REG);
0652     reg &= ~(0x3 << (cs * 2));
0653     reg |= type << (cs * 2);
0654     writel(reg, aspi->regs + CONFIG_REG);
0655 }
0656 
0657 static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
0658 {
0659     u32 we_bit = BIT(aspi->data->we0 + cs);
0660     u32 reg = readl(aspi->regs + CONFIG_REG);
0661 
0662     if (enable)
0663         reg |= we_bit;
0664     else
0665         reg &= ~we_bit;
0666     writel(reg, aspi->regs + CONFIG_REG);
0667 }
0668 
0669 static int aspeed_spi_setup(struct spi_device *spi)
0670 {
0671     struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
0672     const struct aspeed_spi_data *data = aspi->data;
0673     unsigned int cs = spi->chip_select;
0674     struct aspeed_spi_chip *chip = &aspi->chips[cs];
0675 
0676     chip->aspi = aspi;
0677     chip->cs = cs;
0678     chip->ctl = aspi->regs + data->ctl0 + cs * 4;
0679 
0680     /* The driver only supports SPI type flash */
0681     if (data->hastype)
0682         aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
0683 
0684     if (aspeed_spi_chip_set_default_window(chip) < 0) {
0685         dev_warn(aspi->dev, "CE%d window invalid", cs);
0686         return -EINVAL;
0687     }
0688 
0689     aspeed_spi_chip_enable(aspi, cs, true);
0690 
0691     chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
0692 
0693     dev_dbg(aspi->dev, "CE%d setup done\n", cs);
0694     return 0;
0695 }
0696 
0697 static void aspeed_spi_cleanup(struct spi_device *spi)
0698 {
0699     struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
0700     unsigned int cs = spi->chip_select;
0701 
0702     aspeed_spi_chip_enable(aspi, cs, false);
0703 
0704     dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
0705 }
0706 
0707 static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
0708 {
0709     int cs;
0710 
0711     for (cs = 0; cs < aspi->data->max_cs; cs++)
0712         aspeed_spi_chip_enable(aspi, cs, enable);
0713 }
0714 
0715 static int aspeed_spi_probe(struct platform_device *pdev)
0716 {
0717     struct device *dev = &pdev->dev;
0718     const struct aspeed_spi_data *data;
0719     struct spi_controller *ctlr;
0720     struct aspeed_spi *aspi;
0721     struct resource *res;
0722     int ret;
0723 
0724     data = of_device_get_match_data(&pdev->dev);
0725     if (!data)
0726         return -ENODEV;
0727 
0728     ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
0729     if (!ctlr)
0730         return -ENOMEM;
0731 
0732     aspi = spi_controller_get_devdata(ctlr);
0733     platform_set_drvdata(pdev, aspi);
0734     aspi->data = data;
0735     aspi->dev = dev;
0736 
0737     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0738     aspi->regs = devm_ioremap_resource(dev, res);
0739     if (IS_ERR(aspi->regs)) {
0740         dev_err(dev, "missing AHB register window\n");
0741         return PTR_ERR(aspi->regs);
0742     }
0743 
0744     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0745     aspi->ahb_base = devm_ioremap_resource(dev, res);
0746     if (IS_ERR(aspi->ahb_base)) {
0747         dev_err(dev, "missing AHB mapping window\n");
0748         return PTR_ERR(aspi->ahb_base);
0749     }
0750 
0751     aspi->ahb_window_size = resource_size(res);
0752     aspi->ahb_base_phy = res->start;
0753 
0754     aspi->clk = devm_clk_get(&pdev->dev, NULL);
0755     if (IS_ERR(aspi->clk)) {
0756         dev_err(dev, "missing clock\n");
0757         return PTR_ERR(aspi->clk);
0758     }
0759 
0760     aspi->clk_freq = clk_get_rate(aspi->clk);
0761     if (!aspi->clk_freq) {
0762         dev_err(dev, "invalid clock\n");
0763         return -EINVAL;
0764     }
0765 
0766     ret = clk_prepare_enable(aspi->clk);
0767     if (ret) {
0768         dev_err(dev, "can not enable the clock\n");
0769         return ret;
0770     }
0771 
0772     /* IRQ is for DMA, which the driver doesn't support yet */
0773 
0774     ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
0775     ctlr->bus_num = pdev->id;
0776     ctlr->mem_ops = &aspeed_spi_mem_ops;
0777     ctlr->setup = aspeed_spi_setup;
0778     ctlr->cleanup = aspeed_spi_cleanup;
0779     ctlr->num_chipselect = data->max_cs;
0780     ctlr->dev.of_node = dev->of_node;
0781 
0782     ret = devm_spi_register_controller(dev, ctlr);
0783     if (ret) {
0784         dev_err(&pdev->dev, "spi_register_controller failed\n");
0785         goto disable_clk;
0786     }
0787     return 0;
0788 
0789 disable_clk:
0790     clk_disable_unprepare(aspi->clk);
0791     return ret;
0792 }
0793 
0794 static int aspeed_spi_remove(struct platform_device *pdev)
0795 {
0796     struct aspeed_spi *aspi = platform_get_drvdata(pdev);
0797 
0798     aspeed_spi_enable(aspi, false);
0799     clk_disable_unprepare(aspi->clk);
0800     return 0;
0801 }
0802 
0803 /*
0804  * AHB mappings
0805  */
0806 
0807 /*
0808  * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
0809  * The address range is encoded with absolute addresses in the overall
0810  * mapping window.
0811  */
0812 static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
0813 {
0814     return ((reg >> 16) & 0xFF) << 23;
0815 }
0816 
0817 static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
0818 {
0819     return ((reg >> 24) & 0xFF) << 23;
0820 }
0821 
0822 static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
0823 {
0824     return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
0825 }
0826 
0827 /*
0828  * The Segment Registers of the AST2600 use a 1MB unit. The address
0829  * range is encoded with offsets in the overall mapping window.
0830  */
0831 
0832 #define AST2600_SEG_ADDR_MASK 0x0ff00000
0833 
0834 static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
0835                         u32 reg)
0836 {
0837     u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
0838 
0839     return aspi->ahb_base_phy + start_offset;
0840 }
0841 
0842 static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
0843                       u32 reg)
0844 {
0845     u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
0846 
0847     /* segment is disabled */
0848     if (!end_offset)
0849         return aspi->ahb_base_phy;
0850 
0851     return aspi->ahb_base_phy + end_offset + 0x100000;
0852 }
0853 
0854 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
0855                       u32 start, u32 end)
0856 {
0857     /* disable zero size segments */
0858     if (start == end)
0859         return 0;
0860 
0861     return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
0862         ((end - 1) & AST2600_SEG_ADDR_MASK);
0863 }
0864 
0865 /*
0866  * Read timing compensation sequences
0867  */
0868 
0869 #define CALIBRATE_BUF_SIZE SZ_16K
0870 
0871 static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
0872                    const u8 *golden_buf, u8 *test_buf)
0873 {
0874     int i;
0875 
0876     for (i = 0; i < 10; i++) {
0877         memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
0878         if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
0879 #if defined(VERBOSE_DEBUG)
0880             print_hex_dump_bytes(DEVICE_NAME "  fail: ", DUMP_PREFIX_NONE,
0881                          test_buf, 0x100);
0882 #endif
0883             return false;
0884         }
0885     }
0886     return true;
0887 }
0888 
0889 #define FREAD_TPASS(i)  (((i) / 2) | (((i) & 1) ? 0 : 8))
0890 
0891 /*
0892  * The timing register is shared by all devices. Only update for CE0.
0893  */
0894 static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
0895                 const u8 *golden_buf, u8 *test_buf)
0896 {
0897     struct aspeed_spi *aspi = chip->aspi;
0898     const struct aspeed_spi_data *data = aspi->data;
0899     int i;
0900     int good_pass = -1, pass_count = 0;
0901     u32 shift = (hdiv - 1) << 2;
0902     u32 mask = ~(0xfu << shift);
0903     u32 fread_timing_val = 0;
0904 
0905     /* Try HCLK delay 0..5, each one with/without delay and look for a
0906      * good pair.
0907      */
0908     for (i = 0; i < 12; i++) {
0909         bool pass;
0910 
0911         if (chip->cs == 0) {
0912             fread_timing_val &= mask;
0913             fread_timing_val |= FREAD_TPASS(i) << shift;
0914             writel(fread_timing_val, aspi->regs + data->timing);
0915         }
0916         pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
0917         dev_dbg(aspi->dev,
0918             "  * [%08x] %d HCLK delay, %dns DI delay : %s",
0919             fread_timing_val, i / 2, (i & 1) ? 0 : 4,
0920             pass ? "PASS" : "FAIL");
0921         if (pass) {
0922             pass_count++;
0923             if (pass_count == 3) {
0924                 good_pass = i - 1;
0925                 break;
0926             }
0927         } else {
0928             pass_count = 0;
0929         }
0930     }
0931 
0932     /* No good setting for this frequency */
0933     if (good_pass < 0)
0934         return -1;
0935 
0936     /* We have at least one pass of margin, let's use first pass */
0937     if (chip->cs == 0) {
0938         fread_timing_val &= mask;
0939         fread_timing_val |= FREAD_TPASS(good_pass) << shift;
0940         writel(fread_timing_val, aspi->regs + data->timing);
0941     }
0942     dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
0943         good_pass, fread_timing_val);
0944     return 0;
0945 }
0946 
0947 static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
0948 {
0949     const u32 *tb32 = (const u32 *)test_buf;
0950     u32 i, cnt = 0;
0951 
0952     /* We check if we have enough words that are neither all 0
0953      * nor all 1's so the calibration can be considered valid.
0954      *
0955      * I use an arbitrary threshold for now of 64
0956      */
0957     size >>= 2;
0958     for (i = 0; i < size; i++) {
0959         if (tb32[i] != 0 && tb32[i] != 0xffffffff)
0960             cnt++;
0961     }
0962     return cnt >= 64;
0963 }
0964 
0965 static const u32 aspeed_spi_hclk_divs[] = {
0966     0xf, /* HCLK */
0967     0x7, /* HCLK/2 */
0968     0xe, /* HCLK/3 */
0969     0x6, /* HCLK/4 */
0970     0xd, /* HCLK/5 */
0971 };
0972 
0973 #define ASPEED_SPI_HCLK_DIV(i) \
0974     (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
0975 
0976 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
0977 {
0978     struct aspeed_spi *aspi = chip->aspi;
0979     const struct aspeed_spi_data *data = aspi->data;
0980     u32 ahb_freq = aspi->clk_freq;
0981     u32 max_freq = chip->clk_freq;
0982     u32 ctl_val;
0983     u8 *golden_buf = NULL;
0984     u8 *test_buf = NULL;
0985     int i, rc, best_div = -1;
0986 
0987     dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
0988         ahb_freq / 1000000);
0989 
0990     /*
0991      * use the related low frequency to get check calibration data
0992      * and get golden data.
0993      */
0994     ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
0995     writel(ctl_val, chip->ctl);
0996 
0997     test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
0998     if (!test_buf)
0999         return -ENOMEM;
1000 
1001     golden_buf = test_buf + CALIBRATE_BUF_SIZE;
1002 
1003     memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
1004     if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
1005         dev_info(aspi->dev, "Calibration area too uniform, using low speed");
1006         goto no_calib;
1007     }
1008 
1009 #if defined(VERBOSE_DEBUG)
1010     print_hex_dump_bytes(DEVICE_NAME "  good: ", DUMP_PREFIX_NONE,
1011                  golden_buf, 0x100);
1012 #endif
1013 
1014     /* Now we iterate the HCLK dividers until we find our breaking point */
1015     for (i = ARRAY_SIZE(aspeed_spi_hclk_divs); i > data->hdiv_max - 1; i--) {
1016         u32 tv, freq;
1017 
1018         freq = ahb_freq / i;
1019         if (freq > max_freq)
1020             continue;
1021 
1022         /* Set the timing */
1023         tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
1024         writel(tv, chip->ctl);
1025         dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
1026         rc = data->calibrate(chip, i, golden_buf, test_buf);
1027         if (rc == 0)
1028             best_div = i;
1029     }
1030 
1031     /* Nothing found ? */
1032     if (best_div < 0) {
1033         dev_warn(aspi->dev, "No good frequency, using dumb slow");
1034     } else {
1035         dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
1036 
1037         /* Record the freq */
1038         for (i = 0; i < ASPEED_SPI_MAX; i++)
1039             chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
1040                 ASPEED_SPI_HCLK_DIV(best_div);
1041     }
1042 
1043 no_calib:
1044     writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
1045     kfree(test_buf);
1046     return 0;
1047 }
1048 
1049 #define TIMING_DELAY_DI     BIT(3)
1050 #define TIMING_DELAY_HCYCLE_MAX 5
1051 #define TIMING_REG_AST2600(chip)                \
1052     ((chip)->aspi->regs + (chip)->aspi->data->timing +  \
1053      (chip)->cs * 4)
1054 
1055 static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
1056                     const u8 *golden_buf, u8 *test_buf)
1057 {
1058     struct aspeed_spi *aspi = chip->aspi;
1059     int hcycle;
1060     u32 shift = (hdiv - 2) << 3;
1061     u32 mask = ~(0xfu << shift);
1062     u32 fread_timing_val = 0;
1063 
1064     for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
1065         int delay_ns;
1066         bool pass = false;
1067 
1068         fread_timing_val &= mask;
1069         fread_timing_val |= hcycle << shift;
1070 
1071         /* no DI input delay first  */
1072         writel(fread_timing_val, TIMING_REG_AST2600(chip));
1073         pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1074         dev_dbg(aspi->dev,
1075             "  * [%08x] %d HCLK delay, DI delay none : %s",
1076             fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
1077         if (pass)
1078             return 0;
1079 
1080         /* Add DI input delays  */
1081         fread_timing_val &= mask;
1082         fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
1083 
1084         for (delay_ns = 0; delay_ns < 0x10; delay_ns++) {
1085             fread_timing_val &= ~(0xf << (4 + shift));
1086             fread_timing_val |= delay_ns << (4 + shift);
1087 
1088             writel(fread_timing_val, TIMING_REG_AST2600(chip));
1089             pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1090             dev_dbg(aspi->dev,
1091                 "  * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
1092                 fread_timing_val, hcycle, (delay_ns + 1) / 2,
1093                 (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
1094             /*
1095              * TODO: This is optimistic. We should look
1096              * for a working interval and save the middle
1097              * value in the read timing register.
1098              */
1099             if (pass)
1100                 return 0;
1101         }
1102     }
1103 
1104     /* No good setting for this frequency */
1105     return -1;
1106 }
1107 
1108 /*
1109  * Platform definitions
1110  */
1111 static const struct aspeed_spi_data ast2400_fmc_data = {
1112     .max_cs        = 5,
1113     .hastype       = true,
1114     .we0           = 16,
1115     .ctl0          = CE0_CTRL_REG,
1116     .timing        = CE0_TIMING_COMPENSATION_REG,
1117     .hclk_mask     = 0xfffff0ff,
1118     .hdiv_max      = 1,
1119     .calibrate     = aspeed_spi_calibrate,
1120     .segment_start = aspeed_spi_segment_start,
1121     .segment_end   = aspeed_spi_segment_end,
1122     .segment_reg   = aspeed_spi_segment_reg,
1123 };
1124 
1125 static const struct aspeed_spi_data ast2400_spi_data = {
1126     .max_cs        = 1,
1127     .hastype       = false,
1128     .we0           = 0,
1129     .ctl0          = 0x04,
1130     .timing        = 0x14,
1131     .hclk_mask     = 0xfffff0ff,
1132     .hdiv_max      = 1,
1133     .calibrate     = aspeed_spi_calibrate,
1134     /* No segment registers */
1135 };
1136 
1137 static const struct aspeed_spi_data ast2500_fmc_data = {
1138     .max_cs        = 3,
1139     .hastype       = true,
1140     .we0           = 16,
1141     .ctl0          = CE0_CTRL_REG,
1142     .timing        = CE0_TIMING_COMPENSATION_REG,
1143     .hclk_mask     = 0xffffd0ff,
1144     .hdiv_max      = 1,
1145     .calibrate     = aspeed_spi_calibrate,
1146     .segment_start = aspeed_spi_segment_start,
1147     .segment_end   = aspeed_spi_segment_end,
1148     .segment_reg   = aspeed_spi_segment_reg,
1149 };
1150 
1151 static const struct aspeed_spi_data ast2500_spi_data = {
1152     .max_cs        = 2,
1153     .hastype       = false,
1154     .we0           = 16,
1155     .ctl0          = CE0_CTRL_REG,
1156     .timing        = CE0_TIMING_COMPENSATION_REG,
1157     .hclk_mask     = 0xffffd0ff,
1158     .hdiv_max      = 1,
1159     .calibrate     = aspeed_spi_calibrate,
1160     .segment_start = aspeed_spi_segment_start,
1161     .segment_end   = aspeed_spi_segment_end,
1162     .segment_reg   = aspeed_spi_segment_reg,
1163 };
1164 
1165 static const struct aspeed_spi_data ast2600_fmc_data = {
1166     .max_cs        = 3,
1167     .hastype       = false,
1168     .mode_bits     = SPI_RX_QUAD | SPI_RX_QUAD,
1169     .we0           = 16,
1170     .ctl0          = CE0_CTRL_REG,
1171     .timing        = CE0_TIMING_COMPENSATION_REG,
1172     .hclk_mask     = 0xf0fff0ff,
1173     .hdiv_max      = 2,
1174     .calibrate     = aspeed_spi_ast2600_calibrate,
1175     .segment_start = aspeed_spi_segment_ast2600_start,
1176     .segment_end   = aspeed_spi_segment_ast2600_end,
1177     .segment_reg   = aspeed_spi_segment_ast2600_reg,
1178 };
1179 
1180 static const struct aspeed_spi_data ast2600_spi_data = {
1181     .max_cs        = 2,
1182     .hastype       = false,
1183     .mode_bits     = SPI_RX_QUAD | SPI_RX_QUAD,
1184     .we0           = 16,
1185     .ctl0          = CE0_CTRL_REG,
1186     .timing        = CE0_TIMING_COMPENSATION_REG,
1187     .hclk_mask     = 0xf0fff0ff,
1188     .hdiv_max      = 2,
1189     .calibrate     = aspeed_spi_ast2600_calibrate,
1190     .segment_start = aspeed_spi_segment_ast2600_start,
1191     .segment_end   = aspeed_spi_segment_ast2600_end,
1192     .segment_reg   = aspeed_spi_segment_ast2600_reg,
1193 };
1194 
1195 static const struct of_device_id aspeed_spi_matches[] = {
1196     { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
1197     { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
1198     { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
1199     { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
1200     { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
1201     { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
1202     { }
1203 };
1204 MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
1205 
1206 static struct platform_driver aspeed_spi_driver = {
1207     .probe          = aspeed_spi_probe,
1208     .remove         = aspeed_spi_remove,
1209     .driver = {
1210         .name       = DEVICE_NAME,
1211         .of_match_table = aspeed_spi_matches,
1212     }
1213 };
1214 
1215 module_platform_driver(aspeed_spi_driver);
1216 
1217 MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
1218 MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
1219 MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
1220 MODULE_LICENSE("GPL v2");
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