drivers/spi/spi-ar934x.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs
0004 //
0005 // Copyright (C) 2020 Chuanhong Guo <gch981213@gmail.com>
0006 //
0007 // Based on spi-mt7621.c:
0008 // Copyright (C) 2011 Sergiy <piratfm@gmail.com>
0009 // Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
0010 // Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
0011
0012 #include <linux/clk.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/spi/spi.h>
0019
0020 #define DRIVER_NAME "spi-ar934x"
0021
0022 #define AR934X_SPI_REG_FS       0x00
0023 #define AR934X_SPI_ENABLE       BIT(0)
0024
0025 #define AR934X_SPI_REG_IOC      0x08
0026 #define AR934X_SPI_IOC_INITVAL      0x70000
0027
0028 #define AR934X_SPI_REG_CTRL     0x04
0029 #define AR934X_SPI_CLK_MASK     GENMASK(5, 0)
0030
0031 #define AR934X_SPI_DATAOUT      0x10
0032
0033 #define AR934X_SPI_REG_SHIFT_CTRL   0x14
0034 #define AR934X_SPI_SHIFT_EN     BIT(31)
0035 #define AR934X_SPI_SHIFT_CS(n)      BIT(28 + (n))
0036 #define AR934X_SPI_SHIFT_TERM       26
0037 #define AR934X_SPI_SHIFT_VAL(cs, term, count)           \
0038     (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) |    \
0039     (term) << AR934X_SPI_SHIFT_TERM | (count))
0040
0041 #define AR934X_SPI_DATAIN 0x18
0042
0043 struct ar934x_spi {
0044     struct spi_controller *ctlr;
0045     void __iomem *base;
0046     struct clk *clk;
0047     unsigned int clk_freq;
0048 };
0049
0050 static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq)
0051 {
0052     int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1;
0053
0054     if (div < 0)
0055         return 0;
0056     else if (div > AR934X_SPI_CLK_MASK)
0057         return -EINVAL;
0058     else
0059         return div;
0060 }
0061
0062 static int ar934x_spi_setup(struct spi_device *spi)
0063 {
0064     struct ar934x_spi *sp = spi_controller_get_devdata(spi->master);
0065
0066     if ((spi->max_speed_hz == 0) ||
0067         (spi->max_speed_hz > (sp->clk_freq / 2))) {
0068         spi->max_speed_hz = sp->clk_freq / 2;
0069     } else if (spi->max_speed_hz < (sp->clk_freq / 128)) {
0070         dev_err(&spi->dev, "spi clock is too low\n");
0071         return -EINVAL;
0072     }
0073
0074     return 0;
0075 }
0076
0077 static int ar934x_spi_transfer_one_message(struct spi_controller *master,
0078                        struct spi_message *m)
0079 {
0080     struct ar934x_spi *sp = spi_controller_get_devdata(master);
0081     struct spi_transfer *t = NULL;
0082     struct spi_device *spi = m->spi;
0083     unsigned long trx_done, trx_cur;
0084     int stat = 0;
0085     u8 bpw, term = 0;
0086     int div, i;
0087     u32 reg;
0088     const u8 *tx_buf;
0089     u8 *buf;
0090
0091     m->actual_length = 0;
0092     list_for_each_entry(t, &m->transfers, transfer_list) {
0093         if (t->bits_per_word >= 8 && t->bits_per_word < 32)
0094             bpw = t->bits_per_word >> 3;
0095         else
0096             bpw = 4;
0097
0098         if (t->speed_hz)
0099             div = ar934x_spi_clk_div(sp, t->speed_hz);
0100         else
0101             div = ar934x_spi_clk_div(sp, spi->max_speed_hz);
0102         if (div < 0) {
0103             stat = -EIO;
0104             goto msg_done;
0105         }
0106
0107         reg = ioread32(sp->base + AR934X_SPI_REG_CTRL);
0108         reg &= ~AR934X_SPI_CLK_MASK;
0109         reg |= div;
0110         iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL);
0111         iowrite32(0, sp->base + AR934X_SPI_DATAOUT);
0112
0113         for (trx_done = 0; trx_done < t->len; trx_done += bpw) {
0114             trx_cur = t->len - trx_done;
0115             if (trx_cur > bpw)
0116                 trx_cur = bpw;
0117             else if (list_is_last(&t->transfer_list, &m->transfers))
0118                 term = 1;
0119
0120             if (t->tx_buf) {
0121                 tx_buf = t->tx_buf + trx_done;
0122                 reg = tx_buf[0];
0123                 for (i = 1; i < trx_cur; i++)
0124                     reg = reg << 8 | tx_buf[i];
0125                 iowrite32(reg, sp->base + AR934X_SPI_DATAOUT);
0126             }
0127
0128             reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term,
0129                            trx_cur * 8);
0130             iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL);
0131             stat = readl_poll_timeout(
0132                 sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg,
0133                 !(reg & AR934X_SPI_SHIFT_EN), 0, 5);
0134             if (stat < 0)
0135                 goto msg_done;
0136
0137             if (t->rx_buf) {
0138                 reg = ioread32(sp->base + AR934X_SPI_DATAIN);
0139                 buf = t->rx_buf + trx_done;
0140                 for (i = 0; i < trx_cur; i++) {
0141                     buf[trx_cur - i - 1] = reg & 0xff;
0142                     reg >>= 8;
0143                 }
0144             }
0145             spi_delay_exec(&t->word_delay, t);
0146         }
0147         m->actual_length += t->len;
0148         spi_transfer_delay_exec(t);
0149     }
0150
0151 msg_done:
0152     m->status = stat;
0153     spi_finalize_current_message(master);
0154
0155     return 0;
0156 }
0157
0158 static const struct of_device_id ar934x_spi_match[] = {
0159     { .compatible = "qca,ar934x-spi" },
0160     {},
0161 };
0162 MODULE_DEVICE_TABLE(of, ar934x_spi_match);
0163
0164 static int ar934x_spi_probe(struct platform_device *pdev)
0165 {
0166     struct spi_controller *ctlr;
0167     struct ar934x_spi *sp;
0168     void __iomem *base;
0169     struct clk *clk;
0170     int ret;
0171
0172     base = devm_platform_ioremap_resource(pdev, 0);
0173     if (IS_ERR(base))
0174         return PTR_ERR(base);
0175
0176     clk = devm_clk_get(&pdev->dev, NULL);
0177     if (IS_ERR(clk)) {
0178         dev_err(&pdev->dev, "failed to get clock\n");
0179         return PTR_ERR(clk);
0180     }
0181
0182     ret = clk_prepare_enable(clk);
0183     if (ret)
0184         return ret;
0185
0186     ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*sp));
0187     if (!ctlr) {
0188         dev_info(&pdev->dev, "failed to allocate spi controller\n");
0189         ret = -ENOMEM;
0190         goto err_clk_disable;
0191     }
0192
0193     /* disable flash mapping and expose spi controller registers */
0194     iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS);
0195     /* restore pins to default state: CSn=1 DO=CLK=0 */
0196     iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC);
0197
0198     ctlr->mode_bits = SPI_LSB_FIRST;
0199     ctlr->setup = ar934x_spi_setup;
0200     ctlr->transfer_one_message = ar934x_spi_transfer_one_message;
0201     ctlr->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(24) |
0202                    SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
0203     ctlr->dev.of_node = pdev->dev.of_node;
0204     ctlr->num_chipselect = 3;
0205
0206     dev_set_drvdata(&pdev->dev, ctlr);
0207
0208     sp = spi_controller_get_devdata(ctlr);
0209     sp->base = base;
0210     sp->clk = clk;
0211     sp->clk_freq = clk_get_rate(clk);
0212     sp->ctlr = ctlr;
0213
0214     ret = spi_register_controller(ctlr);
0215     if (!ret)
0216         return 0;
0217
0218 err_clk_disable:
0219     clk_disable_unprepare(clk);
0220     return ret;
0221 }
0222
0223 static int ar934x_spi_remove(struct platform_device *pdev)
0224 {
0225     struct spi_controller *ctlr;
0226     struct ar934x_spi *sp;
0227
0228     ctlr = dev_get_drvdata(&pdev->dev);
0229     sp = spi_controller_get_devdata(ctlr);
0230
0231     spi_unregister_controller(ctlr);
0232     clk_disable_unprepare(sp->clk);
0233
0234     return 0;
0235 }
0236
0237 static struct platform_driver ar934x_spi_driver = {
0238     .driver = {
0239         .name = DRIVER_NAME,
0240         .of_match_table = ar934x_spi_match,
0241     },
0242     .probe = ar934x_spi_probe,
0243     .remove = ar934x_spi_remove,
0244 };
0245
0246 module_platform_driver(ar934x_spi_driver);
0247
0248 MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx");
0249 MODULE_AUTHOR("Chuanhong Guo <gch981213@gmail.com>");
0250 MODULE_LICENSE("GPL v2");
0251 MODULE_ALIAS("platform:" DRIVER_NAME);