drivers/spi/spi-amd.c

0001 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
0002 //
0003 // AMD SPI controller driver
0004 //
0005 // Copyright (c) 2020, Advanced Micro Devices, Inc.
0006 //
0007 // Author: Sanjay R Mehta <sanju.mehta@amd.com>
0008
0009 #include <linux/acpi.h>
0010 #include <linux/init.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/delay.h>
0014 #include <linux/spi/spi.h>
0015 #include <linux/iopoll.h>
0016
0017 #define AMD_SPI_CTRL0_REG   0x00
0018 #define AMD_SPI_EXEC_CMD    BIT(16)
0019 #define AMD_SPI_FIFO_CLEAR  BIT(20)
0020 #define AMD_SPI_BUSY        BIT(31)
0021
0022 #define AMD_SPI_OPCODE_REG  0x45
0023 #define AMD_SPI_CMD_TRIGGER_REG 0x47
0024 #define AMD_SPI_TRIGGER_CMD BIT(7)
0025
0026 #define AMD_SPI_OPCODE_MASK 0xFF
0027
0028 #define AMD_SPI_ALT_CS_REG  0x1D
0029 #define AMD_SPI_ALT_CS_MASK 0x3
0030
0031 #define AMD_SPI_FIFO_BASE   0x80
0032 #define AMD_SPI_TX_COUNT_REG    0x48
0033 #define AMD_SPI_RX_COUNT_REG    0x4B
0034 #define AMD_SPI_STATUS_REG  0x4C
0035
0036 #define AMD_SPI_FIFO_SIZE   70
0037 #define AMD_SPI_MEM_SIZE    200
0038
0039 /* M_CMD OP codes for SPI */
0040 #define AMD_SPI_XFER_TX     1
0041 #define AMD_SPI_XFER_RX     2
0042
0043 /**
0044  * enum amd_spi_versions - SPI controller versions
0045  * @AMD_SPI_V1:     AMDI0061 hardware version
0046  * @AMD_SPI_V2:     AMDI0062 hardware version
0047  */
0048 enum amd_spi_versions {
0049     AMD_SPI_V1 = 1,
0050     AMD_SPI_V2,
0051 };
0052
0053 /**
0054  * struct amd_spi - SPI driver instance
0055  * @io_remap_addr:  Start address of the SPI controller registers
0056  * @version:        SPI controller hardware version
0057  */
0058 struct amd_spi {
0059     void __iomem *io_remap_addr;
0060     enum amd_spi_versions version;
0061 };
0062
0063 static inline u8 amd_spi_readreg8(struct amd_spi *amd_spi, int idx)
0064 {
0065     return ioread8((u8 __iomem *)amd_spi->io_remap_addr + idx);
0066 }
0067
0068 static inline void amd_spi_writereg8(struct amd_spi *amd_spi, int idx, u8 val)
0069 {
0070     iowrite8(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
0071 }
0072
0073 static void amd_spi_setclear_reg8(struct amd_spi *amd_spi, int idx, u8 set, u8 clear)
0074 {
0075     u8 tmp = amd_spi_readreg8(amd_spi, idx);
0076
0077     tmp = (tmp & ~clear) | set;
0078     amd_spi_writereg8(amd_spi, idx, tmp);
0079 }
0080
0081 static inline u32 amd_spi_readreg32(struct amd_spi *amd_spi, int idx)
0082 {
0083     return ioread32((u8 __iomem *)amd_spi->io_remap_addr + idx);
0084 }
0085
0086 static inline void amd_spi_writereg32(struct amd_spi *amd_spi, int idx, u32 val)
0087 {
0088     iowrite32(val, ((u8 __iomem *)amd_spi->io_remap_addr + idx));
0089 }
0090
0091 static inline void amd_spi_setclear_reg32(struct amd_spi *amd_spi, int idx, u32 set, u32 clear)
0092 {
0093     u32 tmp = amd_spi_readreg32(amd_spi, idx);
0094
0095     tmp = (tmp & ~clear) | set;
0096     amd_spi_writereg32(amd_spi, idx, tmp);
0097 }
0098
0099 static void amd_spi_select_chip(struct amd_spi *amd_spi, u8 cs)
0100 {
0101     amd_spi_setclear_reg8(amd_spi, AMD_SPI_ALT_CS_REG, cs, AMD_SPI_ALT_CS_MASK);
0102 }
0103
0104 static inline void amd_spi_clear_chip(struct amd_spi *amd_spi, u8 chip_select)
0105 {
0106     amd_spi_writereg8(amd_spi, AMD_SPI_ALT_CS_REG, chip_select & ~AMD_SPI_ALT_CS_MASK);
0107 }
0108
0109 static void amd_spi_clear_fifo_ptr(struct amd_spi *amd_spi)
0110 {
0111     amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, AMD_SPI_FIFO_CLEAR);
0112 }
0113
0114 static int amd_spi_set_opcode(struct amd_spi *amd_spi, u8 cmd_opcode)
0115 {
0116     switch (amd_spi->version) {
0117     case AMD_SPI_V1:
0118         amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, cmd_opcode,
0119                        AMD_SPI_OPCODE_MASK);
0120         return 0;
0121     case AMD_SPI_V2:
0122         amd_spi_writereg8(amd_spi, AMD_SPI_OPCODE_REG, cmd_opcode);
0123         return 0;
0124     default:
0125         return -ENODEV;
0126     }
0127 }
0128
0129 static inline void amd_spi_set_rx_count(struct amd_spi *amd_spi, u8 rx_count)
0130 {
0131     amd_spi_setclear_reg8(amd_spi, AMD_SPI_RX_COUNT_REG, rx_count, 0xff);
0132 }
0133
0134 static inline void amd_spi_set_tx_count(struct amd_spi *amd_spi, u8 tx_count)
0135 {
0136     amd_spi_setclear_reg8(amd_spi, AMD_SPI_TX_COUNT_REG, tx_count, 0xff);
0137 }
0138
0139 static int amd_spi_busy_wait(struct amd_spi *amd_spi)
0140 {
0141     u32 val;
0142     int reg;
0143
0144     switch (amd_spi->version) {
0145     case AMD_SPI_V1:
0146         reg = AMD_SPI_CTRL0_REG;
0147         break;
0148     case AMD_SPI_V2:
0149         reg = AMD_SPI_STATUS_REG;
0150         break;
0151     default:
0152         return -ENODEV;
0153     }
0154
0155     return readl_poll_timeout(amd_spi->io_remap_addr + reg, val,
0156                   !(val & AMD_SPI_BUSY), 20, 2000000);
0157 }
0158
0159 static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
0160 {
0161     int ret;
0162
0163     ret = amd_spi_busy_wait(amd_spi);
0164     if (ret)
0165         return ret;
0166
0167     switch (amd_spi->version) {
0168     case AMD_SPI_V1:
0169         /* Set ExecuteOpCode bit in the CTRL0 register */
0170         amd_spi_setclear_reg32(amd_spi, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD,
0171                        AMD_SPI_EXEC_CMD);
0172         return 0;
0173     case AMD_SPI_V2:
0174         /* Trigger the command execution */
0175         amd_spi_setclear_reg8(amd_spi, AMD_SPI_CMD_TRIGGER_REG,
0176                       AMD_SPI_TRIGGER_CMD, AMD_SPI_TRIGGER_CMD);
0177         return 0;
0178     default:
0179         return -ENODEV;
0180     }
0181 }
0182
0183 static int amd_spi_master_setup(struct spi_device *spi)
0184 {
0185     struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
0186
0187     amd_spi_clear_fifo_ptr(amd_spi);
0188
0189     return 0;
0190 }
0191
0192 static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
0193                     struct spi_master *master,
0194                     struct spi_message *message)
0195 {
0196     struct spi_transfer *xfer = NULL;
0197     u8 cmd_opcode;
0198     u8 *buf = NULL;
0199     u32 m_cmd = 0;
0200     u32 i = 0;
0201     u32 tx_len = 0, rx_len = 0;
0202
0203     list_for_each_entry(xfer, &message->transfers,
0204                 transfer_list) {
0205         if (xfer->rx_buf)
0206             m_cmd = AMD_SPI_XFER_RX;
0207         if (xfer->tx_buf)
0208             m_cmd = AMD_SPI_XFER_TX;
0209
0210         if (m_cmd & AMD_SPI_XFER_TX) {
0211             buf = (u8 *)xfer->tx_buf;
0212             tx_len = xfer->len - 1;
0213             cmd_opcode = *(u8 *)xfer->tx_buf;
0214             buf++;
0215             amd_spi_set_opcode(amd_spi, cmd_opcode);
0216
0217             /* Write data into the FIFO. */
0218             for (i = 0; i < tx_len; i++) {
0219                 iowrite8(buf[i], ((u8 __iomem *)amd_spi->io_remap_addr +
0220                      AMD_SPI_FIFO_BASE + i));
0221             }
0222
0223             amd_spi_set_tx_count(amd_spi, tx_len);
0224             amd_spi_clear_fifo_ptr(amd_spi);
0225             /* Execute command */
0226             amd_spi_execute_opcode(amd_spi);
0227         }
0228         if (m_cmd & AMD_SPI_XFER_RX) {
0229             /*
0230              * Store no. of bytes to be received from
0231              * FIFO
0232              */
0233             rx_len = xfer->len;
0234             buf = (u8 *)xfer->rx_buf;
0235             amd_spi_set_rx_count(amd_spi, rx_len);
0236             amd_spi_clear_fifo_ptr(amd_spi);
0237             /* Execute command */
0238             amd_spi_execute_opcode(amd_spi);
0239             amd_spi_busy_wait(amd_spi);
0240             /* Read data from FIFO to receive buffer  */
0241             for (i = 0; i < rx_len; i++)
0242                 buf[i] = amd_spi_readreg8(amd_spi, AMD_SPI_FIFO_BASE + tx_len + i);
0243         }
0244     }
0245
0246     /* Update statistics */
0247     message->actual_length = tx_len + rx_len + 1;
0248     /* complete the transaction */
0249     message->status = 0;
0250
0251     switch (amd_spi->version) {
0252     case AMD_SPI_V1:
0253         break;
0254     case AMD_SPI_V2:
0255         amd_spi_clear_chip(amd_spi, message->spi->chip_select);
0256         break;
0257     default:
0258         return -ENODEV;
0259     }
0260
0261     spi_finalize_current_message(master);
0262
0263     return 0;
0264 }
0265
0266 static int amd_spi_master_transfer(struct spi_master *master,
0267                    struct spi_message *msg)
0268 {
0269     struct amd_spi *amd_spi = spi_master_get_devdata(master);
0270     struct spi_device *spi = msg->spi;
0271
0272     amd_spi_select_chip(amd_spi, spi->chip_select);
0273
0274     /*
0275      * Extract spi_transfers from the spi message and
0276      * program the controller.
0277      */
0278     amd_spi_fifo_xfer(amd_spi, master, msg);
0279
0280     return 0;
0281 }
0282
0283 static size_t amd_spi_max_transfer_size(struct spi_device *spi)
0284 {
0285     return AMD_SPI_FIFO_SIZE;
0286 }
0287
0288 static int amd_spi_probe(struct platform_device *pdev)
0289 {
0290     struct device *dev = &pdev->dev;
0291     struct spi_master *master;
0292     struct amd_spi *amd_spi;
0293     int err;
0294
0295     /* Allocate storage for spi_master and driver private data */
0296     master = devm_spi_alloc_master(dev, sizeof(struct amd_spi));
0297     if (!master)
0298         return dev_err_probe(dev, -ENOMEM, "Error allocating SPI master\n");
0299
0300     amd_spi = spi_master_get_devdata(master);
0301     amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
0302     if (IS_ERR(amd_spi->io_remap_addr))
0303         return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
0304                      "ioremap of SPI registers failed\n");
0305
0306     dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr);
0307
0308     amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
0309
0310     /* Initialize the spi_master fields */
0311     master->bus_num = 0;
0312     master->num_chipselect = 4;
0313     master->mode_bits = 0;
0314     master->flags = SPI_MASTER_HALF_DUPLEX;
0315     master->setup = amd_spi_master_setup;
0316     master->transfer_one_message = amd_spi_master_transfer;
0317     master->max_transfer_size = amd_spi_max_transfer_size;
0318     master->max_message_size = amd_spi_max_transfer_size;
0319
0320     /* Register the controller with SPI framework */
0321     err = devm_spi_register_master(dev, master);
0322     if (err)
0323         return dev_err_probe(dev, err, "error registering SPI controller\n");
0324
0325     return 0;
0326 }
0327
0328 #ifdef CONFIG_ACPI
0329 static const struct acpi_device_id spi_acpi_match[] = {
0330     { "AMDI0061", AMD_SPI_V1 },
0331     { "AMDI0062", AMD_SPI_V2 },
0332     {},
0333 };
0334 MODULE_DEVICE_TABLE(acpi, spi_acpi_match);
0335 #endif
0336
0337 static struct platform_driver amd_spi_driver = {
0338     .driver = {
0339         .name = "amd_spi",
0340         .acpi_match_table = ACPI_PTR(spi_acpi_match),
0341     },
0342     .probe = amd_spi_probe,
0343 };
0344
0345 module_platform_driver(amd_spi_driver);
0346
0347 MODULE_LICENSE("Dual BSD/GPL");
0348 MODULE_AUTHOR("Sanjay Mehta <sanju.mehta@amd.com>");
0349 MODULE_DESCRIPTION("AMD SPI Master Controller Driver");