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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for Atmel QSPI Controller
0004  *
0005  * Copyright (C) 2015 Atmel Corporation
0006  * Copyright (C) 2018 Cryptera A/S
0007  *
0008  * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
0009  * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
0010  *
0011  * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
0012  */
0013 
0014 #include <linux/clk.h>
0015 #include <linux/delay.h>
0016 #include <linux/err.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/of.h>
0022 #include <linux/of_platform.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/pm_runtime.h>
0025 #include <linux/spi/spi-mem.h>
0026 
0027 /* QSPI register offsets */
0028 #define QSPI_CR      0x0000  /* Control Register */
0029 #define QSPI_MR      0x0004  /* Mode Register */
0030 #define QSPI_RD      0x0008  /* Receive Data Register */
0031 #define QSPI_TD      0x000c  /* Transmit Data Register */
0032 #define QSPI_SR      0x0010  /* Status Register */
0033 #define QSPI_IER     0x0014  /* Interrupt Enable Register */
0034 #define QSPI_IDR     0x0018  /* Interrupt Disable Register */
0035 #define QSPI_IMR     0x001c  /* Interrupt Mask Register */
0036 #define QSPI_SCR     0x0020  /* Serial Clock Register */
0037 
0038 #define QSPI_IAR     0x0030  /* Instruction Address Register */
0039 #define QSPI_ICR     0x0034  /* Instruction Code Register */
0040 #define QSPI_WICR    0x0034  /* Write Instruction Code Register */
0041 #define QSPI_IFR     0x0038  /* Instruction Frame Register */
0042 #define QSPI_RICR    0x003C  /* Read Instruction Code Register */
0043 
0044 #define QSPI_SMR     0x0040  /* Scrambling Mode Register */
0045 #define QSPI_SKR     0x0044  /* Scrambling Key Register */
0046 
0047 #define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
0048 #define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
0049 
0050 #define QSPI_VERSION 0x00FC  /* Version Register */
0051 
0052 
0053 /* Bitfields in QSPI_CR (Control Register) */
0054 #define QSPI_CR_QSPIEN                  BIT(0)
0055 #define QSPI_CR_QSPIDIS                 BIT(1)
0056 #define QSPI_CR_SWRST                   BIT(7)
0057 #define QSPI_CR_LASTXFER                BIT(24)
0058 
0059 /* Bitfields in QSPI_MR (Mode Register) */
0060 #define QSPI_MR_SMM                     BIT(0)
0061 #define QSPI_MR_LLB                     BIT(1)
0062 #define QSPI_MR_WDRBT                   BIT(2)
0063 #define QSPI_MR_SMRM                    BIT(3)
0064 #define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
0065 #define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
0066 #define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
0067 #define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
0068 #define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
0069 #define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
0070 #define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
0071 #define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
0072 #define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
0073 #define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
0074 
0075 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
0076 #define QSPI_SR_RDRF                    BIT(0)
0077 #define QSPI_SR_TDRE                    BIT(1)
0078 #define QSPI_SR_TXEMPTY                 BIT(2)
0079 #define QSPI_SR_OVRES                   BIT(3)
0080 #define QSPI_SR_CSR                     BIT(8)
0081 #define QSPI_SR_CSS                     BIT(9)
0082 #define QSPI_SR_INSTRE                  BIT(10)
0083 #define QSPI_SR_QSPIENS                 BIT(24)
0084 
0085 #define QSPI_SR_CMD_COMPLETED   (QSPI_SR_INSTRE | QSPI_SR_CSR)
0086 
0087 /* Bitfields in QSPI_SCR (Serial Clock Register) */
0088 #define QSPI_SCR_CPOL                   BIT(0)
0089 #define QSPI_SCR_CPHA                   BIT(1)
0090 #define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
0091 #define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
0092 #define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
0093 #define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
0094 
0095 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
0096 #define QSPI_ICR_INST_MASK              GENMASK(7, 0)
0097 #define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
0098 #define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
0099 #define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
0100 
0101 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
0102 #define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
0103 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
0104 #define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
0105 #define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
0106 #define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
0107 #define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
0108 #define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
0109 #define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
0110 #define QSPI_IFR_INSTEN                 BIT(4)
0111 #define QSPI_IFR_ADDREN                 BIT(5)
0112 #define QSPI_IFR_OPTEN                  BIT(6)
0113 #define QSPI_IFR_DATAEN                 BIT(7)
0114 #define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
0115 #define QSPI_IFR_OPTL_1BIT              (0 << 8)
0116 #define QSPI_IFR_OPTL_2BIT              (1 << 8)
0117 #define QSPI_IFR_OPTL_4BIT              (2 << 8)
0118 #define QSPI_IFR_OPTL_8BIT              (3 << 8)
0119 #define QSPI_IFR_ADDRL                  BIT(10)
0120 #define QSPI_IFR_TFRTYP_MEM     BIT(12)
0121 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR    BIT(13)
0122 #define QSPI_IFR_CRM                    BIT(14)
0123 #define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
0124 #define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
0125 #define QSPI_IFR_APBTFRTYP_READ     BIT(24) /* Defined in SAM9X60 */
0126 
0127 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
0128 #define QSPI_SMR_SCREN                  BIT(0)
0129 #define QSPI_SMR_RVDIS                  BIT(1)
0130 
0131 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
0132 #define QSPI_WPMR_WPEN                  BIT(0)
0133 #define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
0134 #define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
0135 
0136 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
0137 #define QSPI_WPSR_WPVS                  BIT(0)
0138 #define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
0139 #define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
0140 
0141 struct atmel_qspi_caps {
0142     bool has_qspick;
0143     bool has_ricr;
0144 };
0145 
0146 struct atmel_qspi {
0147     void __iomem        *regs;
0148     void __iomem        *mem;
0149     struct clk      *pclk;
0150     struct clk      *qspick;
0151     struct platform_device  *pdev;
0152     const struct atmel_qspi_caps *caps;
0153     resource_size_t     mmap_size;
0154     u32         pending;
0155     u32         mr;
0156     u32         scr;
0157     struct completion   cmd_completion;
0158 };
0159 
0160 struct atmel_qspi_mode {
0161     u8 cmd_buswidth;
0162     u8 addr_buswidth;
0163     u8 data_buswidth;
0164     u32 config;
0165 };
0166 
0167 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
0168     { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
0169     { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
0170     { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
0171     { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
0172     { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
0173     { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
0174     { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
0175 };
0176 
0177 #ifdef VERBOSE_DEBUG
0178 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
0179 {
0180     switch (offset) {
0181     case QSPI_CR:
0182         return "CR";
0183     case QSPI_MR:
0184         return "MR";
0185     case QSPI_RD:
0186         return "MR";
0187     case QSPI_TD:
0188         return "TD";
0189     case QSPI_SR:
0190         return "SR";
0191     case QSPI_IER:
0192         return "IER";
0193     case QSPI_IDR:
0194         return "IDR";
0195     case QSPI_IMR:
0196         return "IMR";
0197     case QSPI_SCR:
0198         return "SCR";
0199     case QSPI_IAR:
0200         return "IAR";
0201     case QSPI_ICR:
0202         return "ICR/WICR";
0203     case QSPI_IFR:
0204         return "IFR";
0205     case QSPI_RICR:
0206         return "RICR";
0207     case QSPI_SMR:
0208         return "SMR";
0209     case QSPI_SKR:
0210         return "SKR";
0211     case QSPI_WPMR:
0212         return "WPMR";
0213     case QSPI_WPSR:
0214         return "WPSR";
0215     case QSPI_VERSION:
0216         return "VERSION";
0217     default:
0218         snprintf(tmp, sz, "0x%02x", offset);
0219         break;
0220     }
0221 
0222     return tmp;
0223 }
0224 #endif /* VERBOSE_DEBUG */
0225 
0226 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
0227 {
0228     u32 value = readl_relaxed(aq->regs + offset);
0229 
0230 #ifdef VERBOSE_DEBUG
0231     char tmp[8];
0232 
0233     dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
0234          atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
0235 #endif /* VERBOSE_DEBUG */
0236 
0237     return value;
0238 }
0239 
0240 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
0241 {
0242 #ifdef VERBOSE_DEBUG
0243     char tmp[8];
0244 
0245     dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
0246          atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
0247 #endif /* VERBOSE_DEBUG */
0248 
0249     writel_relaxed(value, aq->regs + offset);
0250 }
0251 
0252 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
0253                         const struct atmel_qspi_mode *mode)
0254 {
0255     if (op->cmd.buswidth != mode->cmd_buswidth)
0256         return false;
0257 
0258     if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
0259         return false;
0260 
0261     if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
0262         return false;
0263 
0264     return true;
0265 }
0266 
0267 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
0268 {
0269     u32 i;
0270 
0271     for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
0272         if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
0273             return i;
0274 
0275     return -ENOTSUPP;
0276 }
0277 
0278 static bool atmel_qspi_supports_op(struct spi_mem *mem,
0279                    const struct spi_mem_op *op)
0280 {
0281     if (!spi_mem_default_supports_op(mem, op))
0282         return false;
0283 
0284     if (atmel_qspi_find_mode(op) < 0)
0285         return false;
0286 
0287     /* special case not supported by hardware */
0288     if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
0289         op->dummy.nbytes == 0)
0290         return false;
0291 
0292     return true;
0293 }
0294 
0295 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
0296                   const struct spi_mem_op *op, u32 *offset)
0297 {
0298     u32 iar, icr, ifr;
0299     u32 dummy_cycles = 0;
0300     int mode;
0301 
0302     iar = 0;
0303     icr = QSPI_ICR_INST(op->cmd.opcode);
0304     ifr = QSPI_IFR_INSTEN;
0305 
0306     mode = atmel_qspi_find_mode(op);
0307     if (mode < 0)
0308         return mode;
0309     ifr |= atmel_qspi_modes[mode].config;
0310 
0311     if (op->dummy.nbytes)
0312         dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
0313 
0314     /*
0315      * The controller allows 24 and 32-bit addressing while NAND-flash
0316      * requires 16-bit long. Handling 8-bit long addresses is done using
0317      * the option field. For the 16-bit addresses, the workaround depends
0318      * of the number of requested dummy bits. If there are 8 or more dummy
0319      * cycles, the address is shifted and sent with the first dummy byte.
0320      * Otherwise opcode is disabled and the first byte of the address
0321      * contains the command opcode (works only if the opcode and address
0322      * use the same buswidth). The limitation is when the 16-bit address is
0323      * used without enough dummy cycles and the opcode is using a different
0324      * buswidth than the address.
0325      */
0326     if (op->addr.buswidth) {
0327         switch (op->addr.nbytes) {
0328         case 0:
0329             break;
0330         case 1:
0331             ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
0332             icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
0333             break;
0334         case 2:
0335             if (dummy_cycles < 8 / op->addr.buswidth) {
0336                 ifr &= ~QSPI_IFR_INSTEN;
0337                 ifr |= QSPI_IFR_ADDREN;
0338                 iar = (op->cmd.opcode << 16) |
0339                     (op->addr.val & 0xffff);
0340             } else {
0341                 ifr |= QSPI_IFR_ADDREN;
0342                 iar = (op->addr.val << 8) & 0xffffff;
0343                 dummy_cycles -= 8 / op->addr.buswidth;
0344             }
0345             break;
0346         case 3:
0347             ifr |= QSPI_IFR_ADDREN;
0348             iar = op->addr.val & 0xffffff;
0349             break;
0350         case 4:
0351             ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
0352             iar = op->addr.val & 0x7ffffff;
0353             break;
0354         default:
0355             return -ENOTSUPP;
0356         }
0357     }
0358 
0359     /* offset of the data access in the QSPI memory space */
0360     *offset = iar;
0361 
0362     /* Set number of dummy cycles */
0363     if (dummy_cycles)
0364         ifr |= QSPI_IFR_NBDUM(dummy_cycles);
0365 
0366     /* Set data enable and data transfer type. */
0367     if (op->data.nbytes) {
0368         ifr |= QSPI_IFR_DATAEN;
0369 
0370         if (op->addr.nbytes)
0371             ifr |= QSPI_IFR_TFRTYP_MEM;
0372     }
0373 
0374     /*
0375      * If the QSPI controller is set in regular SPI mode, set it in
0376      * Serial Memory Mode (SMM).
0377      */
0378     if (aq->mr != QSPI_MR_SMM) {
0379         atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
0380         aq->mr = QSPI_MR_SMM;
0381     }
0382 
0383     /* Clear pending interrupts */
0384     (void)atmel_qspi_read(aq, QSPI_SR);
0385 
0386     /* Set QSPI Instruction Frame registers. */
0387     if (op->addr.nbytes && !op->data.nbytes)
0388         atmel_qspi_write(iar, aq, QSPI_IAR);
0389 
0390     if (aq->caps->has_ricr) {
0391         if (op->data.dir == SPI_MEM_DATA_IN)
0392             atmel_qspi_write(icr, aq, QSPI_RICR);
0393         else
0394             atmel_qspi_write(icr, aq, QSPI_WICR);
0395     } else {
0396         if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
0397             ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
0398 
0399         atmel_qspi_write(icr, aq, QSPI_ICR);
0400     }
0401 
0402     atmel_qspi_write(ifr, aq, QSPI_IFR);
0403 
0404     return 0;
0405 }
0406 
0407 static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
0408 {
0409     struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->master);
0410     u32 sr, offset;
0411     int err;
0412 
0413     /*
0414      * Check if the address exceeds the MMIO window size. An improvement
0415      * would be to add support for regular SPI mode and fall back to it
0416      * when the flash memories overrun the controller's memory space.
0417      */
0418     if (op->addr.val + op->data.nbytes > aq->mmap_size)
0419         return -ENOTSUPP;
0420 
0421     err = pm_runtime_resume_and_get(&aq->pdev->dev);
0422     if (err < 0)
0423         return err;
0424 
0425     err = atmel_qspi_set_cfg(aq, op, &offset);
0426     if (err)
0427         goto pm_runtime_put;
0428 
0429     /* Skip to the final steps if there is no data */
0430     if (op->data.nbytes) {
0431         /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
0432         (void)atmel_qspi_read(aq, QSPI_IFR);
0433 
0434         /* Send/Receive data */
0435         if (op->data.dir == SPI_MEM_DATA_IN)
0436             memcpy_fromio(op->data.buf.in, aq->mem + offset,
0437                       op->data.nbytes);
0438         else
0439             memcpy_toio(aq->mem + offset, op->data.buf.out,
0440                     op->data.nbytes);
0441 
0442         /* Release the chip-select */
0443         atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
0444     }
0445 
0446     /* Poll INSTRuction End status */
0447     sr = atmel_qspi_read(aq, QSPI_SR);
0448     if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
0449         goto pm_runtime_put;
0450 
0451     /* Wait for INSTRuction End interrupt */
0452     reinit_completion(&aq->cmd_completion);
0453     aq->pending = sr & QSPI_SR_CMD_COMPLETED;
0454     atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
0455     if (!wait_for_completion_timeout(&aq->cmd_completion,
0456                      msecs_to_jiffies(1000)))
0457         err = -ETIMEDOUT;
0458     atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
0459 
0460 pm_runtime_put:
0461     pm_runtime_mark_last_busy(&aq->pdev->dev);
0462     pm_runtime_put_autosuspend(&aq->pdev->dev);
0463     return err;
0464 }
0465 
0466 static const char *atmel_qspi_get_name(struct spi_mem *spimem)
0467 {
0468     return dev_name(spimem->spi->dev.parent);
0469 }
0470 
0471 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
0472     .supports_op = atmel_qspi_supports_op,
0473     .exec_op = atmel_qspi_exec_op,
0474     .get_name = atmel_qspi_get_name
0475 };
0476 
0477 static int atmel_qspi_setup(struct spi_device *spi)
0478 {
0479     struct spi_controller *ctrl = spi->master;
0480     struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
0481     unsigned long src_rate;
0482     u32 scbr;
0483     int ret;
0484 
0485     if (ctrl->busy)
0486         return -EBUSY;
0487 
0488     if (!spi->max_speed_hz)
0489         return -EINVAL;
0490 
0491     src_rate = clk_get_rate(aq->pclk);
0492     if (!src_rate)
0493         return -EINVAL;
0494 
0495     /* Compute the QSPI baudrate */
0496     scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
0497     if (scbr > 0)
0498         scbr--;
0499 
0500     ret = pm_runtime_resume_and_get(ctrl->dev.parent);
0501     if (ret < 0)
0502         return ret;
0503 
0504     aq->scr = QSPI_SCR_SCBR(scbr);
0505     atmel_qspi_write(aq->scr, aq, QSPI_SCR);
0506 
0507     pm_runtime_mark_last_busy(ctrl->dev.parent);
0508     pm_runtime_put_autosuspend(ctrl->dev.parent);
0509 
0510     return 0;
0511 }
0512 
0513 static void atmel_qspi_init(struct atmel_qspi *aq)
0514 {
0515     /* Reset the QSPI controller */
0516     atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
0517 
0518     /* Set the QSPI controller by default in Serial Memory Mode */
0519     atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
0520     aq->mr = QSPI_MR_SMM;
0521 
0522     /* Enable the QSPI controller */
0523     atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
0524 }
0525 
0526 static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
0527 {
0528     struct atmel_qspi *aq = dev_id;
0529     u32 status, mask, pending;
0530 
0531     status = atmel_qspi_read(aq, QSPI_SR);
0532     mask = atmel_qspi_read(aq, QSPI_IMR);
0533     pending = status & mask;
0534 
0535     if (!pending)
0536         return IRQ_NONE;
0537 
0538     aq->pending |= pending;
0539     if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
0540         complete(&aq->cmd_completion);
0541 
0542     return IRQ_HANDLED;
0543 }
0544 
0545 static int atmel_qspi_probe(struct platform_device *pdev)
0546 {
0547     struct spi_controller *ctrl;
0548     struct atmel_qspi *aq;
0549     struct resource *res;
0550     int irq, err = 0;
0551 
0552     ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*aq));
0553     if (!ctrl)
0554         return -ENOMEM;
0555 
0556     ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
0557     ctrl->setup = atmel_qspi_setup;
0558     ctrl->bus_num = -1;
0559     ctrl->mem_ops = &atmel_qspi_mem_ops;
0560     ctrl->num_chipselect = 1;
0561     ctrl->dev.of_node = pdev->dev.of_node;
0562     platform_set_drvdata(pdev, ctrl);
0563 
0564     aq = spi_controller_get_devdata(ctrl);
0565 
0566     init_completion(&aq->cmd_completion);
0567     aq->pdev = pdev;
0568 
0569     /* Map the registers */
0570     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
0571     aq->regs = devm_ioremap_resource(&pdev->dev, res);
0572     if (IS_ERR(aq->regs)) {
0573         dev_err(&pdev->dev, "missing registers\n");
0574         return PTR_ERR(aq->regs);
0575     }
0576 
0577     /* Map the AHB memory */
0578     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
0579     aq->mem = devm_ioremap_resource(&pdev->dev, res);
0580     if (IS_ERR(aq->mem)) {
0581         dev_err(&pdev->dev, "missing AHB memory\n");
0582         return PTR_ERR(aq->mem);
0583     }
0584 
0585     aq->mmap_size = resource_size(res);
0586 
0587     /* Get the peripheral clock */
0588     aq->pclk = devm_clk_get(&pdev->dev, "pclk");
0589     if (IS_ERR(aq->pclk))
0590         aq->pclk = devm_clk_get(&pdev->dev, NULL);
0591 
0592     if (IS_ERR(aq->pclk)) {
0593         dev_err(&pdev->dev, "missing peripheral clock\n");
0594         return PTR_ERR(aq->pclk);
0595     }
0596 
0597     /* Enable the peripheral clock */
0598     err = clk_prepare_enable(aq->pclk);
0599     if (err) {
0600         dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
0601         return err;
0602     }
0603 
0604     aq->caps = of_device_get_match_data(&pdev->dev);
0605     if (!aq->caps) {
0606         dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
0607         err = -EINVAL;
0608         goto disable_pclk;
0609     }
0610 
0611     if (aq->caps->has_qspick) {
0612         /* Get the QSPI system clock */
0613         aq->qspick = devm_clk_get(&pdev->dev, "qspick");
0614         if (IS_ERR(aq->qspick)) {
0615             dev_err(&pdev->dev, "missing system clock\n");
0616             err = PTR_ERR(aq->qspick);
0617             goto disable_pclk;
0618         }
0619 
0620         /* Enable the QSPI system clock */
0621         err = clk_prepare_enable(aq->qspick);
0622         if (err) {
0623             dev_err(&pdev->dev,
0624                 "failed to enable the QSPI system clock\n");
0625             goto disable_pclk;
0626         }
0627     }
0628 
0629     /* Request the IRQ */
0630     irq = platform_get_irq(pdev, 0);
0631     if (irq < 0) {
0632         err = irq;
0633         goto disable_qspick;
0634     }
0635     err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
0636                    0, dev_name(&pdev->dev), aq);
0637     if (err)
0638         goto disable_qspick;
0639 
0640     pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
0641     pm_runtime_use_autosuspend(&pdev->dev);
0642     pm_runtime_set_active(&pdev->dev);
0643     pm_runtime_enable(&pdev->dev);
0644     pm_runtime_get_noresume(&pdev->dev);
0645 
0646     atmel_qspi_init(aq);
0647 
0648     err = spi_register_controller(ctrl);
0649     if (err) {
0650         pm_runtime_put_noidle(&pdev->dev);
0651         pm_runtime_disable(&pdev->dev);
0652         pm_runtime_set_suspended(&pdev->dev);
0653         pm_runtime_dont_use_autosuspend(&pdev->dev);
0654         goto disable_qspick;
0655     }
0656     pm_runtime_mark_last_busy(&pdev->dev);
0657     pm_runtime_put_autosuspend(&pdev->dev);
0658 
0659     return 0;
0660 
0661 disable_qspick:
0662     clk_disable_unprepare(aq->qspick);
0663 disable_pclk:
0664     clk_disable_unprepare(aq->pclk);
0665 
0666     return err;
0667 }
0668 
0669 static int atmel_qspi_remove(struct platform_device *pdev)
0670 {
0671     struct spi_controller *ctrl = platform_get_drvdata(pdev);
0672     struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
0673     int ret;
0674 
0675     ret = pm_runtime_resume_and_get(&pdev->dev);
0676     if (ret < 0)
0677         return ret;
0678 
0679     spi_unregister_controller(ctrl);
0680     atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
0681 
0682     pm_runtime_disable(&pdev->dev);
0683     pm_runtime_put_noidle(&pdev->dev);
0684 
0685     clk_disable_unprepare(aq->qspick);
0686     clk_disable_unprepare(aq->pclk);
0687     return 0;
0688 }
0689 
0690 static int __maybe_unused atmel_qspi_suspend(struct device *dev)
0691 {
0692     struct spi_controller *ctrl = dev_get_drvdata(dev);
0693     struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
0694     int ret;
0695 
0696     ret = pm_runtime_resume_and_get(dev);
0697     if (ret < 0)
0698         return ret;
0699 
0700     atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
0701 
0702     pm_runtime_mark_last_busy(dev);
0703     pm_runtime_force_suspend(dev);
0704 
0705     clk_unprepare(aq->qspick);
0706     clk_unprepare(aq->pclk);
0707 
0708     return 0;
0709 }
0710 
0711 static int __maybe_unused atmel_qspi_resume(struct device *dev)
0712 {
0713     struct spi_controller *ctrl = dev_get_drvdata(dev);
0714     struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
0715     int ret;
0716 
0717     clk_prepare(aq->pclk);
0718     clk_prepare(aq->qspick);
0719 
0720     ret = pm_runtime_force_resume(dev);
0721     if (ret < 0)
0722         return ret;
0723 
0724     atmel_qspi_init(aq);
0725 
0726     atmel_qspi_write(aq->scr, aq, QSPI_SCR);
0727 
0728     pm_runtime_mark_last_busy(dev);
0729     pm_runtime_put_autosuspend(dev);
0730 
0731     return 0;
0732 }
0733 
0734 static int __maybe_unused atmel_qspi_runtime_suspend(struct device *dev)
0735 {
0736     struct spi_controller *ctrl = dev_get_drvdata(dev);
0737     struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
0738 
0739     clk_disable(aq->qspick);
0740     clk_disable(aq->pclk);
0741 
0742     return 0;
0743 }
0744 
0745 static int __maybe_unused atmel_qspi_runtime_resume(struct device *dev)
0746 {
0747     struct spi_controller *ctrl = dev_get_drvdata(dev);
0748     struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
0749     int ret;
0750 
0751     ret = clk_enable(aq->pclk);
0752     if (ret)
0753         return ret;
0754 
0755     return clk_enable(aq->qspick);
0756 }
0757 
0758 static const struct dev_pm_ops __maybe_unused atmel_qspi_pm_ops = {
0759     SET_SYSTEM_SLEEP_PM_OPS(atmel_qspi_suspend, atmel_qspi_resume)
0760     SET_RUNTIME_PM_OPS(atmel_qspi_runtime_suspend,
0761                atmel_qspi_runtime_resume, NULL)
0762 };
0763 
0764 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
0765 
0766 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
0767     .has_qspick = true,
0768     .has_ricr = true,
0769 };
0770 
0771 static const struct of_device_id atmel_qspi_dt_ids[] = {
0772     {
0773         .compatible = "atmel,sama5d2-qspi",
0774         .data = &atmel_sama5d2_qspi_caps,
0775     },
0776     {
0777         .compatible = "microchip,sam9x60-qspi",
0778         .data = &atmel_sam9x60_qspi_caps,
0779     },
0780     { /* sentinel */ }
0781 };
0782 
0783 MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
0784 
0785 static struct platform_driver atmel_qspi_driver = {
0786     .driver = {
0787         .name   = "atmel_qspi",
0788         .of_match_table = atmel_qspi_dt_ids,
0789         .pm = pm_ptr(&atmel_qspi_pm_ops),
0790     },
0791     .probe      = atmel_qspi_probe,
0792     .remove     = atmel_qspi_remove,
0793 };
0794 module_platform_driver(atmel_qspi_driver);
0795 
0796 MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
0797 MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
0798 MODULE_DESCRIPTION("Atmel QSPI Controller driver");
0799 MODULE_LICENSE("GPL v2");
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