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0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2019, Linaro Limited
0003 
0004 #include <linux/clk.h>
0005 #include <linux/completion.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/io.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/debugfs.h>
0011 #include <linux/of.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/of_device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regmap.h>
0016 #include <linux/reset.h>
0017 #include <linux/slab.h>
0018 #include <linux/pm_wakeirq.h>
0019 #include <linux/slimbus.h>
0020 #include <linux/soundwire/sdw.h>
0021 #include <linux/soundwire/sdw_registers.h>
0022 #include <sound/pcm_params.h>
0023 #include <sound/soc.h>
0024 #include "bus.h"
0025 
0026 #define SWRM_COMP_SW_RESET                  0x008
0027 #define SWRM_COMP_STATUS                    0x014
0028 #define SWRM_FRM_GEN_ENABLED                    BIT(0)
0029 #define SWRM_COMP_HW_VERSION                    0x00
0030 #define SWRM_COMP_CFG_ADDR                  0x04
0031 #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK            BIT(1)
0032 #define SWRM_COMP_CFG_ENABLE_MSK                BIT(0)
0033 #define SWRM_COMP_PARAMS                    0x100
0034 #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH              GENMASK(14, 10)
0035 #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH              GENMASK(19, 15)
0036 #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK            GENMASK(4, 0)
0037 #define SWRM_COMP_PARAMS_DIN_PORTS_MASK             GENMASK(9, 5)
0038 #define SWRM_COMP_MASTER_ID                 0x104
0039 #define SWRM_INTERRUPT_STATUS                   0x200
0040 #define SWRM_INTERRUPT_STATUS_RMSK              GENMASK(16, 0)
0041 #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ            BIT(0)
0042 #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED        BIT(1)
0043 #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS      BIT(2)
0044 #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET          BIT(3)
0045 #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW          BIT(4)
0046 #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW         BIT(5)
0047 #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW      BIT(6)
0048 #define SWRM_INTERRUPT_STATUS_CMD_ERROR             BIT(7)
0049 #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION       BIT(8)
0050 #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH     BIT(9)
0051 #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED       BIT(10)
0052 #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2             BIT(13)
0053 #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2              BIT(14)
0054 #define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP               BIT(16)
0055 #define SWRM_INTERRUPT_MAX                  17
0056 #define SWRM_INTERRUPT_MASK_ADDR                0x204
0057 #define SWRM_INTERRUPT_CLEAR                    0x208
0058 #define SWRM_INTERRUPT_CPU_EN                   0x210
0059 #define SWRM_CMD_FIFO_WR_CMD                    0x300
0060 #define SWRM_CMD_FIFO_RD_CMD                    0x304
0061 #define SWRM_CMD_FIFO_CMD                   0x308
0062 #define SWRM_CMD_FIFO_FLUSH                 0x1
0063 #define SWRM_CMD_FIFO_STATUS                    0x30C
0064 #define SWRM_RD_CMD_FIFO_CNT_MASK               GENMASK(20, 16)
0065 #define SWRM_WR_CMD_FIFO_CNT_MASK               GENMASK(12, 8)
0066 #define SWRM_CMD_FIFO_CFG_ADDR                  0x314
0067 #define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE            BIT(31)
0068 #define SWRM_RD_WR_CMD_RETRIES                  0x7
0069 #define SWRM_CMD_FIFO_RD_FIFO_ADDR              0x318
0070 #define SWRM_RD_FIFO_CMD_ID_MASK                GENMASK(11, 8)
0071 #define SWRM_ENUMERATOR_CFG_ADDR                0x500
0072 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m)       (0x530 + 0x8 * (m))
0073 #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m)       (0x534 + 0x8 * (m))
0074 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)        (0x101C + 0x40 * (m))
0075 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK          GENMASK(2, 0)
0076 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK          GENMASK(7, 3)
0077 #define SWRM_MCP_BUS_CTRL                   0x1044
0078 #define SWRM_MCP_BUS_CLK_START                  BIT(1)
0079 #define SWRM_MCP_CFG_ADDR                   0x1048
0080 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK       GENMASK(21, 17)
0081 #define SWRM_DEF_CMD_NO_PINGS                   0x1f
0082 #define SWRM_MCP_STATUS                     0x104C
0083 #define SWRM_MCP_STATUS_BANK_NUM_MASK               BIT(0)
0084 #define SWRM_MCP_SLV_STATUS                 0x1090
0085 #define SWRM_MCP_SLV_STATUS_MASK                GENMASK(1, 0)
0086 #define SWRM_MCP_SLV_STATUS_SZ                  2
0087 #define SWRM_DP_PORT_CTRL_BANK(n, m)    (0x1124 + 0x100 * (n - 1) + 0x40 * m)
0088 #define SWRM_DP_PORT_CTRL_2_BANK(n, m)  (0x1128 + 0x100 * (n - 1) + 0x40 * m)
0089 #define SWRM_DP_BLOCK_CTRL_1(n)     (0x112C + 0x100 * (n - 1))
0090 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m)  (0x1130 + 0x100 * (n - 1) + 0x40 * m)
0091 #define SWRM_DP_PORT_HCTRL_BANK(n, m)   (0x1134 + 0x100 * (n - 1) + 0x40 * m)
0092 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m)  (0x1138 + 0x100 * (n - 1) + 0x40 * m)
0093 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n)   (0x1054 + 0x100 * (n - 1))
0094 #define SWR_MSTR_MAX_REG_ADDR       (0x1740)
0095 
0096 #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT              0x18
0097 #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT              0x10
0098 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT              0x08
0099 #define SWRM_AHB_BRIDGE_WR_DATA_0               0xc85
0100 #define SWRM_AHB_BRIDGE_WR_ADDR_0               0xc89
0101 #define SWRM_AHB_BRIDGE_RD_ADDR_0               0xc8d
0102 #define SWRM_AHB_BRIDGE_RD_DATA_0               0xc91
0103 
0104 #define SWRM_REG_VAL_PACK(data, dev, id, reg)   \
0105             ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
0106 
0107 #define SWRM_SPECIAL_CMD_ID 0xF
0108 #define MAX_FREQ_NUM        1
0109 #define TIMEOUT_MS      100
0110 #define QCOM_SWRM_MAX_RD_LEN    0x1
0111 #define QCOM_SDW_MAX_PORTS  14
0112 #define DEFAULT_CLK_FREQ    9600000
0113 #define SWRM_MAX_DAIS       0xF
0114 #define SWR_INVALID_PARAM 0xFF
0115 #define SWR_HSTOP_MAX_VAL 0xF
0116 #define SWR_HSTART_MIN_VAL 0x0
0117 #define SWR_BROADCAST_CMD_ID    0x0F
0118 #define SWR_MAX_CMD_ID  14
0119 #define MAX_FIFO_RD_RETRY 3
0120 #define SWR_OVERFLOW_RETRY_COUNT 30
0121 #define SWRM_LINK_STATUS_RETRY_CNT 100
0122 
0123 enum {
0124     MASTER_ID_WSA = 1,
0125     MASTER_ID_RX,
0126     MASTER_ID_TX
0127 };
0128 
0129 struct qcom_swrm_port_config {
0130     u8 si;
0131     u8 off1;
0132     u8 off2;
0133     u8 bp_mode;
0134     u8 hstart;
0135     u8 hstop;
0136     u8 word_length;
0137     u8 blk_group_count;
0138     u8 lane_control;
0139 };
0140 
0141 struct qcom_swrm_ctrl {
0142     struct sdw_bus bus;
0143     struct device *dev;
0144     struct regmap *regmap;
0145     void __iomem *mmio;
0146     struct reset_control *audio_cgcr;
0147 #ifdef CONFIG_DEBUG_FS
0148     struct dentry *debugfs;
0149 #endif
0150     struct completion broadcast;
0151     struct completion enumeration;
0152     struct work_struct slave_work;
0153     /* Port alloc/free lock */
0154     struct mutex port_lock;
0155     struct clk *hclk;
0156     u8 wr_cmd_id;
0157     u8 rd_cmd_id;
0158     int irq;
0159     unsigned int version;
0160     int wake_irq;
0161     int num_din_ports;
0162     int num_dout_ports;
0163     int cols_index;
0164     int rows_index;
0165     unsigned long dout_port_mask;
0166     unsigned long din_port_mask;
0167     u32 intr_mask;
0168     u8 rcmd_id;
0169     u8 wcmd_id;
0170     struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
0171     struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
0172     enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
0173     int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
0174     int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
0175     u32 slave_status;
0176     u32 wr_fifo_depth;
0177     u32 rd_fifo_depth;
0178     bool clock_stop_not_supported;
0179 };
0180 
0181 struct qcom_swrm_data {
0182     u32 default_cols;
0183     u32 default_rows;
0184     bool sw_clk_gate_required;
0185 };
0186 
0187 static const struct qcom_swrm_data swrm_v1_3_data = {
0188     .default_rows = 48,
0189     .default_cols = 16,
0190 };
0191 
0192 static const struct qcom_swrm_data swrm_v1_5_data = {
0193     .default_rows = 50,
0194     .default_cols = 16,
0195 };
0196 
0197 static const struct qcom_swrm_data swrm_v1_6_data = {
0198     .default_rows = 50,
0199     .default_cols = 16,
0200     .sw_clk_gate_required = true,
0201 };
0202 
0203 #define to_qcom_sdw(b)  container_of(b, struct qcom_swrm_ctrl, bus)
0204 
0205 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
0206                   u32 *val)
0207 {
0208     struct regmap *wcd_regmap = ctrl->regmap;
0209     int ret;
0210 
0211     /* pg register + offset */
0212     ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
0213               (u8 *)&reg, 4);
0214     if (ret < 0)
0215         return SDW_CMD_FAIL;
0216 
0217     ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
0218                    val, 4);
0219     if (ret < 0)
0220         return SDW_CMD_FAIL;
0221 
0222     return SDW_CMD_OK;
0223 }
0224 
0225 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
0226                    int reg, int val)
0227 {
0228     struct regmap *wcd_regmap = ctrl->regmap;
0229     int ret;
0230     /* pg register + offset */
0231     ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
0232               (u8 *)&val, 4);
0233     if (ret)
0234         return SDW_CMD_FAIL;
0235 
0236     /* write address register */
0237     ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
0238               (u8 *)&reg, 4);
0239     if (ret)
0240         return SDW_CMD_FAIL;
0241 
0242     return SDW_CMD_OK;
0243 }
0244 
0245 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
0246                   u32 *val)
0247 {
0248     *val = readl(ctrl->mmio + reg);
0249     return SDW_CMD_OK;
0250 }
0251 
0252 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
0253                    int val)
0254 {
0255     writel(val, ctrl->mmio + reg);
0256     return SDW_CMD_OK;
0257 }
0258 
0259 static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
0260                    u8 dev_addr, u16 reg_addr)
0261 {
0262     u32 val;
0263     u8 id = *cmd_id;
0264 
0265     if (id != SWR_BROADCAST_CMD_ID) {
0266         if (id < SWR_MAX_CMD_ID)
0267             id += 1;
0268         else
0269             id = 0;
0270         *cmd_id = id;
0271     }
0272     val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
0273 
0274     return val;
0275 }
0276 
0277 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *swrm)
0278 {
0279     u32 fifo_outstanding_data, value;
0280     int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
0281 
0282     do {
0283         /* Check for fifo underflow during read */
0284         swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
0285         fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
0286 
0287         /* Check if read data is available in read fifo */
0288         if (fifo_outstanding_data > 0)
0289             return 0;
0290 
0291         usleep_range(500, 510);
0292     } while (fifo_retry_count--);
0293 
0294     if (fifo_outstanding_data == 0) {
0295         dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__);
0296         return -EIO;
0297     }
0298 
0299     return 0;
0300 }
0301 
0302 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *swrm)
0303 {
0304     u32 fifo_outstanding_cmds, value;
0305     int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
0306 
0307     do {
0308         /* Check for fifo overflow during write */
0309         swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
0310         fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
0311 
0312         /* Check for space in write fifo before writing */
0313         if (fifo_outstanding_cmds < swrm->wr_fifo_depth)
0314             return 0;
0315 
0316         usleep_range(500, 510);
0317     } while (fifo_retry_count--);
0318 
0319     if (fifo_outstanding_cmds == swrm->wr_fifo_depth) {
0320         dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__);
0321         return -EIO;
0322     }
0323 
0324     return 0;
0325 }
0326 
0327 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *swrm, u8 cmd_data,
0328                      u8 dev_addr, u16 reg_addr)
0329 {
0330 
0331     u32 val;
0332     int ret = 0;
0333     u8 cmd_id = 0x0;
0334 
0335     if (dev_addr == SDW_BROADCAST_DEV_NUM) {
0336         cmd_id = SWR_BROADCAST_CMD_ID;
0337         val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
0338                           dev_addr, reg_addr);
0339     } else {
0340         val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
0341                           dev_addr, reg_addr);
0342     }
0343 
0344     if (swrm_wait_for_wr_fifo_avail(swrm))
0345         return SDW_CMD_FAIL_OTHER;
0346 
0347     /* Its assumed that write is okay as we do not get any status back */
0348     swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);
0349 
0350     /* version 1.3 or less */
0351     if (swrm->version <= 0x01030000)
0352         usleep_range(150, 155);
0353 
0354     if (cmd_id == SWR_BROADCAST_CMD_ID) {
0355         /*
0356          * sleep for 10ms for MSM soundwire variant to allow broadcast
0357          * command to complete.
0358          */
0359         ret = wait_for_completion_timeout(&swrm->broadcast,
0360                           msecs_to_jiffies(TIMEOUT_MS));
0361         if (!ret)
0362             ret = SDW_CMD_IGNORED;
0363         else
0364             ret = SDW_CMD_OK;
0365 
0366     } else {
0367         ret = SDW_CMD_OK;
0368     }
0369     return ret;
0370 }
0371 
0372 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *swrm,
0373                      u8 dev_addr, u16 reg_addr,
0374                      u32 len, u8 *rval)
0375 {
0376     u32 cmd_data, cmd_id, val, retry_attempt = 0;
0377 
0378     val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
0379 
0380     /* wait for FIFO RD to complete to avoid overflow */
0381     usleep_range(100, 105);
0382     swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
0383     /* wait for FIFO RD CMD complete to avoid overflow */
0384     usleep_range(250, 255);
0385 
0386     if (swrm_wait_for_rd_fifo_avail(swrm))
0387         return SDW_CMD_FAIL_OTHER;
0388 
0389     do {
0390         swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data);
0391         rval[0] = cmd_data & 0xFF;
0392         cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
0393 
0394         if (cmd_id != swrm->rcmd_id) {
0395             if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
0396                 /* wait 500 us before retry on fifo read failure */
0397                 usleep_range(500, 505);
0398                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,
0399                         SWRM_CMD_FIFO_FLUSH);
0400                 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);
0401             }
0402             retry_attempt++;
0403         } else {
0404             return SDW_CMD_OK;
0405         }
0406 
0407     } while (retry_attempt < MAX_FIFO_RD_RETRY);
0408 
0409     dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
0410         dev_num: 0x%x, cmd_data: 0x%x\n",
0411         reg_addr, swrm->rcmd_id, dev_addr, cmd_data);
0412 
0413     return SDW_CMD_IGNORED;
0414 }
0415 
0416 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
0417 {
0418     u32 val, status;
0419     int dev_num;
0420 
0421     ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
0422 
0423     for (dev_num = 0; dev_num <= SDW_MAX_DEVICES; dev_num++) {
0424         status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
0425 
0426         if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
0427             ctrl->status[dev_num] = status;
0428             return dev_num;
0429         }
0430     }
0431 
0432     return -EINVAL;
0433 }
0434 
0435 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
0436 {
0437     u32 val;
0438     int i;
0439 
0440     ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
0441     ctrl->slave_status = val;
0442 
0443     for (i = 0; i <= SDW_MAX_DEVICES; i++) {
0444         u32 s;
0445 
0446         s = (val >> (i * 2));
0447         s &= SWRM_MCP_SLV_STATUS_MASK;
0448         ctrl->status[i] = s;
0449     }
0450 }
0451 
0452 static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
0453                     struct sdw_slave *slave, int devnum)
0454 {
0455     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0456     u32 status;
0457 
0458     ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
0459     status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
0460     status &= SWRM_MCP_SLV_STATUS_MASK;
0461 
0462     if (status == SDW_SLAVE_ATTACHED) {
0463         if (slave)
0464             slave->dev_num = devnum;
0465         mutex_lock(&bus->bus_lock);
0466         set_bit(devnum, bus->assigned);
0467         mutex_unlock(&bus->bus_lock);
0468     }
0469 }
0470 
0471 static int qcom_swrm_enumerate(struct sdw_bus *bus)
0472 {
0473     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0474     struct sdw_slave *slave, *_s;
0475     struct sdw_slave_id id;
0476     u32 val1, val2;
0477     bool found;
0478     u64 addr;
0479     int i;
0480     char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
0481 
0482     for (i = 1; i <= SDW_MAX_DEVICES; i++) {
0483         /* do not continue if the status is Not Present  */
0484         if (!ctrl->status[i])
0485             continue;
0486 
0487         /*SCP_Devid5 - Devid 4*/
0488         ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
0489 
0490         /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
0491         ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
0492 
0493         if (!val1 && !val2)
0494             break;
0495 
0496         addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
0497             ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
0498             ((u64)buf1[0] << 40);
0499 
0500         sdw_extract_slave_id(bus, addr, &id);
0501         found = false;
0502         /* Now compare with entries */
0503         list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
0504             if (sdw_compare_devid(slave, id) == 0) {
0505                 qcom_swrm_set_slave_dev_num(bus, slave, i);
0506                 found = true;
0507                 break;
0508             }
0509         }
0510 
0511         if (!found) {
0512             qcom_swrm_set_slave_dev_num(bus, NULL, i);
0513             sdw_slave_add(bus, &id, NULL);
0514         }
0515     }
0516 
0517     complete(&ctrl->enumeration);
0518     return 0;
0519 }
0520 
0521 static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
0522 {
0523     struct qcom_swrm_ctrl *swrm = dev_id;
0524     int ret;
0525 
0526     ret = pm_runtime_resume_and_get(swrm->dev);
0527     if (ret < 0 && ret != -EACCES) {
0528         dev_err_ratelimited(swrm->dev,
0529                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
0530                     __func__, ret);
0531         return ret;
0532     }
0533 
0534     if (swrm->wake_irq > 0) {
0535         if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq)))
0536             disable_irq_nosync(swrm->wake_irq);
0537     }
0538 
0539     pm_runtime_mark_last_busy(swrm->dev);
0540     pm_runtime_put_autosuspend(swrm->dev);
0541 
0542     return IRQ_HANDLED;
0543 }
0544 
0545 static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
0546 {
0547     struct qcom_swrm_ctrl *swrm = dev_id;
0548     u32 value, intr_sts, intr_sts_masked, slave_status;
0549     u32 i;
0550     int devnum;
0551     int ret = IRQ_HANDLED;
0552     clk_prepare_enable(swrm->hclk);
0553 
0554     swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
0555     intr_sts_masked = intr_sts & swrm->intr_mask;
0556 
0557     do {
0558         for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
0559             value = intr_sts_masked & BIT(i);
0560             if (!value)
0561                 continue;
0562 
0563             switch (value) {
0564             case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
0565                 devnum = qcom_swrm_get_alert_slave_dev_num(swrm);
0566                 if (devnum < 0) {
0567                     dev_err_ratelimited(swrm->dev,
0568                         "no slave alert found.spurious interrupt\n");
0569                 } else {
0570                     sdw_handle_slave_status(&swrm->bus, swrm->status);
0571                 }
0572 
0573                 break;
0574             case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
0575             case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
0576                 dev_err_ratelimited(swrm->dev, "%s: SWR new slave attached\n",
0577                     __func__);
0578                 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status);
0579                 if (swrm->slave_status == slave_status) {
0580                     dev_err(swrm->dev, "Slave status not changed %x\n",
0581                         slave_status);
0582                 } else {
0583                     qcom_swrm_get_device_status(swrm);
0584                     qcom_swrm_enumerate(&swrm->bus);
0585                     sdw_handle_slave_status(&swrm->bus, swrm->status);
0586                 }
0587                 break;
0588             case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
0589                 dev_err_ratelimited(swrm->dev,
0590                         "%s: SWR bus clsh detected\n",
0591                         __func__);
0592                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
0593                 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
0594                 break;
0595             case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
0596                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
0597                 dev_err_ratelimited(swrm->dev,
0598                     "%s: SWR read FIFO overflow fifo status 0x%x\n",
0599                     __func__, value);
0600                 break;
0601             case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
0602                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
0603                 dev_err_ratelimited(swrm->dev,
0604                     "%s: SWR read FIFO underflow fifo status 0x%x\n",
0605                     __func__, value);
0606                 break;
0607             case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
0608                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
0609                 dev_err(swrm->dev,
0610                     "%s: SWR write FIFO overflow fifo status %x\n",
0611                     __func__, value);
0612                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
0613                 break;
0614             case SWRM_INTERRUPT_STATUS_CMD_ERROR:
0615                 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value);
0616                 dev_err_ratelimited(swrm->dev,
0617                     "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
0618                     __func__, value);
0619                 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
0620                 break;
0621             case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
0622                 dev_err_ratelimited(swrm->dev,
0623                         "%s: SWR Port collision detected\n",
0624                         __func__);
0625                 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
0626                 swrm->reg_write(swrm,
0627                     SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
0628                 break;
0629             case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
0630                 dev_err_ratelimited(swrm->dev,
0631                     "%s: SWR read enable valid mismatch\n",
0632                     __func__);
0633                 swrm->intr_mask &=
0634                     ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
0635                 swrm->reg_write(swrm,
0636                     SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);
0637                 break;
0638             case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
0639                 complete(&swrm->broadcast);
0640                 break;
0641             case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
0642                 break;
0643             case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
0644                 break;
0645             case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
0646                 break;
0647             default:
0648                 dev_err_ratelimited(swrm->dev,
0649                         "%s: SWR unknown interrupt value: %d\n",
0650                         __func__, value);
0651                 ret = IRQ_NONE;
0652                 break;
0653             }
0654         }
0655         swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);
0656         swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts);
0657         intr_sts_masked = intr_sts & swrm->intr_mask;
0658     } while (intr_sts_masked);
0659 
0660     clk_disable_unprepare(swrm->hclk);
0661     return ret;
0662 }
0663 
0664 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
0665 {
0666     u32 val;
0667 
0668     /* Clear Rows and Cols */
0669     val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
0670     val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
0671 
0672     reset_control_reset(ctrl->audio_cgcr);
0673 
0674     ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
0675 
0676     /* Enable Auto enumeration */
0677     ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
0678 
0679     ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
0680     /* Mask soundwire interrupts */
0681     ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
0682             SWRM_INTERRUPT_STATUS_RMSK);
0683 
0684     /* Configure No pings */
0685     ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
0686     u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
0687     ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
0688 
0689     ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
0690     /* Configure number of retries of a read/write cmd */
0691     if (ctrl->version > 0x01050001) {
0692         /* Only for versions >= 1.5.1 */
0693         ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
0694                 SWRM_RD_WR_CMD_RETRIES |
0695                 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
0696     } else {
0697         ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
0698                 SWRM_RD_WR_CMD_RETRIES);
0699     }
0700 
0701     /* Set IRQ to PULSE */
0702     ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
0703             SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
0704             SWRM_COMP_CFG_ENABLE_MSK);
0705 
0706     /* enable CPU IRQs */
0707     if (ctrl->mmio) {
0708         ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
0709                 SWRM_INTERRUPT_STATUS_RMSK);
0710     }
0711     ctrl->slave_status = 0;
0712     ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
0713     ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
0714     ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
0715 
0716     return 0;
0717 }
0718 
0719 static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
0720                             struct sdw_msg *msg)
0721 {
0722     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0723     int ret, i, len;
0724 
0725     if (msg->flags == SDW_MSG_FLAG_READ) {
0726         for (i = 0; i < msg->len;) {
0727             if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
0728                 len = msg->len - i;
0729             else
0730                 len = QCOM_SWRM_MAX_RD_LEN;
0731 
0732             ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
0733                             msg->addr + i, len,
0734                                &msg->buf[i]);
0735             if (ret)
0736                 return ret;
0737 
0738             i = i + len;
0739         }
0740     } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
0741         for (i = 0; i < msg->len; i++) {
0742             ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
0743                             msg->dev_num,
0744                                msg->addr + i);
0745             if (ret)
0746                 return SDW_CMD_IGNORED;
0747         }
0748     }
0749 
0750     return SDW_CMD_OK;
0751 }
0752 
0753 static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
0754 {
0755     u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
0756     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0757     u32 val;
0758 
0759     ctrl->reg_read(ctrl, reg, &val);
0760 
0761     u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
0762     u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
0763 
0764     return ctrl->reg_write(ctrl, reg, val);
0765 }
0766 
0767 static int qcom_swrm_port_params(struct sdw_bus *bus,
0768                  struct sdw_port_params *p_params,
0769                  unsigned int bank)
0770 {
0771     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0772 
0773     return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
0774                    p_params->bps - 1);
0775 
0776 }
0777 
0778 static int qcom_swrm_transport_params(struct sdw_bus *bus,
0779                       struct sdw_transport_params *params,
0780                       enum sdw_reg_bank bank)
0781 {
0782     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0783     struct qcom_swrm_port_config *pcfg;
0784     u32 value;
0785     int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
0786     int ret;
0787 
0788     pcfg = &ctrl->pconfig[params->port_num];
0789 
0790     value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
0791     value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
0792     value |= pcfg->si;
0793 
0794     ret = ctrl->reg_write(ctrl, reg, value);
0795     if (ret)
0796         goto err;
0797 
0798     if (pcfg->lane_control != SWR_INVALID_PARAM) {
0799         reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
0800         value = pcfg->lane_control;
0801         ret = ctrl->reg_write(ctrl, reg, value);
0802         if (ret)
0803             goto err;
0804     }
0805 
0806     if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
0807         reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
0808         value = pcfg->blk_group_count;
0809         ret = ctrl->reg_write(ctrl, reg, value);
0810         if (ret)
0811             goto err;
0812     }
0813 
0814     if (pcfg->hstart != SWR_INVALID_PARAM
0815             && pcfg->hstop != SWR_INVALID_PARAM) {
0816         reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
0817         value = (pcfg->hstop << 4) | pcfg->hstart;
0818         ret = ctrl->reg_write(ctrl, reg, value);
0819     } else {
0820         reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
0821         value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
0822         ret = ctrl->reg_write(ctrl, reg, value);
0823     }
0824 
0825     if (ret)
0826         goto err;
0827 
0828     if (pcfg->bp_mode != SWR_INVALID_PARAM) {
0829         reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
0830         ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
0831     }
0832 
0833 err:
0834     return ret;
0835 }
0836 
0837 static int qcom_swrm_port_enable(struct sdw_bus *bus,
0838                  struct sdw_enable_ch *enable_ch,
0839                  unsigned int bank)
0840 {
0841     u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
0842     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0843     u32 val;
0844 
0845     ctrl->reg_read(ctrl, reg, &val);
0846 
0847     if (enable_ch->enable)
0848         val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
0849     else
0850         val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
0851 
0852     return ctrl->reg_write(ctrl, reg, val);
0853 }
0854 
0855 static const struct sdw_master_port_ops qcom_swrm_port_ops = {
0856     .dpn_set_port_params = qcom_swrm_port_params,
0857     .dpn_set_port_transport_params = qcom_swrm_transport_params,
0858     .dpn_port_enable_ch = qcom_swrm_port_enable,
0859 };
0860 
0861 static const struct sdw_master_ops qcom_swrm_ops = {
0862     .xfer_msg = qcom_swrm_xfer_msg,
0863     .pre_bank_switch = qcom_swrm_pre_bank_switch,
0864 };
0865 
0866 static int qcom_swrm_compute_params(struct sdw_bus *bus)
0867 {
0868     struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
0869     struct sdw_master_runtime *m_rt;
0870     struct sdw_slave_runtime *s_rt;
0871     struct sdw_port_runtime *p_rt;
0872     struct qcom_swrm_port_config *pcfg;
0873     struct sdw_slave *slave;
0874     unsigned int m_port;
0875     int i = 1;
0876 
0877     list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
0878         list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
0879             pcfg = &ctrl->pconfig[p_rt->num];
0880             p_rt->transport_params.port_num = p_rt->num;
0881             if (pcfg->word_length != SWR_INVALID_PARAM) {
0882                 sdw_fill_port_params(&p_rt->port_params,
0883                          p_rt->num,  pcfg->word_length + 1,
0884                          SDW_PORT_FLOW_MODE_ISOCH,
0885                          SDW_PORT_DATA_MODE_NORMAL);
0886             }
0887 
0888         }
0889 
0890         list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
0891             slave = s_rt->slave;
0892             list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
0893                 m_port = slave->m_port_map[p_rt->num];
0894                 /* port config starts at offset 0 so -1 from actual port number */
0895                 if (m_port)
0896                     pcfg = &ctrl->pconfig[m_port];
0897                 else
0898                     pcfg = &ctrl->pconfig[i];
0899                 p_rt->transport_params.port_num = p_rt->num;
0900                 p_rt->transport_params.sample_interval =
0901                     pcfg->si + 1;
0902                 p_rt->transport_params.offset1 = pcfg->off1;
0903                 p_rt->transport_params.offset2 = pcfg->off2;
0904                 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
0905                 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
0906 
0907                 p_rt->transport_params.hstart = pcfg->hstart;
0908                 p_rt->transport_params.hstop = pcfg->hstop;
0909                 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
0910                 if (pcfg->word_length != SWR_INVALID_PARAM) {
0911                     sdw_fill_port_params(&p_rt->port_params,
0912                              p_rt->num,
0913                              pcfg->word_length + 1,
0914                              SDW_PORT_FLOW_MODE_ISOCH,
0915                              SDW_PORT_DATA_MODE_NORMAL);
0916                 }
0917                 i++;
0918             }
0919         }
0920     }
0921 
0922     return 0;
0923 }
0924 
0925 static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
0926     DEFAULT_CLK_FREQ,
0927 };
0928 
0929 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
0930                     struct sdw_stream_runtime *stream)
0931 {
0932     struct sdw_master_runtime *m_rt;
0933     struct sdw_port_runtime *p_rt;
0934     unsigned long *port_mask;
0935 
0936     mutex_lock(&ctrl->port_lock);
0937 
0938     list_for_each_entry(m_rt, &stream->master_list, stream_node) {
0939         if (m_rt->direction == SDW_DATA_DIR_RX)
0940             port_mask = &ctrl->dout_port_mask;
0941         else
0942             port_mask = &ctrl->din_port_mask;
0943 
0944         list_for_each_entry(p_rt, &m_rt->port_list, port_node)
0945             clear_bit(p_rt->num, port_mask);
0946     }
0947 
0948     mutex_unlock(&ctrl->port_lock);
0949 }
0950 
0951 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
0952                     struct sdw_stream_runtime *stream,
0953                        struct snd_pcm_hw_params *params,
0954                        int direction)
0955 {
0956     struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
0957     struct sdw_stream_config sconfig;
0958     struct sdw_master_runtime *m_rt;
0959     struct sdw_slave_runtime *s_rt;
0960     struct sdw_port_runtime *p_rt;
0961     struct sdw_slave *slave;
0962     unsigned long *port_mask;
0963     int i, maxport, pn, nports = 0, ret = 0;
0964     unsigned int m_port;
0965 
0966     mutex_lock(&ctrl->port_lock);
0967     list_for_each_entry(m_rt, &stream->master_list, stream_node) {
0968         if (m_rt->direction == SDW_DATA_DIR_RX) {
0969             maxport = ctrl->num_dout_ports;
0970             port_mask = &ctrl->dout_port_mask;
0971         } else {
0972             maxport = ctrl->num_din_ports;
0973             port_mask = &ctrl->din_port_mask;
0974         }
0975 
0976         list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
0977             slave = s_rt->slave;
0978             list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
0979                 m_port = slave->m_port_map[p_rt->num];
0980                 /* Port numbers start from 1 - 14*/
0981                 if (m_port)
0982                     pn = m_port;
0983                 else
0984                     pn = find_first_zero_bit(port_mask, maxport);
0985 
0986                 if (pn > maxport) {
0987                     dev_err(ctrl->dev, "All ports busy\n");
0988                     ret = -EBUSY;
0989                     goto err;
0990                 }
0991                 set_bit(pn, port_mask);
0992                 pconfig[nports].num = pn;
0993                 pconfig[nports].ch_mask = p_rt->ch_mask;
0994                 nports++;
0995             }
0996         }
0997     }
0998 
0999     if (direction == SNDRV_PCM_STREAM_CAPTURE)
1000         sconfig.direction = SDW_DATA_DIR_TX;
1001     else
1002         sconfig.direction = SDW_DATA_DIR_RX;
1003 
1004     /* hw parameters wil be ignored as we only support PDM */
1005     sconfig.ch_count = 1;
1006     sconfig.frame_rate = params_rate(params);
1007     sconfig.type = stream->type;
1008     sconfig.bps = 1;
1009     sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1010                   nports, stream);
1011 err:
1012     if (ret) {
1013         for (i = 0; i < nports; i++)
1014             clear_bit(pconfig[i].num, port_mask);
1015     }
1016 
1017     mutex_unlock(&ctrl->port_lock);
1018 
1019     return ret;
1020 }
1021 
1022 static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1023                    struct snd_pcm_hw_params *params,
1024                   struct snd_soc_dai *dai)
1025 {
1026     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1027     struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1028     int ret;
1029 
1030     ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1031                        substream->stream);
1032     if (ret)
1033         qcom_swrm_stream_free_ports(ctrl, sruntime);
1034 
1035     return ret;
1036 }
1037 
1038 static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1039                  struct snd_soc_dai *dai)
1040 {
1041     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1042     struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1043 
1044     qcom_swrm_stream_free_ports(ctrl, sruntime);
1045     sdw_stream_remove_master(&ctrl->bus, sruntime);
1046 
1047     return 0;
1048 }
1049 
1050 static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1051                     void *stream, int direction)
1052 {
1053     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1054 
1055     ctrl->sruntime[dai->id] = stream;
1056 
1057     return 0;
1058 }
1059 
1060 static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1061 {
1062     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1063 
1064     return ctrl->sruntime[dai->id];
1065 }
1066 
1067 static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1068                  struct snd_soc_dai *dai)
1069 {
1070     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1071     struct snd_soc_pcm_runtime *rtd = substream->private_data;
1072     struct sdw_stream_runtime *sruntime;
1073     struct snd_soc_dai *codec_dai;
1074     int ret, i;
1075 
1076     ret = pm_runtime_resume_and_get(ctrl->dev);
1077     if (ret < 0 && ret != -EACCES) {
1078         dev_err_ratelimited(ctrl->dev,
1079                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1080                     __func__, ret);
1081         return ret;
1082     }
1083 
1084     sruntime = sdw_alloc_stream(dai->name);
1085     if (!sruntime)
1086         return -ENOMEM;
1087 
1088     ctrl->sruntime[dai->id] = sruntime;
1089 
1090     for_each_rtd_codec_dais(rtd, i, codec_dai) {
1091         ret = snd_soc_dai_set_stream(codec_dai, sruntime,
1092                          substream->stream);
1093         if (ret < 0 && ret != -ENOTSUPP) {
1094             dev_err(dai->dev, "Failed to set sdw stream on %s\n",
1095                 codec_dai->name);
1096             sdw_release_stream(sruntime);
1097             return ret;
1098         }
1099     }
1100 
1101     return 0;
1102 }
1103 
1104 static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1105                    struct snd_soc_dai *dai)
1106 {
1107     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1108 
1109     sdw_release_stream(ctrl->sruntime[dai->id]);
1110     ctrl->sruntime[dai->id] = NULL;
1111     pm_runtime_mark_last_busy(ctrl->dev);
1112     pm_runtime_put_autosuspend(ctrl->dev);
1113 
1114 }
1115 
1116 static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1117     .hw_params = qcom_swrm_hw_params,
1118     .hw_free = qcom_swrm_hw_free,
1119     .startup = qcom_swrm_startup,
1120     .shutdown = qcom_swrm_shutdown,
1121     .set_stream = qcom_swrm_set_sdw_stream,
1122     .get_stream = qcom_swrm_get_sdw_stream,
1123 };
1124 
1125 static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1126     .name = "soundwire",
1127 };
1128 
1129 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1130 {
1131     int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1132     struct snd_soc_dai_driver *dais;
1133     struct snd_soc_pcm_stream *stream;
1134     struct device *dev = ctrl->dev;
1135     int i;
1136 
1137     /* PDM dais are only tested for now */
1138     dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1139     if (!dais)
1140         return -ENOMEM;
1141 
1142     for (i = 0; i < num_dais; i++) {
1143         dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1144         if (!dais[i].name)
1145             return -ENOMEM;
1146 
1147         if (i < ctrl->num_dout_ports)
1148             stream = &dais[i].playback;
1149         else
1150             stream = &dais[i].capture;
1151 
1152         stream->channels_min = 1;
1153         stream->channels_max = 1;
1154         stream->rates = SNDRV_PCM_RATE_48000;
1155         stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1156 
1157         dais[i].ops = &qcom_swrm_pdm_dai_ops;
1158         dais[i].id = i;
1159     }
1160 
1161     return devm_snd_soc_register_component(ctrl->dev,
1162                         &qcom_swrm_dai_component,
1163                         dais, num_dais);
1164 }
1165 
1166 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1167 {
1168     struct device_node *np = ctrl->dev->of_node;
1169     u8 off1[QCOM_SDW_MAX_PORTS];
1170     u8 off2[QCOM_SDW_MAX_PORTS];
1171     u8 si[QCOM_SDW_MAX_PORTS];
1172     u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
1173     u8 hstart[QCOM_SDW_MAX_PORTS];
1174     u8 hstop[QCOM_SDW_MAX_PORTS];
1175     u8 word_length[QCOM_SDW_MAX_PORTS];
1176     u8 blk_group_count[QCOM_SDW_MAX_PORTS];
1177     u8 lane_control[QCOM_SDW_MAX_PORTS];
1178     int i, ret, nports, val;
1179 
1180     ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1181 
1182     ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1183     ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1184 
1185     ret = of_property_read_u32(np, "qcom,din-ports", &val);
1186     if (ret)
1187         return ret;
1188 
1189     if (val > ctrl->num_din_ports)
1190         return -EINVAL;
1191 
1192     ctrl->num_din_ports = val;
1193 
1194     ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1195     if (ret)
1196         return ret;
1197 
1198     if (val > ctrl->num_dout_ports)
1199         return -EINVAL;
1200 
1201     ctrl->num_dout_ports = val;
1202 
1203     nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1204     /* Valid port numbers are from 1-14, so mask out port 0 explicitly */
1205     set_bit(0, &ctrl->dout_port_mask);
1206     set_bit(0, &ctrl->din_port_mask);
1207 
1208     ret = of_property_read_u8_array(np, "qcom,ports-offset1",
1209                     off1, nports);
1210     if (ret)
1211         return ret;
1212 
1213     ret = of_property_read_u8_array(np, "qcom,ports-offset2",
1214                     off2, nports);
1215     if (ret)
1216         return ret;
1217 
1218     ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
1219                     si, nports);
1220     if (ret)
1221         return ret;
1222 
1223     ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
1224                     bp_mode, nports);
1225     if (ret) {
1226         if (ctrl->version <= 0x01030000)
1227             memset(bp_mode, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1228         else
1229             return ret;
1230     }
1231 
1232     memset(hstart, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1233     of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports);
1234 
1235     memset(hstop, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1236     of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports);
1237 
1238     memset(word_length, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1239     of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports);
1240 
1241     memset(blk_group_count, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1242     of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports);
1243 
1244     memset(lane_control, SWR_INVALID_PARAM, QCOM_SDW_MAX_PORTS);
1245     of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports);
1246 
1247     for (i = 0; i < nports; i++) {
1248         /* Valid port number range is from 1-14 */
1249         ctrl->pconfig[i + 1].si = si[i];
1250         ctrl->pconfig[i + 1].off1 = off1[i];
1251         ctrl->pconfig[i + 1].off2 = off2[i];
1252         ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1253         ctrl->pconfig[i + 1].hstart = hstart[i];
1254         ctrl->pconfig[i + 1].hstop = hstop[i];
1255         ctrl->pconfig[i + 1].word_length = word_length[i];
1256         ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1257         ctrl->pconfig[i + 1].lane_control = lane_control[i];
1258     }
1259 
1260     return 0;
1261 }
1262 
1263 #ifdef CONFIG_DEBUG_FS
1264 static int swrm_reg_show(struct seq_file *s_file, void *data)
1265 {
1266     struct qcom_swrm_ctrl *swrm = s_file->private;
1267     int reg, reg_val, ret;
1268 
1269     ret = pm_runtime_resume_and_get(swrm->dev);
1270     if (ret < 0 && ret != -EACCES) {
1271         dev_err_ratelimited(swrm->dev,
1272                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
1273                     __func__, ret);
1274         return ret;
1275     }
1276 
1277     for (reg = 0; reg <= SWR_MSTR_MAX_REG_ADDR; reg += 4) {
1278         swrm->reg_read(swrm, reg, &reg_val);
1279         seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1280     }
1281     pm_runtime_mark_last_busy(swrm->dev);
1282     pm_runtime_put_autosuspend(swrm->dev);
1283 
1284 
1285     return 0;
1286 }
1287 DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1288 #endif
1289 
1290 static int qcom_swrm_probe(struct platform_device *pdev)
1291 {
1292     struct device *dev = &pdev->dev;
1293     struct sdw_master_prop *prop;
1294     struct sdw_bus_params *params;
1295     struct qcom_swrm_ctrl *ctrl;
1296     const struct qcom_swrm_data *data;
1297     int ret;
1298     u32 val;
1299 
1300     ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1301     if (!ctrl)
1302         return -ENOMEM;
1303 
1304     data = of_device_get_match_data(dev);
1305     ctrl->rows_index = sdw_find_row_index(data->default_rows);
1306     ctrl->cols_index = sdw_find_col_index(data->default_cols);
1307 #if IS_REACHABLE(CONFIG_SLIMBUS)
1308     if (dev->parent->bus == &slimbus_bus) {
1309 #else
1310     if (false) {
1311 #endif
1312         ctrl->reg_read = qcom_swrm_ahb_reg_read;
1313         ctrl->reg_write = qcom_swrm_ahb_reg_write;
1314         ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1315         if (!ctrl->regmap)
1316             return -EINVAL;
1317     } else {
1318         ctrl->reg_read = qcom_swrm_cpu_reg_read;
1319         ctrl->reg_write = qcom_swrm_cpu_reg_write;
1320         ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1321         if (IS_ERR(ctrl->mmio))
1322             return PTR_ERR(ctrl->mmio);
1323     }
1324 
1325     if (data->sw_clk_gate_required) {
1326         ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr");
1327         if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) {
1328             dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1329             ret = PTR_ERR(ctrl->audio_cgcr);
1330             goto err_init;
1331         }
1332     }
1333 
1334     ctrl->irq = of_irq_get(dev->of_node, 0);
1335     if (ctrl->irq < 0) {
1336         ret = ctrl->irq;
1337         goto err_init;
1338     }
1339 
1340     ctrl->hclk = devm_clk_get(dev, "iface");
1341     if (IS_ERR(ctrl->hclk)) {
1342         ret = PTR_ERR(ctrl->hclk);
1343         goto err_init;
1344     }
1345 
1346     clk_prepare_enable(ctrl->hclk);
1347 
1348     ctrl->dev = dev;
1349     dev_set_drvdata(&pdev->dev, ctrl);
1350     mutex_init(&ctrl->port_lock);
1351     init_completion(&ctrl->broadcast);
1352     init_completion(&ctrl->enumeration);
1353 
1354     ctrl->bus.ops = &qcom_swrm_ops;
1355     ctrl->bus.port_ops = &qcom_swrm_port_ops;
1356     ctrl->bus.compute_params = &qcom_swrm_compute_params;
1357     ctrl->bus.clk_stop_timeout = 300;
1358 
1359     ret = qcom_swrm_get_port_config(ctrl);
1360     if (ret)
1361         goto err_clk;
1362 
1363     params = &ctrl->bus.params;
1364     params->max_dr_freq = DEFAULT_CLK_FREQ;
1365     params->curr_dr_freq = DEFAULT_CLK_FREQ;
1366     params->col = data->default_cols;
1367     params->row = data->default_rows;
1368     ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1369     params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1370     params->next_bank = !params->curr_bank;
1371 
1372     prop = &ctrl->bus.prop;
1373     prop->max_clk_freq = DEFAULT_CLK_FREQ;
1374     prop->num_clk_gears = 0;
1375     prop->num_clk_freq = MAX_FREQ_NUM;
1376     prop->clk_freq = &qcom_swrm_freq_tbl[0];
1377     prop->default_col = data->default_cols;
1378     prop->default_row = data->default_rows;
1379 
1380     ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1381 
1382     ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1383                     qcom_swrm_irq_handler,
1384                     IRQF_TRIGGER_RISING |
1385                     IRQF_ONESHOT,
1386                     "soundwire", ctrl);
1387     if (ret) {
1388         dev_err(dev, "Failed to request soundwire irq\n");
1389         goto err_clk;
1390     }
1391 
1392     ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1393     if (ctrl->wake_irq > 0) {
1394         ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1395                         qcom_swrm_wake_irq_handler,
1396                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1397                         "swr_wake_irq", ctrl);
1398         if (ret) {
1399             dev_err(dev, "Failed to request soundwire wake irq\n");
1400             goto err_init;
1401         }
1402     }
1403 
1404     ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1405     if (ret) {
1406         dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1407             ret);
1408         goto err_clk;
1409     }
1410 
1411     qcom_swrm_init(ctrl);
1412     wait_for_completion_timeout(&ctrl->enumeration,
1413                     msecs_to_jiffies(TIMEOUT_MS));
1414     ret = qcom_swrm_register_dais(ctrl);
1415     if (ret)
1416         goto err_master_add;
1417 
1418     dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
1419          (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1420          ctrl->version & 0xffff);
1421 
1422     pm_runtime_set_autosuspend_delay(dev, 3000);
1423     pm_runtime_use_autosuspend(dev);
1424     pm_runtime_mark_last_busy(dev);
1425     pm_runtime_set_active(dev);
1426     pm_runtime_enable(dev);
1427 
1428     /* Clk stop is not supported on WSA Soundwire masters */
1429     if (ctrl->version <= 0x01030000) {
1430         ctrl->clock_stop_not_supported = true;
1431     } else {
1432         ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1433         if (val == MASTER_ID_WSA)
1434             ctrl->clock_stop_not_supported = true;
1435     }
1436 
1437 #ifdef CONFIG_DEBUG_FS
1438     ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1439     debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1440                 &swrm_reg_fops);
1441 #endif
1442 
1443     return 0;
1444 
1445 err_master_add:
1446     sdw_bus_master_delete(&ctrl->bus);
1447 err_clk:
1448     clk_disable_unprepare(ctrl->hclk);
1449 err_init:
1450     return ret;
1451 }
1452 
1453 static int qcom_swrm_remove(struct platform_device *pdev)
1454 {
1455     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1456 
1457     sdw_bus_master_delete(&ctrl->bus);
1458     clk_disable_unprepare(ctrl->hclk);
1459 
1460     return 0;
1461 }
1462 
1463 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *swrm)
1464 {
1465     int retry = SWRM_LINK_STATUS_RETRY_CNT;
1466     int comp_sts;
1467 
1468     do {
1469         swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1470 
1471         if (comp_sts & SWRM_FRM_GEN_ENABLED)
1472             return true;
1473 
1474         usleep_range(500, 510);
1475     } while (retry--);
1476 
1477     dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1478         comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
1479 
1480     return false;
1481 }
1482 
1483 static int __maybe_unused swrm_runtime_resume(struct device *dev)
1484 {
1485     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1486     int ret;
1487 
1488     if (ctrl->wake_irq > 0) {
1489         if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1490             disable_irq_nosync(ctrl->wake_irq);
1491     }
1492 
1493     clk_prepare_enable(ctrl->hclk);
1494 
1495     if (ctrl->clock_stop_not_supported) {
1496         reinit_completion(&ctrl->enumeration);
1497         ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1498         usleep_range(100, 105);
1499 
1500         qcom_swrm_init(ctrl);
1501 
1502         usleep_range(100, 105);
1503         if (!swrm_wait_for_frame_gen_enabled(ctrl))
1504             dev_err(ctrl->dev, "link failed to connect\n");
1505 
1506         /* wait for hw enumeration to complete */
1507         wait_for_completion_timeout(&ctrl->enumeration,
1508                         msecs_to_jiffies(TIMEOUT_MS));
1509         qcom_swrm_get_device_status(ctrl);
1510         sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1511     } else {
1512         reset_control_reset(ctrl->audio_cgcr);
1513 
1514         ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1515         ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1516             SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1517 
1518         ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1519         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1520         ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1521 
1522         usleep_range(100, 105);
1523         if (!swrm_wait_for_frame_gen_enabled(ctrl))
1524             dev_err(ctrl->dev, "link failed to connect\n");
1525 
1526         ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1527         if (ret < 0)
1528             dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1529     }
1530 
1531     return 0;
1532 }
1533 
1534 static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1535 {
1536     struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1537     int ret;
1538 
1539     if (!ctrl->clock_stop_not_supported) {
1540         /* Mask bus clash interrupt */
1541         ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1542         ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1543         ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1544         /* Prepare slaves for clock stop */
1545         ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1546         if (ret < 0 && ret != -ENODATA) {
1547             dev_err(dev, "prepare clock stop failed %d", ret);
1548             return ret;
1549         }
1550 
1551         ret = sdw_bus_clk_stop(&ctrl->bus);
1552         if (ret < 0 && ret != -ENODATA) {
1553             dev_err(dev, "bus clock stop failed %d", ret);
1554             return ret;
1555         }
1556     }
1557 
1558     clk_disable_unprepare(ctrl->hclk);
1559 
1560     usleep_range(300, 305);
1561 
1562     if (ctrl->wake_irq > 0) {
1563         if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1564             enable_irq(ctrl->wake_irq);
1565     }
1566 
1567     return 0;
1568 }
1569 
1570 static const struct dev_pm_ops swrm_dev_pm_ops = {
1571     SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1572 };
1573 
1574 static const struct of_device_id qcom_swrm_of_match[] = {
1575     { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1576     { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1577     { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1578     {/* sentinel */},
1579 };
1580 
1581 MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1582 
1583 static struct platform_driver qcom_swrm_driver = {
1584     .probe  = &qcom_swrm_probe,
1585     .remove = &qcom_swrm_remove,
1586     .driver = {
1587         .name   = "qcom-soundwire",
1588         .of_match_table = qcom_swrm_of_match,
1589         .pm = &swrm_dev_pm_ops,
1590     }
1591 };
1592 module_platform_driver(qcom_swrm_driver);
1593 
1594 MODULE_DESCRIPTION("Qualcomm soundwire driver");
1595 MODULE_LICENSE("GPL v2");
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