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0001 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
0002 // Copyright(c) 2015-17 Intel Corporation.
0003 
0004 /*
0005  * Soundwire Intel Master Driver
0006  */
0007 
0008 #include <linux/acpi.h>
0009 #include <linux/debugfs.h>
0010 #include <linux/delay.h>
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/auxiliary_bus.h>
0015 #include <sound/pcm_params.h>
0016 #include <linux/pm_runtime.h>
0017 #include <sound/soc.h>
0018 #include <linux/soundwire/sdw_registers.h>
0019 #include <linux/soundwire/sdw.h>
0020 #include <linux/soundwire/sdw_intel.h>
0021 #include "cadence_master.h"
0022 #include "bus.h"
0023 #include "intel.h"
0024 
0025 #define INTEL_MASTER_SUSPEND_DELAY_MS   3000
0026 #define INTEL_MASTER_RESET_ITERATIONS   10
0027 
0028 /*
0029  * debug/config flags for the Intel SoundWire Master.
0030  *
0031  * Since we may have multiple masters active, we can have up to 8
0032  * flags reused in each byte, with master0 using the ls-byte, etc.
0033  */
0034 
0035 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME     BIT(0)
0036 #define SDW_INTEL_MASTER_DISABLE_CLOCK_STOP     BIT(1)
0037 #define SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE    BIT(2)
0038 #define SDW_INTEL_MASTER_DISABLE_MULTI_LINK     BIT(3)
0039 
0040 static int md_flags;
0041 module_param_named(sdw_md_flags, md_flags, int, 0444);
0042 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
0043 
0044 enum intel_pdi_type {
0045     INTEL_PDI_IN = 0,
0046     INTEL_PDI_OUT = 1,
0047     INTEL_PDI_BD = 2,
0048 };
0049 
0050 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
0051 
0052 /*
0053  * Read, write helpers for HW registers
0054  */
0055 static inline int intel_readl(void __iomem *base, int offset)
0056 {
0057     return readl(base + offset);
0058 }
0059 
0060 static inline void intel_writel(void __iomem *base, int offset, int value)
0061 {
0062     writel(value, base + offset);
0063 }
0064 
0065 static inline u16 intel_readw(void __iomem *base, int offset)
0066 {
0067     return readw(base + offset);
0068 }
0069 
0070 static inline void intel_writew(void __iomem *base, int offset, u16 value)
0071 {
0072     writew(value, base + offset);
0073 }
0074 
0075 static int intel_wait_bit(void __iomem *base, int offset, u32 mask, u32 target)
0076 {
0077     int timeout = 10;
0078     u32 reg_read;
0079 
0080     do {
0081         reg_read = readl(base + offset);
0082         if ((reg_read & mask) == target)
0083             return 0;
0084 
0085         timeout--;
0086         usleep_range(50, 100);
0087     } while (timeout != 0);
0088 
0089     return -EAGAIN;
0090 }
0091 
0092 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
0093 {
0094     writel(value, base + offset);
0095     return intel_wait_bit(base, offset, mask, 0);
0096 }
0097 
0098 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
0099 {
0100     writel(value, base + offset);
0101     return intel_wait_bit(base, offset, mask, mask);
0102 }
0103 
0104 /*
0105  * debugfs
0106  */
0107 #ifdef CONFIG_DEBUG_FS
0108 
0109 #define RD_BUF (2 * PAGE_SIZE)
0110 
0111 static ssize_t intel_sprintf(void __iomem *mem, bool l,
0112                  char *buf, size_t pos, unsigned int reg)
0113 {
0114     int value;
0115 
0116     if (l)
0117         value = intel_readl(mem, reg);
0118     else
0119         value = intel_readw(mem, reg);
0120 
0121     return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
0122 }
0123 
0124 static int intel_reg_show(struct seq_file *s_file, void *data)
0125 {
0126     struct sdw_intel *sdw = s_file->private;
0127     void __iomem *s = sdw->link_res->shim;
0128     void __iomem *a = sdw->link_res->alh;
0129     char *buf;
0130     ssize_t ret;
0131     int i, j;
0132     unsigned int links, reg;
0133 
0134     buf = kzalloc(RD_BUF, GFP_KERNEL);
0135     if (!buf)
0136         return -ENOMEM;
0137 
0138     links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
0139 
0140     ret = scnprintf(buf, RD_BUF, "Register  Value\n");
0141     ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
0142 
0143     for (i = 0; i < links; i++) {
0144         reg = SDW_SHIM_LCAP + i * 4;
0145         ret += intel_sprintf(s, true, buf, ret, reg);
0146     }
0147 
0148     for (i = 0; i < links; i++) {
0149         ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
0150         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
0151         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
0152         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
0153         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
0154         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
0155         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
0156 
0157         ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
0158 
0159         /*
0160          * the value 10 is the number of PDIs. We will need a
0161          * cleanup to remove hard-coded Intel configurations
0162          * from cadence_master.c
0163          */
0164         for (j = 0; j < 10; j++) {
0165             ret += intel_sprintf(s, false, buf, ret,
0166                     SDW_SHIM_PCMSYCHM(i, j));
0167             ret += intel_sprintf(s, false, buf, ret,
0168                     SDW_SHIM_PCMSYCHC(i, j));
0169         }
0170         ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
0171 
0172         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
0173         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
0174         ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
0175     }
0176 
0177     ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
0178     ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
0179     ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
0180 
0181     ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
0182     for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
0183         ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
0184 
0185     seq_printf(s_file, "%s", buf);
0186     kfree(buf);
0187 
0188     return 0;
0189 }
0190 DEFINE_SHOW_ATTRIBUTE(intel_reg);
0191 
0192 static int intel_set_m_datamode(void *data, u64 value)
0193 {
0194     struct sdw_intel *sdw = data;
0195     struct sdw_bus *bus = &sdw->cdns.bus;
0196 
0197     if (value > SDW_PORT_DATA_MODE_STATIC_1)
0198         return -EINVAL;
0199 
0200     /* Userspace changed the hardware state behind the kernel's back */
0201     add_taint(TAINT_USER, LOCKDEP_STILL_OK);
0202 
0203     bus->params.m_data_mode = value;
0204 
0205     return 0;
0206 }
0207 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_m_datamode_fops, NULL,
0208              intel_set_m_datamode, "%llu\n");
0209 
0210 static int intel_set_s_datamode(void *data, u64 value)
0211 {
0212     struct sdw_intel *sdw = data;
0213     struct sdw_bus *bus = &sdw->cdns.bus;
0214 
0215     if (value > SDW_PORT_DATA_MODE_STATIC_1)
0216         return -EINVAL;
0217 
0218     /* Userspace changed the hardware state behind the kernel's back */
0219     add_taint(TAINT_USER, LOCKDEP_STILL_OK);
0220 
0221     bus->params.s_data_mode = value;
0222 
0223     return 0;
0224 }
0225 DEFINE_DEBUGFS_ATTRIBUTE(intel_set_s_datamode_fops, NULL,
0226              intel_set_s_datamode, "%llu\n");
0227 
0228 static void intel_debugfs_init(struct sdw_intel *sdw)
0229 {
0230     struct dentry *root = sdw->cdns.bus.debugfs;
0231 
0232     if (!root)
0233         return;
0234 
0235     sdw->debugfs = debugfs_create_dir("intel-sdw", root);
0236 
0237     debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
0238                 &intel_reg_fops);
0239 
0240     debugfs_create_file("intel-m-datamode", 0200, sdw->debugfs, sdw,
0241                 &intel_set_m_datamode_fops);
0242 
0243     debugfs_create_file("intel-s-datamode", 0200, sdw->debugfs, sdw,
0244                 &intel_set_s_datamode_fops);
0245 
0246     sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
0247 }
0248 
0249 static void intel_debugfs_exit(struct sdw_intel *sdw)
0250 {
0251     debugfs_remove_recursive(sdw->debugfs);
0252 }
0253 #else
0254 static void intel_debugfs_init(struct sdw_intel *sdw) {}
0255 static void intel_debugfs_exit(struct sdw_intel *sdw) {}
0256 #endif /* CONFIG_DEBUG_FS */
0257 
0258 /*
0259  * shim ops
0260  */
0261 
0262 static int intel_link_power_up(struct sdw_intel *sdw)
0263 {
0264     unsigned int link_id = sdw->instance;
0265     void __iomem *shim = sdw->link_res->shim;
0266     u32 *shim_mask = sdw->link_res->shim_mask;
0267     struct sdw_bus *bus = &sdw->cdns.bus;
0268     struct sdw_master_prop *prop = &bus->prop;
0269     u32 spa_mask, cpa_mask;
0270     u32 link_control;
0271     int ret = 0;
0272     u32 syncprd;
0273     u32 sync_reg;
0274 
0275     mutex_lock(sdw->link_res->shim_lock);
0276 
0277     /*
0278      * The hardware relies on an internal counter, typically 4kHz,
0279      * to generate the SoundWire SSP - which defines a 'safe'
0280      * synchronization point between commands and audio transport
0281      * and allows for multi link synchronization. The SYNCPRD value
0282      * is only dependent on the oscillator clock provided to
0283      * the IP, so adjust based on _DSD properties reported in DSDT
0284      * tables. The values reported are based on either 24MHz
0285      * (CNL/CML) or 38.4 MHz (ICL/TGL+).
0286      */
0287     if (prop->mclk_freq % 6000000)
0288         syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;
0289     else
0290         syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;
0291 
0292     if (!*shim_mask) {
0293         dev_dbg(sdw->cdns.dev, "%s: powering up all links\n", __func__);
0294 
0295         /* we first need to program the SyncPRD/CPU registers */
0296         dev_dbg(sdw->cdns.dev,
0297             "%s: first link up, programming SYNCPRD\n", __func__);
0298 
0299         /* set SyncPRD period */
0300         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
0301         u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);
0302 
0303         /* Set SyncCPU bit */
0304         sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
0305         intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
0306 
0307         /* Link power up sequence */
0308         link_control = intel_readl(shim, SDW_SHIM_LCTL);
0309 
0310         /* only power-up enabled links */
0311         spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);
0312         cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
0313 
0314         link_control |=  spa_mask;
0315 
0316         ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
0317         if (ret < 0) {
0318             dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);
0319             goto out;
0320         }
0321 
0322         /* SyncCPU will change once link is active */
0323         ret = intel_wait_bit(shim, SDW_SHIM_SYNC,
0324                      SDW_SHIM_SYNC_SYNCCPU, 0);
0325         if (ret < 0) {
0326             dev_err(sdw->cdns.dev,
0327                 "Failed to set SHIM_SYNC: %d\n", ret);
0328             goto out;
0329         }
0330     }
0331 
0332     *shim_mask |= BIT(link_id);
0333 
0334     sdw->cdns.link_up = true;
0335 out:
0336     mutex_unlock(sdw->link_res->shim_lock);
0337 
0338     return ret;
0339 }
0340 
0341 /* this needs to be called with shim_lock */
0342 static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)
0343 {
0344     void __iomem *shim = sdw->link_res->shim;
0345     unsigned int link_id = sdw->instance;
0346     u16 ioctl;
0347 
0348     /* Switch to MIP from Glue logic */
0349     ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));
0350 
0351     ioctl &= ~(SDW_SHIM_IOCTL_DOE);
0352     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0353     usleep_range(10, 15);
0354 
0355     ioctl &= ~(SDW_SHIM_IOCTL_DO);
0356     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0357     usleep_range(10, 15);
0358 
0359     ioctl |= (SDW_SHIM_IOCTL_MIF);
0360     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0361     usleep_range(10, 15);
0362 
0363     ioctl &= ~(SDW_SHIM_IOCTL_BKE);
0364     ioctl &= ~(SDW_SHIM_IOCTL_COE);
0365     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0366     usleep_range(10, 15);
0367 
0368     /* at this point Master IP has full control of the I/Os */
0369 }
0370 
0371 /* this needs to be called with shim_lock */
0372 static void intel_shim_master_ip_to_glue(struct sdw_intel *sdw)
0373 {
0374     unsigned int link_id = sdw->instance;
0375     void __iomem *shim = sdw->link_res->shim;
0376     u16 ioctl;
0377 
0378     /* Glue logic */
0379     ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
0380     ioctl |= SDW_SHIM_IOCTL_BKE;
0381     ioctl |= SDW_SHIM_IOCTL_COE;
0382     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0383     usleep_range(10, 15);
0384 
0385     ioctl &= ~(SDW_SHIM_IOCTL_MIF);
0386     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0387     usleep_range(10, 15);
0388 
0389     /* at this point Integration Glue has full control of the I/Os */
0390 }
0391 
0392 static int intel_shim_init(struct sdw_intel *sdw, bool clock_stop)
0393 {
0394     void __iomem *shim = sdw->link_res->shim;
0395     unsigned int link_id = sdw->instance;
0396     int ret = 0;
0397     u16 ioctl = 0, act = 0;
0398 
0399     mutex_lock(sdw->link_res->shim_lock);
0400 
0401     /* Initialize Shim */
0402     ioctl |= SDW_SHIM_IOCTL_BKE;
0403     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0404     usleep_range(10, 15);
0405 
0406     ioctl |= SDW_SHIM_IOCTL_WPDD;
0407     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0408     usleep_range(10, 15);
0409 
0410     ioctl |= SDW_SHIM_IOCTL_DO;
0411     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0412     usleep_range(10, 15);
0413 
0414     ioctl |= SDW_SHIM_IOCTL_DOE;
0415     intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
0416     usleep_range(10, 15);
0417 
0418     intel_shim_glue_to_master_ip(sdw);
0419 
0420     u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS);
0421     act |= SDW_SHIM_CTMCTL_DACTQE;
0422     act |= SDW_SHIM_CTMCTL_DODS;
0423     intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
0424     usleep_range(10, 15);
0425 
0426     mutex_unlock(sdw->link_res->shim_lock);
0427 
0428     return ret;
0429 }
0430 
0431 static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
0432 {
0433     void __iomem *shim = sdw->link_res->shim;
0434     unsigned int link_id = sdw->instance;
0435     u16 wake_en, wake_sts;
0436 
0437     mutex_lock(sdw->link_res->shim_lock);
0438     wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);
0439 
0440     if (wake_enable) {
0441         /* Enable the wakeup */
0442         wake_en |= (SDW_SHIM_WAKEEN_ENABLE << link_id);
0443         intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
0444     } else {
0445         /* Disable the wake up interrupt */
0446         wake_en &= ~(SDW_SHIM_WAKEEN_ENABLE << link_id);
0447         intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);
0448 
0449         /* Clear wake status */
0450         wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
0451         wake_sts |= (SDW_SHIM_WAKESTS_STATUS << link_id);
0452         intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);
0453     }
0454     mutex_unlock(sdw->link_res->shim_lock);
0455 }
0456 
0457 static int intel_link_power_down(struct sdw_intel *sdw)
0458 {
0459     u32 link_control, spa_mask, cpa_mask;
0460     unsigned int link_id = sdw->instance;
0461     void __iomem *shim = sdw->link_res->shim;
0462     u32 *shim_mask = sdw->link_res->shim_mask;
0463     int ret = 0;
0464 
0465     mutex_lock(sdw->link_res->shim_lock);
0466 
0467     if (!(*shim_mask & BIT(link_id)))
0468         dev_err(sdw->cdns.dev,
0469             "%s: Unbalanced power-up/down calls\n", __func__);
0470 
0471     sdw->cdns.link_up = false;
0472 
0473     intel_shim_master_ip_to_glue(sdw);
0474 
0475     *shim_mask &= ~BIT(link_id);
0476 
0477     if (!*shim_mask) {
0478 
0479         dev_dbg(sdw->cdns.dev, "%s: powering down all links\n", __func__);
0480 
0481         /* Link power down sequence */
0482         link_control = intel_readl(shim, SDW_SHIM_LCTL);
0483 
0484         /* only power-down enabled links */
0485         spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, ~sdw->link_res->link_mask);
0486         cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);
0487 
0488         link_control &=  spa_mask;
0489 
0490         ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
0491         if (ret < 0) {
0492             dev_err(sdw->cdns.dev, "%s: could not power down link\n", __func__);
0493 
0494             /*
0495              * we leave the sdw->cdns.link_up flag as false since we've disabled
0496              * the link at this point and cannot handle interrupts any longer.
0497              */
0498         }
0499     }
0500 
0501     mutex_unlock(sdw->link_res->shim_lock);
0502 
0503     return ret;
0504 }
0505 
0506 static void intel_shim_sync_arm(struct sdw_intel *sdw)
0507 {
0508     void __iomem *shim = sdw->link_res->shim;
0509     u32 sync_reg;
0510 
0511     mutex_lock(sdw->link_res->shim_lock);
0512 
0513     /* update SYNC register */
0514     sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
0515     sync_reg |= (SDW_SHIM_SYNC_CMDSYNC << sdw->instance);
0516     intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
0517 
0518     mutex_unlock(sdw->link_res->shim_lock);
0519 }
0520 
0521 static int intel_shim_sync_go_unlocked(struct sdw_intel *sdw)
0522 {
0523     void __iomem *shim = sdw->link_res->shim;
0524     u32 sync_reg;
0525     int ret;
0526 
0527     /* Read SYNC register */
0528     sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
0529 
0530     /*
0531      * Set SyncGO bit to synchronously trigger a bank switch for
0532      * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
0533      * the Masters.
0534      */
0535     sync_reg |= SDW_SHIM_SYNC_SYNCGO;
0536 
0537     ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
0538                   SDW_SHIM_SYNC_SYNCGO);
0539 
0540     if (ret < 0)
0541         dev_err(sdw->cdns.dev, "SyncGO clear failed: %d\n", ret);
0542 
0543     return ret;
0544 }
0545 
0546 static int intel_shim_sync_go(struct sdw_intel *sdw)
0547 {
0548     int ret;
0549 
0550     mutex_lock(sdw->link_res->shim_lock);
0551 
0552     ret = intel_shim_sync_go_unlocked(sdw);
0553 
0554     mutex_unlock(sdw->link_res->shim_lock);
0555 
0556     return ret;
0557 }
0558 
0559 /*
0560  * PDI routines
0561  */
0562 static void intel_pdi_init(struct sdw_intel *sdw,
0563                struct sdw_cdns_stream_config *config)
0564 {
0565     void __iomem *shim = sdw->link_res->shim;
0566     unsigned int link_id = sdw->instance;
0567     int pcm_cap;
0568 
0569     /* PCM Stream Capability */
0570     pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
0571 
0572     config->pcm_bd = FIELD_GET(SDW_SHIM_PCMSCAP_BSS, pcm_cap);
0573     config->pcm_in = FIELD_GET(SDW_SHIM_PCMSCAP_ISS, pcm_cap);
0574     config->pcm_out = FIELD_GET(SDW_SHIM_PCMSCAP_OSS, pcm_cap);
0575 
0576     dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
0577         config->pcm_bd, config->pcm_in, config->pcm_out);
0578 }
0579 
0580 static int
0581 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num)
0582 {
0583     void __iomem *shim = sdw->link_res->shim;
0584     unsigned int link_id = sdw->instance;
0585     int count;
0586 
0587     count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
0588 
0589     /*
0590      * WORKAROUND: on all existing Intel controllers, pdi
0591      * number 2 reports channel count as 1 even though it
0592      * supports 8 channels. Performing hardcoding for pdi
0593      * number 2.
0594      */
0595     if (pdi_num == 2)
0596         count = 7;
0597 
0598     /* zero based values for channel count in register */
0599     count++;
0600 
0601     return count;
0602 }
0603 
0604 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
0605                    struct sdw_cdns_pdi *pdi,
0606                    unsigned int num_pdi,
0607                    unsigned int *num_ch)
0608 {
0609     int i, ch_count = 0;
0610 
0611     for (i = 0; i < num_pdi; i++) {
0612         pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num);
0613         ch_count += pdi->ch_count;
0614         pdi++;
0615     }
0616 
0617     *num_ch = ch_count;
0618     return 0;
0619 }
0620 
0621 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
0622                       struct sdw_cdns_streams *stream)
0623 {
0624     intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
0625                 &stream->num_ch_bd);
0626 
0627     intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
0628                 &stream->num_ch_in);
0629 
0630     intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
0631                 &stream->num_ch_out);
0632 
0633     return 0;
0634 }
0635 
0636 static int intel_pdi_ch_update(struct sdw_intel *sdw)
0637 {
0638     intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm);
0639 
0640     return 0;
0641 }
0642 
0643 static void
0644 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
0645 {
0646     void __iomem *shim = sdw->link_res->shim;
0647     unsigned int link_id = sdw->instance;
0648     int pdi_conf = 0;
0649 
0650     /* the Bulk and PCM streams are not contiguous */
0651     pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
0652     if (pdi->num >= 2)
0653         pdi->intel_alh_id += 2;
0654 
0655     /*
0656      * Program stream parameters to stream SHIM register
0657      * This is applicable for PCM stream only.
0658      */
0659     if (pdi->type != SDW_STREAM_PCM)
0660         return;
0661 
0662     if (pdi->dir == SDW_DATA_DIR_RX)
0663         pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
0664     else
0665         pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
0666 
0667     u32p_replace_bits(&pdi_conf, pdi->intel_alh_id, SDW_SHIM_PCMSYCM_STREAM);
0668     u32p_replace_bits(&pdi_conf, pdi->l_ch_num, SDW_SHIM_PCMSYCM_LCHN);
0669     u32p_replace_bits(&pdi_conf, pdi->h_ch_num, SDW_SHIM_PCMSYCM_HCHN);
0670 
0671     intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
0672 }
0673 
0674 static void
0675 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
0676 {
0677     void __iomem *alh = sdw->link_res->alh;
0678     unsigned int link_id = sdw->instance;
0679     unsigned int conf;
0680 
0681     /* the Bulk and PCM streams are not contiguous */
0682     pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
0683     if (pdi->num >= 2)
0684         pdi->intel_alh_id += 2;
0685 
0686     /* Program Stream config ALH register */
0687     conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
0688 
0689     u32p_replace_bits(&conf, SDW_ALH_STRMZCFG_DMAT_VAL, SDW_ALH_STRMZCFG_DMAT);
0690     u32p_replace_bits(&conf, pdi->ch_count - 1, SDW_ALH_STRMZCFG_CHN);
0691 
0692     intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
0693 }
0694 
0695 static int intel_params_stream(struct sdw_intel *sdw,
0696                    int stream,
0697                    struct snd_soc_dai *dai,
0698                    struct snd_pcm_hw_params *hw_params,
0699                    int link_id, int alh_stream_id)
0700 {
0701     struct sdw_intel_link_res *res = sdw->link_res;
0702     struct sdw_intel_stream_params_data params_data;
0703 
0704     params_data.stream = stream; /* direction */
0705     params_data.dai = dai;
0706     params_data.hw_params = hw_params;
0707     params_data.link_id = link_id;
0708     params_data.alh_stream_id = alh_stream_id;
0709 
0710     if (res->ops && res->ops->params_stream && res->dev)
0711         return res->ops->params_stream(res->dev,
0712                            &params_data);
0713     return -EIO;
0714 }
0715 
0716 static int intel_free_stream(struct sdw_intel *sdw,
0717                  int stream,
0718                  struct snd_soc_dai *dai,
0719                  int link_id)
0720 {
0721     struct sdw_intel_link_res *res = sdw->link_res;
0722     struct sdw_intel_stream_free_data free_data;
0723 
0724     free_data.stream = stream; /* direction */
0725     free_data.dai = dai;
0726     free_data.link_id = link_id;
0727 
0728     if (res->ops && res->ops->free_stream && res->dev)
0729         return res->ops->free_stream(res->dev,
0730                          &free_data);
0731 
0732     return 0;
0733 }
0734 
0735 /*
0736  * bank switch routines
0737  */
0738 
0739 static int intel_pre_bank_switch(struct sdw_bus *bus)
0740 {
0741     struct sdw_cdns *cdns = bus_to_cdns(bus);
0742     struct sdw_intel *sdw = cdns_to_intel(cdns);
0743 
0744     /* Write to register only for multi-link */
0745     if (!bus->multi_link)
0746         return 0;
0747 
0748     intel_shim_sync_arm(sdw);
0749 
0750     return 0;
0751 }
0752 
0753 static int intel_post_bank_switch(struct sdw_bus *bus)
0754 {
0755     struct sdw_cdns *cdns = bus_to_cdns(bus);
0756     struct sdw_intel *sdw = cdns_to_intel(cdns);
0757     void __iomem *shim = sdw->link_res->shim;
0758     int sync_reg, ret;
0759 
0760     /* Write to register only for multi-link */
0761     if (!bus->multi_link)
0762         return 0;
0763 
0764     mutex_lock(sdw->link_res->shim_lock);
0765 
0766     /* Read SYNC register */
0767     sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
0768 
0769     /*
0770      * post_bank_switch() ops is called from the bus in loop for
0771      * all the Masters in the steam with the expectation that
0772      * we trigger the bankswitch for the only first Master in the list
0773      * and do nothing for the other Masters
0774      *
0775      * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
0776      */
0777     if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK)) {
0778         ret = 0;
0779         goto unlock;
0780     }
0781 
0782     ret = intel_shim_sync_go_unlocked(sdw);
0783 unlock:
0784     mutex_unlock(sdw->link_res->shim_lock);
0785 
0786     if (ret < 0)
0787         dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
0788 
0789     return ret;
0790 }
0791 
0792 /*
0793  * DAI routines
0794  */
0795 
0796 static int intel_startup(struct snd_pcm_substream *substream,
0797              struct snd_soc_dai *dai)
0798 {
0799     struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
0800     int ret;
0801 
0802     ret = pm_runtime_resume_and_get(cdns->dev);
0803     if (ret < 0 && ret != -EACCES) {
0804         dev_err_ratelimited(cdns->dev,
0805                     "pm_runtime_resume_and_get failed in %s, ret %d\n",
0806                     __func__, ret);
0807         return ret;
0808     }
0809     return 0;
0810 }
0811 
0812 static int intel_hw_params(struct snd_pcm_substream *substream,
0813                struct snd_pcm_hw_params *params,
0814                struct snd_soc_dai *dai)
0815 {
0816     struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
0817     struct sdw_intel *sdw = cdns_to_intel(cdns);
0818     struct sdw_cdns_dma_data *dma;
0819     struct sdw_cdns_pdi *pdi;
0820     struct sdw_stream_config sconfig;
0821     struct sdw_port_config *pconfig;
0822     int ch, dir;
0823     int ret;
0824 
0825     dma = snd_soc_dai_get_dma_data(dai, substream);
0826     if (!dma)
0827         return -EIO;
0828 
0829     ch = params_channels(params);
0830     if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0831         dir = SDW_DATA_DIR_RX;
0832     else
0833         dir = SDW_DATA_DIR_TX;
0834 
0835     pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
0836 
0837     if (!pdi) {
0838         ret = -EINVAL;
0839         goto error;
0840     }
0841 
0842     /* do run-time configurations for SHIM, ALH and PDI/PORT */
0843     intel_pdi_shim_configure(sdw, pdi);
0844     intel_pdi_alh_configure(sdw, pdi);
0845     sdw_cdns_config_stream(cdns, ch, dir, pdi);
0846 
0847     /* store pdi and hw_params, may be needed in prepare step */
0848     dma->paused = false;
0849     dma->suspended = false;
0850     dma->pdi = pdi;
0851     dma->hw_params = params;
0852 
0853     /* Inform DSP about PDI stream number */
0854     ret = intel_params_stream(sdw, substream->stream, dai, params,
0855                   sdw->instance,
0856                   pdi->intel_alh_id);
0857     if (ret)
0858         goto error;
0859 
0860     sconfig.direction = dir;
0861     sconfig.ch_count = ch;
0862     sconfig.frame_rate = params_rate(params);
0863     sconfig.type = dma->stream_type;
0864 
0865     sconfig.bps = snd_pcm_format_width(params_format(params));
0866 
0867     /* Port configuration */
0868     pconfig = kzalloc(sizeof(*pconfig), GFP_KERNEL);
0869     if (!pconfig) {
0870         ret =  -ENOMEM;
0871         goto error;
0872     }
0873 
0874     pconfig->num = pdi->num;
0875     pconfig->ch_mask = (1 << ch) - 1;
0876 
0877     ret = sdw_stream_add_master(&cdns->bus, &sconfig,
0878                     pconfig, 1, dma->stream);
0879     if (ret)
0880         dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
0881 
0882     kfree(pconfig);
0883 error:
0884     return ret;
0885 }
0886 
0887 static int intel_prepare(struct snd_pcm_substream *substream,
0888              struct snd_soc_dai *dai)
0889 {
0890     struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
0891     struct sdw_intel *sdw = cdns_to_intel(cdns);
0892     struct sdw_cdns_dma_data *dma;
0893     int ch, dir;
0894     int ret = 0;
0895 
0896     dma = snd_soc_dai_get_dma_data(dai, substream);
0897     if (!dma) {
0898         dev_err(dai->dev, "failed to get dma data in %s\n",
0899             __func__);
0900         return -EIO;
0901     }
0902 
0903     if (dma->suspended) {
0904         dma->suspended = false;
0905 
0906         /*
0907          * .prepare() is called after system resume, where we
0908          * need to reinitialize the SHIM/ALH/Cadence IP.
0909          * .prepare() is also called to deal with underflows,
0910          * but in those cases we cannot touch ALH/SHIM
0911          * registers
0912          */
0913 
0914         /* configure stream */
0915         ch = params_channels(dma->hw_params);
0916         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
0917             dir = SDW_DATA_DIR_RX;
0918         else
0919             dir = SDW_DATA_DIR_TX;
0920 
0921         intel_pdi_shim_configure(sdw, dma->pdi);
0922         intel_pdi_alh_configure(sdw, dma->pdi);
0923         sdw_cdns_config_stream(cdns, ch, dir, dma->pdi);
0924 
0925         /* Inform DSP about PDI stream number */
0926         ret = intel_params_stream(sdw, substream->stream, dai,
0927                       dma->hw_params,
0928                       sdw->instance,
0929                       dma->pdi->intel_alh_id);
0930     }
0931 
0932     return ret;
0933 }
0934 
0935 static int
0936 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
0937 {
0938     struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
0939     struct sdw_intel *sdw = cdns_to_intel(cdns);
0940     struct sdw_cdns_dma_data *dma;
0941     int ret;
0942 
0943     dma = snd_soc_dai_get_dma_data(dai, substream);
0944     if (!dma)
0945         return -EIO;
0946 
0947     /*
0948      * The sdw stream state will transition to RELEASED when stream->
0949      * master_list is empty. So the stream state will transition to
0950      * DEPREPARED for the first cpu-dai and to RELEASED for the last
0951      * cpu-dai.
0952      */
0953     ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
0954     if (ret < 0) {
0955         dev_err(dai->dev, "remove master from stream %s failed: %d\n",
0956             dma->stream->name, ret);
0957         return ret;
0958     }
0959 
0960     ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
0961     if (ret < 0) {
0962         dev_err(dai->dev, "intel_free_stream: failed %d\n", ret);
0963         return ret;
0964     }
0965 
0966     dma->hw_params = NULL;
0967     dma->pdi = NULL;
0968 
0969     return 0;
0970 }
0971 
0972 static void intel_shutdown(struct snd_pcm_substream *substream,
0973                struct snd_soc_dai *dai)
0974 {
0975     struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
0976 
0977     pm_runtime_mark_last_busy(cdns->dev);
0978     pm_runtime_put_autosuspend(cdns->dev);
0979 }
0980 
0981 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
0982                     void *stream, int direction)
0983 {
0984     return cdns_set_sdw_stream(dai, stream, direction);
0985 }
0986 
0987 static void *intel_get_sdw_stream(struct snd_soc_dai *dai,
0988                   int direction)
0989 {
0990     struct sdw_cdns_dma_data *dma;
0991 
0992     if (direction == SNDRV_PCM_STREAM_PLAYBACK)
0993         dma = dai->playback_dma_data;
0994     else
0995         dma = dai->capture_dma_data;
0996 
0997     if (!dma)
0998         return ERR_PTR(-EINVAL);
0999 
1000     return dma->stream;
1001 }
1002 
1003 static int intel_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
1004 {
1005     struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1006     struct sdw_intel *sdw = cdns_to_intel(cdns);
1007     struct sdw_intel_link_res *res = sdw->link_res;
1008     struct sdw_cdns_dma_data *dma;
1009     int ret = 0;
1010 
1011     /*
1012      * The .trigger callback is used to send required IPC to audio
1013      * firmware. The .free_stream callback will still be called
1014      * by intel_free_stream() in the TRIGGER_SUSPEND case.
1015      */
1016     if (res->ops && res->ops->trigger)
1017         res->ops->trigger(dai, cmd, substream->stream);
1018 
1019     dma = snd_soc_dai_get_dma_data(dai, substream);
1020     if (!dma) {
1021         dev_err(dai->dev, "failed to get dma data in %s\n",
1022             __func__);
1023         return -EIO;
1024     }
1025 
1026     switch (cmd) {
1027     case SNDRV_PCM_TRIGGER_SUSPEND:
1028 
1029         /*
1030          * The .prepare callback is used to deal with xruns and resume operations.
1031          * In the case of xruns, the DMAs and SHIM registers cannot be touched,
1032          * but for resume operations the DMAs and SHIM registers need to be initialized.
1033          * the .trigger callback is used to track the suspend case only.
1034          */
1035 
1036         dma->suspended = true;
1037 
1038         ret = intel_free_stream(sdw, substream->stream, dai, sdw->instance);
1039         break;
1040 
1041     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1042         dma->paused = true;
1043         break;
1044     case SNDRV_PCM_TRIGGER_STOP:
1045     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1046         dma->paused = false;
1047         break;
1048     default:
1049         break;
1050     }
1051 
1052     return ret;
1053 }
1054 
1055 static int intel_component_probe(struct snd_soc_component *component)
1056 {
1057     int ret;
1058 
1059     /*
1060      * make sure the device is pm_runtime_active before initiating
1061      * bus transactions during the card registration.
1062      * We use pm_runtime_resume() here, without taking a reference
1063      * and releasing it immediately.
1064      */
1065     ret = pm_runtime_resume(component->dev);
1066     if (ret < 0 && ret != -EACCES)
1067         return ret;
1068 
1069     return 0;
1070 }
1071 
1072 static int intel_component_dais_suspend(struct snd_soc_component *component)
1073 {
1074     struct snd_soc_dai *dai;
1075 
1076     /*
1077      * In the corner case where a SUSPEND happens during a PAUSE, the ALSA core
1078      * does not throw the TRIGGER_SUSPEND. This leaves the DAIs in an unbalanced state.
1079      * Since the component suspend is called last, we can trap this corner case
1080      * and force the DAIs to release their resources.
1081      */
1082     for_each_component_dais(component, dai) {
1083         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
1084         struct sdw_intel *sdw = cdns_to_intel(cdns);
1085         struct sdw_cdns_dma_data *dma;
1086         int stream;
1087         int ret;
1088 
1089         dma = dai->playback_dma_data;
1090         stream = SNDRV_PCM_STREAM_PLAYBACK;
1091         if (!dma) {
1092             dma = dai->capture_dma_data;
1093             stream = SNDRV_PCM_STREAM_CAPTURE;
1094         }
1095 
1096         if (!dma)
1097             continue;
1098 
1099         if (dma->suspended)
1100             continue;
1101 
1102         if (dma->paused) {
1103             dma->suspended = true;
1104 
1105             ret = intel_free_stream(sdw, stream, dai, sdw->instance);
1106             if (ret < 0)
1107                 return ret;
1108         }
1109     }
1110 
1111     return 0;
1112 }
1113 
1114 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
1115     .startup = intel_startup,
1116     .hw_params = intel_hw_params,
1117     .prepare = intel_prepare,
1118     .hw_free = intel_hw_free,
1119     .trigger = intel_trigger,
1120     .shutdown = intel_shutdown,
1121     .set_stream = intel_pcm_set_sdw_stream,
1122     .get_stream = intel_get_sdw_stream,
1123 };
1124 
1125 static const struct snd_soc_component_driver dai_component = {
1126     .name           = "soundwire",
1127     .probe          = intel_component_probe,
1128     .suspend        = intel_component_dais_suspend,
1129     .legacy_dai_naming  = 1,
1130 };
1131 
1132 static int intel_create_dai(struct sdw_cdns *cdns,
1133                 struct snd_soc_dai_driver *dais,
1134                 enum intel_pdi_type type,
1135                 u32 num, u32 off, u32 max_ch)
1136 {
1137     int i;
1138 
1139     if (num == 0)
1140         return 0;
1141 
1142      /* TODO: Read supported rates/formats from hardware */
1143     for (i = off; i < (off + num); i++) {
1144         dais[i].name = devm_kasprintf(cdns->dev, GFP_KERNEL,
1145                           "SDW%d Pin%d",
1146                           cdns->instance, i);
1147         if (!dais[i].name)
1148             return -ENOMEM;
1149 
1150         if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
1151             dais[i].playback.channels_min = 1;
1152             dais[i].playback.channels_max = max_ch;
1153             dais[i].playback.rates = SNDRV_PCM_RATE_48000;
1154             dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
1155         }
1156 
1157         if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
1158             dais[i].capture.channels_min = 1;
1159             dais[i].capture.channels_max = max_ch;
1160             dais[i].capture.rates = SNDRV_PCM_RATE_48000;
1161             dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
1162         }
1163 
1164         dais[i].ops = &intel_pcm_dai_ops;
1165     }
1166 
1167     return 0;
1168 }
1169 
1170 static int intel_register_dai(struct sdw_intel *sdw)
1171 {
1172     struct sdw_cdns *cdns = &sdw->cdns;
1173     struct sdw_cdns_streams *stream;
1174     struct snd_soc_dai_driver *dais;
1175     int num_dai, ret, off = 0;
1176 
1177     /* DAIs are created based on total number of PDIs supported */
1178     num_dai = cdns->pcm.num_pdi;
1179 
1180     dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
1181     if (!dais)
1182         return -ENOMEM;
1183 
1184     /* Create PCM DAIs */
1185     stream = &cdns->pcm;
1186 
1187     ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
1188                    off, stream->num_ch_in);
1189     if (ret)
1190         return ret;
1191 
1192     off += cdns->pcm.num_in;
1193     ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
1194                    off, stream->num_ch_out);
1195     if (ret)
1196         return ret;
1197 
1198     off += cdns->pcm.num_out;
1199     ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
1200                    off, stream->num_ch_bd);
1201     if (ret)
1202         return ret;
1203 
1204     return snd_soc_register_component(cdns->dev, &dai_component,
1205                       dais, num_dai);
1206 }
1207 
1208 static int sdw_master_read_intel_prop(struct sdw_bus *bus)
1209 {
1210     struct sdw_master_prop *prop = &bus->prop;
1211     struct fwnode_handle *link;
1212     char name[32];
1213     u32 quirk_mask;
1214 
1215     /* Find master handle */
1216     snprintf(name, sizeof(name),
1217          "mipi-sdw-link-%d-subproperties", bus->link_id);
1218 
1219     link = device_get_named_child_node(bus->dev, name);
1220     if (!link) {
1221         dev_err(bus->dev, "Master node %s not found\n", name);
1222         return -EIO;
1223     }
1224 
1225     fwnode_property_read_u32(link,
1226                  "intel-sdw-ip-clock",
1227                  &prop->mclk_freq);
1228 
1229     /* the values reported by BIOS are the 2x clock, not the bus clock */
1230     prop->mclk_freq /= 2;
1231 
1232     fwnode_property_read_u32(link,
1233                  "intel-quirk-mask",
1234                  &quirk_mask);
1235 
1236     if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
1237         prop->hw_disabled = true;
1238 
1239     prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |
1240         SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;
1241 
1242     return 0;
1243 }
1244 
1245 static int intel_prop_read(struct sdw_bus *bus)
1246 {
1247     /* Initialize with default handler to read all DisCo properties */
1248     sdw_master_read_prop(bus);
1249 
1250     /* read Intel-specific properties */
1251     sdw_master_read_intel_prop(bus);
1252 
1253     return 0;
1254 }
1255 
1256 static struct sdw_master_ops sdw_intel_ops = {
1257     .read_prop = sdw_master_read_prop,
1258     .override_adr = sdw_dmi_override_adr,
1259     .xfer_msg = cdns_xfer_msg,
1260     .xfer_msg_defer = cdns_xfer_msg_defer,
1261     .reset_page_addr = cdns_reset_page_addr,
1262     .set_bus_conf = cdns_bus_conf,
1263     .pre_bank_switch = intel_pre_bank_switch,
1264     .post_bank_switch = intel_post_bank_switch,
1265 };
1266 
1267 static int intel_init(struct sdw_intel *sdw)
1268 {
1269     bool clock_stop;
1270 
1271     /* Initialize shim and controller */
1272     intel_link_power_up(sdw);
1273 
1274     clock_stop = sdw_cdns_is_clock_stop(&sdw->cdns);
1275 
1276     intel_shim_init(sdw, clock_stop);
1277 
1278     return 0;
1279 }
1280 
1281 /*
1282  * probe and init (aux_dev_id argument is required by function prototype but not used)
1283  */
1284 static int intel_link_probe(struct auxiliary_device *auxdev,
1285                 const struct auxiliary_device_id *aux_dev_id)
1286 
1287 {
1288     struct device *dev = &auxdev->dev;
1289     struct sdw_intel_link_dev *ldev = auxiliary_dev_to_sdw_intel_link_dev(auxdev);
1290     struct sdw_intel *sdw;
1291     struct sdw_cdns *cdns;
1292     struct sdw_bus *bus;
1293     int ret;
1294 
1295     sdw = devm_kzalloc(dev, sizeof(*sdw), GFP_KERNEL);
1296     if (!sdw)
1297         return -ENOMEM;
1298 
1299     cdns = &sdw->cdns;
1300     bus = &cdns->bus;
1301 
1302     sdw->instance = auxdev->id;
1303     sdw->link_res = &ldev->link_res;
1304     cdns->dev = dev;
1305     cdns->registers = sdw->link_res->registers;
1306     cdns->instance = sdw->instance;
1307     cdns->msg_count = 0;
1308 
1309     bus->link_id = auxdev->id;
1310 
1311     sdw_cdns_probe(cdns);
1312 
1313     /* Set property read ops */
1314     sdw_intel_ops.read_prop = intel_prop_read;
1315     bus->ops = &sdw_intel_ops;
1316 
1317     /* set driver data, accessed by snd_soc_dai_get_drvdata() */
1318     auxiliary_set_drvdata(auxdev, cdns);
1319 
1320     /* use generic bandwidth allocation algorithm */
1321     sdw->cdns.bus.compute_params = sdw_compute_params;
1322 
1323     /* avoid resuming from pm_runtime suspend if it's not required */
1324     dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
1325 
1326     ret = sdw_bus_master_add(bus, dev, dev->fwnode);
1327     if (ret) {
1328         dev_err(dev, "sdw_bus_master_add fail: %d\n", ret);
1329         return ret;
1330     }
1331 
1332     if (bus->prop.hw_disabled)
1333         dev_info(dev,
1334              "SoundWire master %d is disabled, will be ignored\n",
1335              bus->link_id);
1336     /*
1337      * Ignore BIOS err_threshold, it's a really bad idea when dealing
1338      * with multiple hardware synchronized links
1339      */
1340     bus->prop.err_threshold = 0;
1341 
1342     return 0;
1343 }
1344 
1345 int intel_link_startup(struct auxiliary_device *auxdev)
1346 {
1347     struct sdw_cdns_stream_config config;
1348     struct device *dev = &auxdev->dev;
1349     struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev);
1350     struct sdw_intel *sdw = cdns_to_intel(cdns);
1351     struct sdw_bus *bus = &cdns->bus;
1352     int link_flags;
1353     bool multi_link;
1354     u32 clock_stop_quirks;
1355     int ret;
1356 
1357     if (bus->prop.hw_disabled) {
1358         dev_info(dev,
1359              "SoundWire master %d is disabled, ignoring\n",
1360              sdw->instance);
1361         return 0;
1362     }
1363 
1364     link_flags = md_flags >> (bus->link_id * 8);
1365     multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1366     if (!multi_link) {
1367         dev_dbg(dev, "Multi-link is disabled\n");
1368         bus->multi_link = false;
1369     } else {
1370         /*
1371          * hardware-based synchronization is required regardless
1372          * of the number of segments used by a stream: SSP-based
1373          * synchronization is gated by gsync when the multi-master
1374          * mode is set.
1375          */
1376         bus->multi_link = true;
1377         bus->hw_sync_min_links = 1;
1378     }
1379 
1380     /* Initialize shim, controller */
1381     ret = intel_init(sdw);
1382     if (ret)
1383         goto err_init;
1384 
1385     /* Read the PDI config and initialize cadence PDI */
1386     intel_pdi_init(sdw, &config);
1387     ret = sdw_cdns_pdi_init(cdns, config);
1388     if (ret)
1389         goto err_init;
1390 
1391     intel_pdi_ch_update(sdw);
1392 
1393     ret = sdw_cdns_enable_interrupt(cdns, true);
1394     if (ret < 0) {
1395         dev_err(dev, "cannot enable interrupts\n");
1396         goto err_init;
1397     }
1398 
1399     /*
1400      * follow recommended programming flows to avoid timeouts when
1401      * gsync is enabled
1402      */
1403     if (multi_link)
1404         intel_shim_sync_arm(sdw);
1405 
1406     ret = sdw_cdns_init(cdns);
1407     if (ret < 0) {
1408         dev_err(dev, "unable to initialize Cadence IP\n");
1409         goto err_interrupt;
1410     }
1411 
1412     ret = sdw_cdns_exit_reset(cdns);
1413     if (ret < 0) {
1414         dev_err(dev, "unable to exit bus reset sequence\n");
1415         goto err_interrupt;
1416     }
1417 
1418     if (multi_link) {
1419         ret = intel_shim_sync_go(sdw);
1420         if (ret < 0) {
1421             dev_err(dev, "sync go failed: %d\n", ret);
1422             goto err_interrupt;
1423         }
1424     }
1425     sdw_cdns_check_self_clearing_bits(cdns, __func__,
1426                       true, INTEL_MASTER_RESET_ITERATIONS);
1427 
1428     /* Register DAIs */
1429     ret = intel_register_dai(sdw);
1430     if (ret) {
1431         dev_err(dev, "DAI registration failed: %d\n", ret);
1432         snd_soc_unregister_component(dev);
1433         goto err_interrupt;
1434     }
1435 
1436     intel_debugfs_init(sdw);
1437 
1438     /* Enable runtime PM */
1439     if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME)) {
1440         pm_runtime_set_autosuspend_delay(dev,
1441                          INTEL_MASTER_SUSPEND_DELAY_MS);
1442         pm_runtime_use_autosuspend(dev);
1443         pm_runtime_mark_last_busy(dev);
1444 
1445         pm_runtime_set_active(dev);
1446         pm_runtime_enable(dev);
1447     }
1448 
1449     clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1450     if (clock_stop_quirks & SDW_INTEL_CLK_STOP_NOT_ALLOWED) {
1451         /*
1452          * To keep the clock running we need to prevent
1453          * pm_runtime suspend from happening by increasing the
1454          * reference count.
1455          * This quirk is specified by the parent PCI device in
1456          * case of specific latency requirements. It will have
1457          * no effect if pm_runtime is disabled by the user via
1458          * a module parameter for testing purposes.
1459          */
1460         pm_runtime_get_noresume(dev);
1461     }
1462 
1463     /*
1464      * The runtime PM status of Slave devices is "Unsupported"
1465      * until they report as ATTACHED. If they don't, e.g. because
1466      * there are no Slave devices populated or if the power-on is
1467      * delayed or dependent on a power switch, the Master will
1468      * remain active and prevent its parent from suspending.
1469      *
1470      * Conditionally force the pm_runtime core to re-evaluate the
1471      * Master status in the absence of any Slave activity. A quirk
1472      * is provided to e.g. deal with Slaves that may be powered on
1473      * with a delay. A more complete solution would require the
1474      * definition of Master properties.
1475      */
1476     if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1477         pm_runtime_idle(dev);
1478 
1479     sdw->startup_done = true;
1480     return 0;
1481 
1482 err_interrupt:
1483     sdw_cdns_enable_interrupt(cdns, false);
1484 err_init:
1485     return ret;
1486 }
1487 
1488 static void intel_link_remove(struct auxiliary_device *auxdev)
1489 {
1490     struct device *dev = &auxdev->dev;
1491     struct sdw_cdns *cdns = auxiliary_get_drvdata(auxdev);
1492     struct sdw_intel *sdw = cdns_to_intel(cdns);
1493     struct sdw_bus *bus = &cdns->bus;
1494 
1495     /*
1496      * Since pm_runtime is already disabled, we don't decrease
1497      * the refcount when the clock_stop_quirk is
1498      * SDW_INTEL_CLK_STOP_NOT_ALLOWED
1499      */
1500     if (!bus->prop.hw_disabled) {
1501         intel_debugfs_exit(sdw);
1502         sdw_cdns_enable_interrupt(cdns, false);
1503         snd_soc_unregister_component(dev);
1504     }
1505     sdw_bus_master_delete(bus);
1506 }
1507 
1508 int intel_link_process_wakeen_event(struct auxiliary_device *auxdev)
1509 {
1510     struct device *dev = &auxdev->dev;
1511     struct sdw_intel *sdw;
1512     struct sdw_bus *bus;
1513     void __iomem *shim;
1514     u16 wake_sts;
1515 
1516     sdw = auxiliary_get_drvdata(auxdev);
1517     bus = &sdw->cdns.bus;
1518 
1519     if (bus->prop.hw_disabled || !sdw->startup_done) {
1520         dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1521             bus->link_id);
1522         return 0;
1523     }
1524 
1525     shim = sdw->link_res->shim;
1526     wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);
1527 
1528     if (!(wake_sts & BIT(sdw->instance)))
1529         return 0;
1530 
1531     /* disable WAKEEN interrupt ASAP to prevent interrupt flood */
1532     intel_shim_wake(sdw, false);
1533 
1534     /*
1535      * resume the Master, which will generate a bus reset and result in
1536      * Slaves re-attaching and be re-enumerated. The SoundWire physical
1537      * device which generated the wake will trigger an interrupt, which
1538      * will in turn cause the corresponding Linux Slave device to be
1539      * resumed and the Slave codec driver to check the status.
1540      */
1541     pm_request_resume(dev);
1542 
1543     return 0;
1544 }
1545 
1546 /*
1547  * PM calls
1548  */
1549 
1550 static int intel_resume_child_device(struct device *dev, void *data)
1551 {
1552     int ret;
1553     struct sdw_slave *slave = dev_to_sdw_dev(dev);
1554 
1555     if (!slave->probed) {
1556         dev_dbg(dev, "%s: skipping device, no probed driver\n", __func__);
1557         return 0;
1558     }
1559     if (!slave->dev_num_sticky) {
1560         dev_dbg(dev, "%s: skipping device, never detected on bus\n", __func__);
1561         return 0;
1562     }
1563 
1564     ret = pm_request_resume(dev);
1565     if (ret < 0)
1566         dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1567 
1568     return ret;
1569 }
1570 
1571 static int __maybe_unused intel_pm_prepare(struct device *dev)
1572 {
1573     struct sdw_cdns *cdns = dev_get_drvdata(dev);
1574     struct sdw_intel *sdw = cdns_to_intel(cdns);
1575     struct sdw_bus *bus = &cdns->bus;
1576     u32 clock_stop_quirks;
1577     int ret;
1578 
1579     if (bus->prop.hw_disabled || !sdw->startup_done) {
1580         dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1581             bus->link_id);
1582         return 0;
1583     }
1584 
1585     clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1586 
1587     if (pm_runtime_suspended(dev) &&
1588         pm_runtime_suspended(dev->parent) &&
1589         ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1590          !clock_stop_quirks)) {
1591         /*
1592          * if we've enabled clock stop, and the parent is suspended, the SHIM registers
1593          * are not accessible and the shim wake cannot be disabled.
1594          * The only solution is to resume the entire bus to full power
1595          */
1596 
1597         /*
1598          * If any operation in this block fails, we keep going since we don't want
1599          * to prevent system suspend from happening and errors should be recoverable
1600          * on resume.
1601          */
1602 
1603         /*
1604          * first resume the device for this link. This will also by construction
1605          * resume the PCI parent device.
1606          */
1607         ret = pm_request_resume(dev);
1608         if (ret < 0) {
1609             dev_err(dev, "%s: pm_request_resume failed: %d\n", __func__, ret);
1610             return 0;
1611         }
1612 
1613         /*
1614          * Continue resuming the entire bus (parent + child devices) to exit
1615          * the clock stop mode. If there are no devices connected on this link
1616          * this is a no-op.
1617          * The resume to full power could have been implemented with a .prepare
1618          * step in SoundWire codec drivers. This would however require a lot
1619          * of code to handle an Intel-specific corner case. It is simpler in
1620          * practice to add a loop at the link level.
1621          */
1622         ret = device_for_each_child(bus->dev, NULL, intel_resume_child_device);
1623 
1624         if (ret < 0)
1625             dev_err(dev, "%s: intel_resume_child_device failed: %d\n", __func__, ret);
1626     }
1627 
1628     return 0;
1629 }
1630 
1631 static int __maybe_unused intel_suspend(struct device *dev)
1632 {
1633     struct sdw_cdns *cdns = dev_get_drvdata(dev);
1634     struct sdw_intel *sdw = cdns_to_intel(cdns);
1635     struct sdw_bus *bus = &cdns->bus;
1636     u32 clock_stop_quirks;
1637     int ret;
1638 
1639     if (bus->prop.hw_disabled || !sdw->startup_done) {
1640         dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1641             bus->link_id);
1642         return 0;
1643     }
1644 
1645     if (pm_runtime_suspended(dev)) {
1646         dev_dbg(dev, "%s: pm_runtime status: suspended\n", __func__);
1647 
1648         clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1649 
1650         if ((clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) ||
1651             !clock_stop_quirks) {
1652 
1653             if (pm_runtime_suspended(dev->parent)) {
1654                 /*
1655                  * paranoia check: this should not happen with the .prepare
1656                  * resume to full power
1657                  */
1658                 dev_err(dev, "%s: invalid config: parent is suspended\n", __func__);
1659             } else {
1660                 intel_shim_wake(sdw, false);
1661             }
1662         }
1663 
1664         return 0;
1665     }
1666 
1667     ret = sdw_cdns_enable_interrupt(cdns, false);
1668     if (ret < 0) {
1669         dev_err(dev, "cannot disable interrupts on suspend\n");
1670         return ret;
1671     }
1672 
1673     ret = intel_link_power_down(sdw);
1674     if (ret) {
1675         dev_err(dev, "Link power down failed: %d\n", ret);
1676         return ret;
1677     }
1678 
1679     intel_shim_wake(sdw, false);
1680 
1681     return 0;
1682 }
1683 
1684 static int __maybe_unused intel_suspend_runtime(struct device *dev)
1685 {
1686     struct sdw_cdns *cdns = dev_get_drvdata(dev);
1687     struct sdw_intel *sdw = cdns_to_intel(cdns);
1688     struct sdw_bus *bus = &cdns->bus;
1689     u32 clock_stop_quirks;
1690     int ret;
1691 
1692     if (bus->prop.hw_disabled || !sdw->startup_done) {
1693         dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1694             bus->link_id);
1695         return 0;
1696     }
1697 
1698     clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1699 
1700     if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1701 
1702         ret = sdw_cdns_enable_interrupt(cdns, false);
1703         if (ret < 0) {
1704             dev_err(dev, "cannot disable interrupts on suspend\n");
1705             return ret;
1706         }
1707 
1708         ret = intel_link_power_down(sdw);
1709         if (ret) {
1710             dev_err(dev, "Link power down failed: %d\n", ret);
1711             return ret;
1712         }
1713 
1714         intel_shim_wake(sdw, false);
1715 
1716     } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET ||
1717            !clock_stop_quirks) {
1718         bool wake_enable = true;
1719 
1720         ret = sdw_cdns_clock_stop(cdns, true);
1721         if (ret < 0) {
1722             dev_err(dev, "cannot enable clock stop on suspend\n");
1723             wake_enable = false;
1724         }
1725 
1726         ret = sdw_cdns_enable_interrupt(cdns, false);
1727         if (ret < 0) {
1728             dev_err(dev, "cannot disable interrupts on suspend\n");
1729             return ret;
1730         }
1731 
1732         ret = intel_link_power_down(sdw);
1733         if (ret) {
1734             dev_err(dev, "Link power down failed: %d\n", ret);
1735             return ret;
1736         }
1737 
1738         intel_shim_wake(sdw, wake_enable);
1739     } else {
1740         dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
1741             __func__, clock_stop_quirks);
1742         ret = -EINVAL;
1743     }
1744 
1745     return ret;
1746 }
1747 
1748 static int __maybe_unused intel_resume(struct device *dev)
1749 {
1750     struct sdw_cdns *cdns = dev_get_drvdata(dev);
1751     struct sdw_intel *sdw = cdns_to_intel(cdns);
1752     struct sdw_bus *bus = &cdns->bus;
1753     int link_flags;
1754     bool multi_link;
1755     int ret;
1756 
1757     if (bus->prop.hw_disabled || !sdw->startup_done) {
1758         dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1759             bus->link_id);
1760         return 0;
1761     }
1762 
1763     link_flags = md_flags >> (bus->link_id * 8);
1764     multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1765 
1766     if (pm_runtime_suspended(dev)) {
1767         dev_dbg(dev, "%s: pm_runtime status was suspended, forcing active\n", __func__);
1768 
1769         /* follow required sequence from runtime_pm.rst */
1770         pm_runtime_disable(dev);
1771         pm_runtime_set_active(dev);
1772         pm_runtime_mark_last_busy(dev);
1773         pm_runtime_enable(dev);
1774 
1775         link_flags = md_flags >> (bus->link_id * 8);
1776 
1777         if (!(link_flags & SDW_INTEL_MASTER_DISABLE_PM_RUNTIME_IDLE))
1778             pm_runtime_idle(dev);
1779     }
1780 
1781     ret = intel_init(sdw);
1782     if (ret) {
1783         dev_err(dev, "%s failed: %d\n", __func__, ret);
1784         return ret;
1785     }
1786 
1787     /*
1788      * make sure all Slaves are tagged as UNATTACHED and provide
1789      * reason for reinitialization
1790      */
1791     sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1792 
1793     ret = sdw_cdns_enable_interrupt(cdns, true);
1794     if (ret < 0) {
1795         dev_err(dev, "cannot enable interrupts during resume\n");
1796         return ret;
1797     }
1798 
1799     /*
1800      * follow recommended programming flows to avoid timeouts when
1801      * gsync is enabled
1802      */
1803     if (multi_link)
1804         intel_shim_sync_arm(sdw);
1805 
1806     ret = sdw_cdns_init(&sdw->cdns);
1807     if (ret < 0) {
1808         dev_err(dev, "unable to initialize Cadence IP during resume\n");
1809         return ret;
1810     }
1811 
1812     ret = sdw_cdns_exit_reset(cdns);
1813     if (ret < 0) {
1814         dev_err(dev, "unable to exit bus reset sequence during resume\n");
1815         return ret;
1816     }
1817 
1818     if (multi_link) {
1819         ret = intel_shim_sync_go(sdw);
1820         if (ret < 0) {
1821             dev_err(dev, "sync go failed during resume\n");
1822             return ret;
1823         }
1824     }
1825     sdw_cdns_check_self_clearing_bits(cdns, __func__,
1826                       true, INTEL_MASTER_RESET_ITERATIONS);
1827 
1828     /*
1829      * after system resume, the pm_runtime suspend() may kick in
1830      * during the enumeration, before any children device force the
1831      * master device to remain active.  Using pm_runtime_get()
1832      * routines is not really possible, since it'd prevent the
1833      * master from suspending.
1834      * A reasonable compromise is to update the pm_runtime
1835      * counters and delay the pm_runtime suspend by several
1836      * seconds, by when all enumeration should be complete.
1837      */
1838     pm_runtime_mark_last_busy(dev);
1839 
1840     return ret;
1841 }
1842 
1843 static int __maybe_unused intel_resume_runtime(struct device *dev)
1844 {
1845     struct sdw_cdns *cdns = dev_get_drvdata(dev);
1846     struct sdw_intel *sdw = cdns_to_intel(cdns);
1847     struct sdw_bus *bus = &cdns->bus;
1848     u32 clock_stop_quirks;
1849     bool clock_stop0;
1850     int link_flags;
1851     bool multi_link;
1852     int status;
1853     int ret;
1854 
1855     if (bus->prop.hw_disabled || !sdw->startup_done) {
1856         dev_dbg(dev, "SoundWire master %d is disabled or not-started, ignoring\n",
1857             bus->link_id);
1858         return 0;
1859     }
1860 
1861     /* unconditionally disable WAKEEN interrupt */
1862     intel_shim_wake(sdw, false);
1863 
1864     link_flags = md_flags >> (bus->link_id * 8);
1865     multi_link = !(link_flags & SDW_INTEL_MASTER_DISABLE_MULTI_LINK);
1866 
1867     clock_stop_quirks = sdw->link_res->clock_stop_quirks;
1868 
1869     if (clock_stop_quirks & SDW_INTEL_CLK_STOP_TEARDOWN) {
1870         ret = intel_init(sdw);
1871         if (ret) {
1872             dev_err(dev, "%s failed: %d\n", __func__, ret);
1873             return ret;
1874         }
1875 
1876         /*
1877          * make sure all Slaves are tagged as UNATTACHED and provide
1878          * reason for reinitialization
1879          */
1880         sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);
1881 
1882         ret = sdw_cdns_enable_interrupt(cdns, true);
1883         if (ret < 0) {
1884             dev_err(dev, "cannot enable interrupts during resume\n");
1885             return ret;
1886         }
1887 
1888         /*
1889          * follow recommended programming flows to avoid
1890          * timeouts when gsync is enabled
1891          */
1892         if (multi_link)
1893             intel_shim_sync_arm(sdw);
1894 
1895         ret = sdw_cdns_init(&sdw->cdns);
1896         if (ret < 0) {
1897             dev_err(dev, "unable to initialize Cadence IP during resume\n");
1898             return ret;
1899         }
1900 
1901         ret = sdw_cdns_exit_reset(cdns);
1902         if (ret < 0) {
1903             dev_err(dev, "unable to exit bus reset sequence during resume\n");
1904             return ret;
1905         }
1906 
1907         if (multi_link) {
1908             ret = intel_shim_sync_go(sdw);
1909             if (ret < 0) {
1910                 dev_err(dev, "sync go failed during resume\n");
1911                 return ret;
1912             }
1913         }
1914         sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime TEARDOWN",
1915                           true, INTEL_MASTER_RESET_ITERATIONS);
1916 
1917     } else if (clock_stop_quirks & SDW_INTEL_CLK_STOP_BUS_RESET) {
1918         ret = intel_init(sdw);
1919         if (ret) {
1920             dev_err(dev, "%s failed: %d\n", __func__, ret);
1921             return ret;
1922         }
1923 
1924         /*
1925          * An exception condition occurs for the CLK_STOP_BUS_RESET
1926          * case if one or more masters remain active. In this condition,
1927          * all the masters are powered on for they are in the same power
1928          * domain. Master can preserve its context for clock stop0, so
1929          * there is no need to clear slave status and reset bus.
1930          */
1931         clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1932 
1933         if (!clock_stop0) {
1934 
1935             /*
1936              * make sure all Slaves are tagged as UNATTACHED and
1937              * provide reason for reinitialization
1938              */
1939 
1940             status = SDW_UNATTACH_REQUEST_MASTER_RESET;
1941             sdw_clear_slave_status(bus, status);
1942 
1943             ret = sdw_cdns_enable_interrupt(cdns, true);
1944             if (ret < 0) {
1945                 dev_err(dev, "cannot enable interrupts during resume\n");
1946                 return ret;
1947             }
1948 
1949             /*
1950              * follow recommended programming flows to avoid
1951              * timeouts when gsync is enabled
1952              */
1953             if (multi_link)
1954                 intel_shim_sync_arm(sdw);
1955 
1956             /*
1957              * Re-initialize the IP since it was powered-off
1958              */
1959             sdw_cdns_init(&sdw->cdns);
1960 
1961         } else {
1962             ret = sdw_cdns_enable_interrupt(cdns, true);
1963             if (ret < 0) {
1964                 dev_err(dev, "cannot enable interrupts during resume\n");
1965                 return ret;
1966             }
1967         }
1968 
1969         ret = sdw_cdns_clock_restart(cdns, !clock_stop0);
1970         if (ret < 0) {
1971             dev_err(dev, "unable to restart clock during resume\n");
1972             return ret;
1973         }
1974 
1975         if (!clock_stop0) {
1976             ret = sdw_cdns_exit_reset(cdns);
1977             if (ret < 0) {
1978                 dev_err(dev, "unable to exit bus reset sequence during resume\n");
1979                 return ret;
1980             }
1981 
1982             if (multi_link) {
1983                 ret = intel_shim_sync_go(sdw);
1984                 if (ret < 0) {
1985                     dev_err(sdw->cdns.dev, "sync go failed during resume\n");
1986                     return ret;
1987                 }
1988             }
1989         }
1990         sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime BUS_RESET",
1991                           true, INTEL_MASTER_RESET_ITERATIONS);
1992 
1993     } else if (!clock_stop_quirks) {
1994 
1995         clock_stop0 = sdw_cdns_is_clock_stop(&sdw->cdns);
1996         if (!clock_stop0)
1997             dev_err(dev, "%s invalid configuration, clock was not stopped", __func__);
1998 
1999         ret = intel_init(sdw);
2000         if (ret) {
2001             dev_err(dev, "%s failed: %d\n", __func__, ret);
2002             return ret;
2003         }
2004 
2005         ret = sdw_cdns_enable_interrupt(cdns, true);
2006         if (ret < 0) {
2007             dev_err(dev, "cannot enable interrupts during resume\n");
2008             return ret;
2009         }
2010 
2011         ret = sdw_cdns_clock_restart(cdns, false);
2012         if (ret < 0) {
2013             dev_err(dev, "unable to resume master during resume\n");
2014             return ret;
2015         }
2016 
2017         sdw_cdns_check_self_clearing_bits(cdns, "intel_resume_runtime no_quirks",
2018                           true, INTEL_MASTER_RESET_ITERATIONS);
2019     } else {
2020         dev_err(dev, "%s clock_stop_quirks %x unsupported\n",
2021             __func__, clock_stop_quirks);
2022         ret = -EINVAL;
2023     }
2024 
2025     return ret;
2026 }
2027 
2028 static const struct dev_pm_ops intel_pm = {
2029     .prepare = intel_pm_prepare,
2030     SET_SYSTEM_SLEEP_PM_OPS(intel_suspend, intel_resume)
2031     SET_RUNTIME_PM_OPS(intel_suspend_runtime, intel_resume_runtime, NULL)
2032 };
2033 
2034 static const struct auxiliary_device_id intel_link_id_table[] = {
2035     { .name = "soundwire_intel.link" },
2036     {},
2037 };
2038 MODULE_DEVICE_TABLE(auxiliary, intel_link_id_table);
2039 
2040 static struct auxiliary_driver sdw_intel_drv = {
2041     .probe = intel_link_probe,
2042     .remove = intel_link_remove,
2043     .driver = {
2044         /* auxiliary_driver_register() sets .name to be the modname */
2045         .pm = &intel_pm,
2046     },
2047     .id_table = intel_link_id_table
2048 };
2049 module_auxiliary_driver(sdw_intel_drv);
2050 
2051 MODULE_LICENSE("Dual BSD/GPL");
2052 MODULE_DESCRIPTION("Intel Soundwire Link Driver");
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