soc/ti/pm33xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AM33XX Power Management Routines
0004  *
0005  * Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
0006  *  Vaibhav Bedia, Dave Gerlach
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/cpu.h>
0011 #include <linux/err.h>
0012 #include <linux/genalloc.h>
0013 #include <linux/kernel.h>
0014 #include <linux/init.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/nvmem-consumer.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <linux/platform_data/pm33xx.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/rtc.h>
0024 #include <linux/rtc/rtc-omap.h>
0025 #include <linux/sizes.h>
0026 #include <linux/sram.h>
0027 #include <linux/suspend.h>
0028 #include <linux/ti-emif-sram.h>
0029 #include <linux/wkup_m3_ipc.h>
0030
0031 #include <asm/proc-fns.h>
0032 #include <asm/suspend.h>
0033 #include <asm/system_misc.h>
0034
0035 #define AMX3_PM_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
0036                      (unsigned long)pm_sram->do_wfi)
0037
0038 #define RTC_SCRATCH_RESUME_REG  0
0039 #define RTC_SCRATCH_MAGIC_REG   1
0040 #define RTC_REG_BOOT_MAGIC  0x8cd0 /* RTC */
0041 #define GIC_INT_SET_PENDING_BASE 0x200
0042 #define AM43XX_GIC_DIST_BASE    0x48241000
0043
0044 static void __iomem *rtc_base_virt;
0045 static struct clk *rtc_fck;
0046 static u32 rtc_magic_val;
0047
0048 static int (*am33xx_do_wfi_sram)(unsigned long unused);
0049 static phys_addr_t am33xx_do_wfi_sram_phys;
0050
0051 static struct gen_pool *sram_pool, *sram_pool_data;
0052 static unsigned long ocmcram_location, ocmcram_location_data;
0053
0054 static struct rtc_device *omap_rtc;
0055 static void __iomem *gic_dist_base;
0056
0057 static struct am33xx_pm_platform_data *pm_ops;
0058 static struct am33xx_pm_sram_addr *pm_sram;
0059
0060 static struct device *pm33xx_dev;
0061 static struct wkup_m3_ipc *m3_ipc;
0062
0063 #ifdef CONFIG_SUSPEND
0064 static int rtc_only_idle;
0065 static int retrigger_irq;
0066 static unsigned long suspend_wfi_flags;
0067
0068 static struct wkup_m3_wakeup_src wakeup_src = {.irq_nr = 0,
0069     .src = "Unknown",
0070 };
0071
0072 static struct wkup_m3_wakeup_src rtc_alarm_wakeup = {
0073     .irq_nr = 108, .src = "RTC Alarm",
0074 };
0075
0076 static struct wkup_m3_wakeup_src rtc_ext_wakeup = {
0077     .irq_nr = 0, .src = "Ext wakeup",
0078 };
0079 #endif
0080
0081 static u32 sram_suspend_address(unsigned long addr)
0082 {
0083     return ((unsigned long)am33xx_do_wfi_sram +
0084         AMX3_PM_SRAM_SYMBOL_OFFSET(addr));
0085 }
0086
0087 static int am33xx_push_sram_idle(void)
0088 {
0089     struct am33xx_pm_ro_sram_data ro_sram_data;
0090     int ret;
0091     u32 table_addr, ro_data_addr;
0092     void *copy_addr;
0093
0094     ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
0095     ro_sram_data.amx3_pm_sram_data_phys =
0096         gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
0097     ro_sram_data.rtc_base_virt = rtc_base_virt;
0098
0099     /* Save physical address to calculate resume offset during pm init */
0100     am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
0101                             ocmcram_location);
0102
0103     am33xx_do_wfi_sram = sram_exec_copy(sram_pool, (void *)ocmcram_location,
0104                         pm_sram->do_wfi,
0105                         *pm_sram->do_wfi_sz);
0106     if (!am33xx_do_wfi_sram) {
0107         dev_err(pm33xx_dev,
0108             "PM: %s: am33xx_do_wfi copy to sram failed\n",
0109             __func__);
0110         return -ENODEV;
0111     }
0112
0113     table_addr =
0114         sram_suspend_address((unsigned long)pm_sram->emif_sram_table);
0115     ret = ti_emif_copy_pm_function_table(sram_pool, (void *)table_addr);
0116     if (ret) {
0117         dev_dbg(pm33xx_dev,
0118             "PM: %s: EMIF function copy failed\n", __func__);
0119         return -EPROBE_DEFER;
0120     }
0121
0122     ro_data_addr =
0123         sram_suspend_address((unsigned long)pm_sram->ro_sram_data);
0124     copy_addr = sram_exec_copy(sram_pool, (void *)ro_data_addr,
0125                    &ro_sram_data,
0126                    sizeof(ro_sram_data));
0127     if (!copy_addr) {
0128         dev_err(pm33xx_dev,
0129             "PM: %s: ro_sram_data copy to sram failed\n",
0130             __func__);
0131         return -ENODEV;
0132     }
0133
0134     return 0;
0135 }
0136
0137 static int am33xx_do_sram_idle(u32 wfi_flags)
0138 {
0139     if (!m3_ipc || !pm_ops)
0140         return 0;
0141
0142     if (wfi_flags & WFI_FLAG_WAKE_M3)
0143         m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE);
0144
0145     return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags);
0146 }
0147
0148 static int __init am43xx_map_gic(void)
0149 {
0150     gic_dist_base = ioremap(AM43XX_GIC_DIST_BASE, SZ_4K);
0151
0152     if (!gic_dist_base)
0153         return -ENOMEM;
0154
0155     return 0;
0156 }
0157
0158 #ifdef CONFIG_SUSPEND
0159 static struct wkup_m3_wakeup_src rtc_wake_src(void)
0160 {
0161     u32 i;
0162
0163     i = __raw_readl(rtc_base_virt + 0x44) & 0x40;
0164
0165     if (i) {
0166         retrigger_irq = rtc_alarm_wakeup.irq_nr;
0167         return rtc_alarm_wakeup;
0168     }
0169
0170     retrigger_irq = rtc_ext_wakeup.irq_nr;
0171
0172     return rtc_ext_wakeup;
0173 }
0174
0175 static int am33xx_rtc_only_idle(unsigned long wfi_flags)
0176 {
0177     omap_rtc_power_off_program(&omap_rtc->dev);
0178     am33xx_do_wfi_sram(wfi_flags);
0179     return 0;
0180 }
0181
0182 /*
0183  * Note that the RTC module clock must be re-enabled only for rtc+ddr suspend.
0184  * And looks like the module can stay in SYSC_IDLE_SMART_WKUP mode configured
0185  * by the interconnect code just fine for both rtc+ddr suspend and retention
0186  * suspend.
0187  */
0188 static int am33xx_pm_suspend(suspend_state_t suspend_state)
0189 {
0190     int i, ret = 0;
0191
0192     if (suspend_state == PM_SUSPEND_MEM &&
0193         pm_ops->check_off_mode_enable()) {
0194         ret = clk_prepare_enable(rtc_fck);
0195         if (ret) {
0196             dev_err(pm33xx_dev, "Failed to enable clock: %i\n", ret);
0197             return ret;
0198         }
0199
0200         pm_ops->save_context();
0201         suspend_wfi_flags |= WFI_FLAG_RTC_ONLY;
0202         clk_save_context();
0203         ret = pm_ops->soc_suspend(suspend_state, am33xx_rtc_only_idle,
0204                       suspend_wfi_flags);
0205
0206         suspend_wfi_flags &= ~WFI_FLAG_RTC_ONLY;
0207         dev_info(pm33xx_dev, "Entering RTC Only mode with DDR in self-refresh\n");
0208
0209         if (!ret) {
0210             clk_restore_context();
0211             pm_ops->restore_context();
0212             m3_ipc->ops->set_rtc_only(m3_ipc);
0213             am33xx_push_sram_idle();
0214         }
0215     } else {
0216         ret = pm_ops->soc_suspend(suspend_state, am33xx_do_wfi_sram,
0217                       suspend_wfi_flags);
0218     }
0219
0220     if (ret) {
0221         dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
0222     } else {
0223         i = m3_ipc->ops->request_pm_status(m3_ipc);
0224
0225         switch (i) {
0226         case 0:
0227             dev_info(pm33xx_dev,
0228                  "PM: Successfully put all powerdomains to target state\n");
0229             break;
0230         case 1:
0231             dev_err(pm33xx_dev,
0232                 "PM: Could not transition all powerdomains to target state\n");
0233             ret = -1;
0234             break;
0235         default:
0236             dev_err(pm33xx_dev,
0237                 "PM: CM3 returned unknown result = %d\n", i);
0238             ret = -1;
0239         }
0240
0241         /* print the wakeup reason */
0242         if (rtc_only_idle) {
0243             wakeup_src = rtc_wake_src();
0244             pr_info("PM: Wakeup source %s\n", wakeup_src.src);
0245         } else {
0246             pr_info("PM: Wakeup source %s\n",
0247                 m3_ipc->ops->request_wake_src(m3_ipc));
0248         }
0249     }
0250
0251     if (suspend_state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable())
0252         clk_disable_unprepare(rtc_fck);
0253
0254     return ret;
0255 }
0256
0257 static int am33xx_pm_enter(suspend_state_t suspend_state)
0258 {
0259     int ret = 0;
0260
0261     switch (suspend_state) {
0262     case PM_SUSPEND_MEM:
0263     case PM_SUSPEND_STANDBY:
0264         ret = am33xx_pm_suspend(suspend_state);
0265         break;
0266     default:
0267         ret = -EINVAL;
0268     }
0269
0270     return ret;
0271 }
0272
0273 static int am33xx_pm_begin(suspend_state_t state)
0274 {
0275     int ret = -EINVAL;
0276     struct nvmem_device *nvmem;
0277
0278     if (state == PM_SUSPEND_MEM && pm_ops->check_off_mode_enable()) {
0279         nvmem = devm_nvmem_device_get(&omap_rtc->dev,
0280                           "omap_rtc_scratch0");
0281         if (!IS_ERR(nvmem))
0282             nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
0283                        (void *)&rtc_magic_val);
0284         rtc_only_idle = 1;
0285     } else {
0286         rtc_only_idle = 0;
0287     }
0288
0289     pm_ops->begin_suspend();
0290
0291     switch (state) {
0292     case PM_SUSPEND_MEM:
0293         ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_DEEPSLEEP);
0294         break;
0295     case PM_SUSPEND_STANDBY:
0296         ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_STANDBY);
0297         break;
0298     }
0299
0300     return ret;
0301 }
0302
0303 static void am33xx_pm_end(void)
0304 {
0305     u32 val = 0;
0306     struct nvmem_device *nvmem;
0307
0308     nvmem = devm_nvmem_device_get(&omap_rtc->dev, "omap_rtc_scratch0");
0309     if (IS_ERR(nvmem))
0310         return;
0311
0312     m3_ipc->ops->finish_low_power(m3_ipc);
0313     if (rtc_only_idle) {
0314         if (retrigger_irq) {
0315             /*
0316              * 32 bits of Interrupt Set-Pending correspond to 32
0317              * 32 interrupts. Compute the bit offset of the
0318              * Interrupt and set that particular bit
0319              * Compute the register offset by dividing interrupt
0320              * number by 32 and mutiplying by 4
0321              */
0322             writel_relaxed(1 << (retrigger_irq & 31),
0323                        gic_dist_base + GIC_INT_SET_PENDING_BASE
0324                        + retrigger_irq / 32 * 4);
0325         }
0326
0327         nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4, 4,
0328                    (void *)&val);
0329     }
0330
0331     rtc_only_idle = 0;
0332
0333     pm_ops->finish_suspend();
0334 }
0335
0336 static int am33xx_pm_valid(suspend_state_t state)
0337 {
0338     switch (state) {
0339     case PM_SUSPEND_STANDBY:
0340     case PM_SUSPEND_MEM:
0341         return 1;
0342     default:
0343         return 0;
0344     }
0345 }
0346
0347 static const struct platform_suspend_ops am33xx_pm_ops = {
0348     .begin      = am33xx_pm_begin,
0349     .end        = am33xx_pm_end,
0350     .enter      = am33xx_pm_enter,
0351     .valid      = am33xx_pm_valid,
0352 };
0353 #endif /* CONFIG_SUSPEND */
0354
0355 static void am33xx_pm_set_ipc_ops(void)
0356 {
0357     u32 resume_address;
0358     int temp;
0359
0360     temp = ti_emif_get_mem_type();
0361     if (temp < 0) {
0362         dev_err(pm33xx_dev, "PM: Cannot determine memory type, no PM available\n");
0363         return;
0364     }
0365     m3_ipc->ops->set_mem_type(m3_ipc, temp);
0366
0367     /* Physical resume address to be used by ROM code */
0368     resume_address = am33xx_do_wfi_sram_phys +
0369              *pm_sram->resume_offset + 0x4;
0370
0371     m3_ipc->ops->set_resume_address(m3_ipc, (void *)resume_address);
0372 }
0373
0374 static void am33xx_pm_free_sram(void)
0375 {
0376     gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
0377     gen_pool_free(sram_pool_data, ocmcram_location_data,
0378               sizeof(struct am33xx_pm_ro_sram_data));
0379 }
0380
0381 /*
0382  * Push the minimal suspend-resume code to SRAM
0383  */
0384 static int am33xx_pm_alloc_sram(void)
0385 {
0386     struct device_node *np;
0387     int ret = 0;
0388
0389     np = of_find_compatible_node(NULL, NULL, "ti,omap3-mpu");
0390     if (!np) {
0391         np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
0392         if (!np) {
0393             dev_err(pm33xx_dev, "PM: %s: Unable to find device node for mpu\n",
0394                 __func__);
0395             return -ENODEV;
0396         }
0397     }
0398
0399     sram_pool = of_gen_pool_get(np, "pm-sram", 0);
0400     if (!sram_pool) {
0401         dev_err(pm33xx_dev, "PM: %s: Unable to get sram pool for ocmcram\n",
0402             __func__);
0403         ret = -ENODEV;
0404         goto mpu_put_node;
0405     }
0406
0407     sram_pool_data = of_gen_pool_get(np, "pm-sram", 1);
0408     if (!sram_pool_data) {
0409         dev_err(pm33xx_dev, "PM: %s: Unable to get sram data pool for ocmcram\n",
0410             __func__);
0411         ret = -ENODEV;
0412         goto mpu_put_node;
0413     }
0414
0415     ocmcram_location = gen_pool_alloc(sram_pool, *pm_sram->do_wfi_sz);
0416     if (!ocmcram_location) {
0417         dev_err(pm33xx_dev, "PM: %s: Unable to allocate memory from ocmcram\n",
0418             __func__);
0419         ret = -ENOMEM;
0420         goto mpu_put_node;
0421     }
0422
0423     ocmcram_location_data = gen_pool_alloc(sram_pool_data,
0424                            sizeof(struct emif_regs_amx3));
0425     if (!ocmcram_location_data) {
0426         dev_err(pm33xx_dev, "PM: Unable to allocate memory from ocmcram\n");
0427         gen_pool_free(sram_pool, ocmcram_location, *pm_sram->do_wfi_sz);
0428         ret = -ENOMEM;
0429     }
0430
0431 mpu_put_node:
0432     of_node_put(np);
0433     return ret;
0434 }
0435
0436 static int am33xx_pm_rtc_setup(void)
0437 {
0438     struct device_node *np;
0439     unsigned long val = 0;
0440     struct nvmem_device *nvmem;
0441     int error;
0442
0443     np = of_find_node_by_name(NULL, "rtc");
0444
0445     if (of_device_is_available(np)) {
0446         /* RTC interconnect target module clock */
0447         rtc_fck = of_clk_get_by_name(np->parent, "fck");
0448         if (IS_ERR(rtc_fck))
0449             return PTR_ERR(rtc_fck);
0450
0451         rtc_base_virt = of_iomap(np, 0);
0452         if (!rtc_base_virt) {
0453             pr_warn("PM: could not iomap rtc");
0454             error = -ENODEV;
0455             goto err_clk_put;
0456         }
0457
0458         omap_rtc = rtc_class_open("rtc0");
0459         if (!omap_rtc) {
0460             pr_warn("PM: rtc0 not available");
0461             error = -EPROBE_DEFER;
0462             goto err_iounmap;
0463         }
0464
0465         nvmem = devm_nvmem_device_get(&omap_rtc->dev,
0466                           "omap_rtc_scratch0");
0467         if (!IS_ERR(nvmem)) {
0468             nvmem_device_read(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
0469                       4, (void *)&rtc_magic_val);
0470             if ((rtc_magic_val & 0xffff) != RTC_REG_BOOT_MAGIC)
0471                 pr_warn("PM: bootloader does not support rtc-only!\n");
0472
0473             nvmem_device_write(nvmem, RTC_SCRATCH_MAGIC_REG * 4,
0474                        4, (void *)&val);
0475             val = pm_sram->resume_address;
0476             nvmem_device_write(nvmem, RTC_SCRATCH_RESUME_REG * 4,
0477                        4, (void *)&val);
0478         }
0479     } else {
0480         pr_warn("PM: no-rtc available, rtc-only mode disabled.\n");
0481     }
0482
0483     return 0;
0484
0485 err_iounmap:
0486     iounmap(rtc_base_virt);
0487 err_clk_put:
0488     clk_put(rtc_fck);
0489
0490     return error;
0491 }
0492
0493 static int am33xx_pm_probe(struct platform_device *pdev)
0494 {
0495     struct device *dev = &pdev->dev;
0496     int ret;
0497
0498     if (!of_machine_is_compatible("ti,am33xx") &&
0499         !of_machine_is_compatible("ti,am43"))
0500         return -ENODEV;
0501
0502     pm_ops = dev->platform_data;
0503     if (!pm_ops) {
0504         dev_err(dev, "PM: Cannot get core PM ops!\n");
0505         return -ENODEV;
0506     }
0507
0508     ret = am43xx_map_gic();
0509     if (ret) {
0510         pr_err("PM: Could not ioremap GIC base\n");
0511         return ret;
0512     }
0513
0514     pm_sram = pm_ops->get_sram_addrs();
0515     if (!pm_sram) {
0516         dev_err(dev, "PM: Cannot get PM asm function addresses!!\n");
0517         return -ENODEV;
0518     }
0519
0520     m3_ipc = wkup_m3_ipc_get();
0521     if (!m3_ipc) {
0522         pr_err("PM: Cannot get wkup_m3_ipc handle\n");
0523         return -EPROBE_DEFER;
0524     }
0525
0526     pm33xx_dev = dev;
0527
0528     ret = am33xx_pm_alloc_sram();
0529     if (ret)
0530         return ret;
0531
0532     ret = am33xx_pm_rtc_setup();
0533     if (ret)
0534         goto err_free_sram;
0535
0536     ret = am33xx_push_sram_idle();
0537     if (ret)
0538         goto err_unsetup_rtc;
0539
0540     am33xx_pm_set_ipc_ops();
0541
0542 #ifdef CONFIG_SUSPEND
0543     suspend_set_ops(&am33xx_pm_ops);
0544
0545     /*
0546      * For a system suspend we must flush the caches, we want
0547      * the DDR in self-refresh, we want to save the context
0548      * of the EMIF, and we want the wkup_m3 to handle low-power
0549      * transition.
0550      */
0551     suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
0552     suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
0553     suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
0554     suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
0555 #endif /* CONFIG_SUSPEND */
0556
0557     pm_runtime_enable(dev);
0558     ret = pm_runtime_resume_and_get(dev);
0559     if (ret < 0)
0560         goto err_pm_runtime_disable;
0561
0562     ret = pm_ops->init(am33xx_do_sram_idle);
0563     if (ret) {
0564         dev_err(dev, "Unable to call core pm init!\n");
0565         ret = -ENODEV;
0566         goto err_pm_runtime_put;
0567     }
0568
0569     return 0;
0570
0571 err_pm_runtime_put:
0572     pm_runtime_put_sync(dev);
0573 err_pm_runtime_disable:
0574     pm_runtime_disable(dev);
0575     wkup_m3_ipc_put(m3_ipc);
0576 err_unsetup_rtc:
0577     iounmap(rtc_base_virt);
0578     clk_put(rtc_fck);
0579 err_free_sram:
0580     am33xx_pm_free_sram();
0581     pm33xx_dev = NULL;
0582     return ret;
0583 }
0584
0585 static int am33xx_pm_remove(struct platform_device *pdev)
0586 {
0587     pm_runtime_put_sync(&pdev->dev);
0588     pm_runtime_disable(&pdev->dev);
0589     if (pm_ops->deinit)
0590         pm_ops->deinit();
0591     suspend_set_ops(NULL);
0592     wkup_m3_ipc_put(m3_ipc);
0593     am33xx_pm_free_sram();
0594     iounmap(rtc_base_virt);
0595     clk_put(rtc_fck);
0596     return 0;
0597 }
0598
0599 static struct platform_driver am33xx_pm_driver = {
0600     .driver = {
0601         .name   = "pm33xx",
0602     },
0603     .probe = am33xx_pm_probe,
0604     .remove = am33xx_pm_remove,
0605 };
0606 module_platform_driver(am33xx_pm_driver);
0607
0608 MODULE_ALIAS("platform:pm33xx");
0609 MODULE_LICENSE("GPL v2");
0610 MODULE_DESCRIPTION("am33xx power management driver");