soc/tegra/regulators-tegra30.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Voltage regulators coupler for NVIDIA Tegra30
0004  * Copyright (C) 2019 GRATE-DRIVER project
0005  *
0006  * Voltage constraints borrowed from downstream kernel sources
0007  * Copyright (C) 2010-2011 NVIDIA Corporation
0008  */
0009
0010 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
0011
0012 #include <linux/init.h>
0013 #include <linux/kernel.h>
0014 #include <linux/of.h>
0015 #include <linux/reboot.h>
0016 #include <linux/regulator/coupler.h>
0017 #include <linux/regulator/driver.h>
0018 #include <linux/regulator/machine.h>
0019 #include <linux/suspend.h>
0020
0021 #include <soc/tegra/fuse.h>
0022 #include <soc/tegra/pmc.h>
0023
0024 struct tegra_regulator_coupler {
0025     struct regulator_coupler coupler;
0026     struct regulator_dev *core_rdev;
0027     struct regulator_dev *cpu_rdev;
0028     struct notifier_block reboot_notifier;
0029     struct notifier_block suspend_notifier;
0030     int core_min_uV, cpu_min_uV;
0031     bool sys_reboot_mode_req;
0032     bool sys_reboot_mode;
0033     bool sys_suspend_mode_req;
0034     bool sys_suspend_mode;
0035 };
0036
0037 static inline struct tegra_regulator_coupler *
0038 to_tegra_coupler(struct regulator_coupler *coupler)
0039 {
0040     return container_of(coupler, struct tegra_regulator_coupler, coupler);
0041 }
0042
0043 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra,
0044                   struct regulator_dev *core_rdev)
0045 {
0046     int core_min_uV = 0;
0047     int core_max_uV;
0048     int core_cur_uV;
0049     int err;
0050
0051     /*
0052      * Tegra30 SoC has critical DVFS-capable devices that are
0053      * permanently-active or active at a boot time, like EMC
0054      * (DRAM controller) or Display controller for example.
0055      *
0056      * The voltage of a CORE SoC power domain shall not be dropped below
0057      * a minimum level, which is determined by device's clock rate.
0058      * This means that we can't fully allow CORE voltage scaling until
0059      * the state of all DVFS-critical CORE devices is synced.
0060      */
0061     if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) {
0062         pr_info_once("voltage state synced\n");
0063         return 0;
0064     }
0065
0066     if (tegra->core_min_uV > 0)
0067         return tegra->core_min_uV;
0068
0069     core_cur_uV = regulator_get_voltage_rdev(core_rdev);
0070     if (core_cur_uV < 0)
0071         return core_cur_uV;
0072
0073     core_max_uV = max(core_cur_uV, 1200000);
0074
0075     err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV);
0076     if (err)
0077         return err;
0078
0079     /*
0080      * Limit minimum CORE voltage to a value left from bootloader or,
0081      * if it's unreasonably low value, to the most common 1.2v or to
0082      * whatever maximum value defined via board's device-tree.
0083      */
0084     tegra->core_min_uV = core_max_uV;
0085
0086     pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);
0087
0088     return tegra->core_min_uV;
0089 }
0090
0091 static int tegra30_core_cpu_limit(int cpu_uV)
0092 {
0093     if (cpu_uV < 800000)
0094         return 950000;
0095
0096     if (cpu_uV < 900000)
0097         return 1000000;
0098
0099     if (cpu_uV < 1000000)
0100         return 1100000;
0101
0102     if (cpu_uV < 1100000)
0103         return 1200000;
0104
0105     if (cpu_uV < 1250000) {
0106         switch (tegra_sku_info.cpu_speedo_id) {
0107         case 0 ... 1:
0108         case 4:
0109         case 7 ... 8:
0110             return 1200000;
0111
0112         default:
0113             return 1300000;
0114         }
0115     }
0116
0117     return -EINVAL;
0118 }
0119
0120 static int tegra30_cpu_nominal_uV(void)
0121 {
0122     switch (tegra_sku_info.cpu_speedo_id) {
0123     case 10 ... 11:
0124         return  850000;
0125
0126     case 9:
0127         return  912000;
0128
0129     case 1 ...  3:
0130     case 7 ...  8:
0131         return 1050000;
0132
0133     default:
0134         return 1125000;
0135
0136     case  4 ...  6:
0137     case 12 ... 13:
0138         return 1237000;
0139     }
0140 }
0141
0142 static int tegra30_core_nominal_uV(void)
0143 {
0144     switch (tegra_sku_info.soc_speedo_id) {
0145     case 0:
0146         return 1200000;
0147
0148     case 1:
0149         if (tegra_sku_info.cpu_speedo_id != 7 &&
0150             tegra_sku_info.cpu_speedo_id != 8)
0151             return 1200000;
0152
0153         fallthrough;
0154
0155     case 2:
0156         if (tegra_sku_info.cpu_speedo_id != 13)
0157             return 1300000;
0158
0159         return 1350000;
0160
0161     default:
0162         return 1250000;
0163     }
0164 }
0165
0166 static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra,
0167                   struct regulator_dev *cpu_rdev,
0168                   struct regulator_dev *core_rdev)
0169 {
0170     int core_min_uV, core_max_uV = INT_MAX;
0171     int cpu_min_uV, cpu_max_uV = INT_MAX;
0172     int cpu_min_uV_consumers = 0;
0173     int core_min_limited_uV;
0174     int core_target_uV;
0175     int cpu_target_uV;
0176     int core_max_step;
0177     int cpu_max_step;
0178     int max_spread;
0179     int core_uV;
0180     int cpu_uV;
0181     int err;
0182
0183     /*
0184      * CPU voltage should not got lower than 300mV from the CORE.
0185      * CPU voltage should stay below the CORE by 100mV+, depending
0186      * by the CORE voltage. This applies to all Tegra30 SoC's.
0187      */
0188     max_spread = cpu_rdev->constraints->max_spread[0];
0189     cpu_max_step = cpu_rdev->constraints->max_uV_step;
0190     core_max_step = core_rdev->constraints->max_uV_step;
0191
0192     if (!max_spread) {
0193         pr_err_once("cpu-core max-spread is undefined in device-tree\n");
0194         max_spread = 300000;
0195     }
0196
0197     if (!cpu_max_step) {
0198         pr_err_once("cpu max-step is undefined in device-tree\n");
0199         cpu_max_step = 150000;
0200     }
0201
0202     if (!core_max_step) {
0203         pr_err_once("core max-step is undefined in device-tree\n");
0204         core_max_step = 150000;
0205     }
0206
0207     /*
0208      * The CORE voltage scaling is currently not hooked up in drivers,
0209      * hence we will limit the minimum CORE voltage to a reasonable value.
0210      * This should be good enough for the time being.
0211      */
0212     core_min_uV = tegra30_core_limit(tegra, core_rdev);
0213     if (core_min_uV < 0)
0214         return core_min_uV;
0215
0216     err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV,
0217                     PM_SUSPEND_ON);
0218     if (err)
0219         return err;
0220
0221     /* prepare voltage level for suspend */
0222     if (tegra->sys_suspend_mode)
0223         core_min_uV = clamp(tegra30_core_nominal_uV(),
0224                     core_min_uV, core_max_uV);
0225
0226     core_uV = regulator_get_voltage_rdev(core_rdev);
0227     if (core_uV < 0)
0228         return core_uV;
0229
0230     cpu_min_uV = core_min_uV - max_spread;
0231
0232     err = regulator_check_consumers(cpu_rdev, &cpu_min_uV, &cpu_max_uV,
0233                     PM_SUSPEND_ON);
0234     if (err)
0235         return err;
0236
0237     err = regulator_check_consumers(cpu_rdev, &cpu_min_uV_consumers,
0238                     &cpu_max_uV, PM_SUSPEND_ON);
0239     if (err)
0240         return err;
0241
0242     err = regulator_check_voltage(cpu_rdev, &cpu_min_uV, &cpu_max_uV);
0243     if (err)
0244         return err;
0245
0246     cpu_uV = regulator_get_voltage_rdev(cpu_rdev);
0247     if (cpu_uV < 0)
0248         return cpu_uV;
0249
0250     /* store boot voltage level */
0251     if (!tegra->cpu_min_uV)
0252         tegra->cpu_min_uV = cpu_uV;
0253
0254     /*
0255      * CPU's regulator may not have any consumers, hence the voltage
0256      * must not be changed in that case because CPU simply won't
0257      * survive the voltage drop if it's running on a higher frequency.
0258      */
0259     if (!cpu_min_uV_consumers)
0260         cpu_min_uV = max(cpu_uV, cpu_min_uV);
0261
0262     /*
0263      * Bootloader shall set up voltages correctly, but if it
0264      * happens that there is a violation, then try to fix it
0265      * at first.
0266      */
0267     core_min_limited_uV = tegra30_core_cpu_limit(cpu_uV);
0268     if (core_min_limited_uV < 0)
0269         return core_min_limited_uV;
0270
0271     core_min_uV = max(core_min_uV, tegra30_core_cpu_limit(cpu_min_uV));
0272
0273     err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV);
0274     if (err)
0275         return err;
0276
0277     /* restore boot voltage level */
0278     if (tegra->sys_reboot_mode)
0279         cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV);
0280
0281     /* prepare voltage level for suspend */
0282     if (tegra->sys_suspend_mode)
0283         cpu_min_uV = clamp(tegra30_cpu_nominal_uV(),
0284                    cpu_min_uV, cpu_max_uV);
0285
0286     if (core_min_limited_uV > core_uV) {
0287         pr_err("core voltage constraint violated: %d %d %d\n",
0288                core_uV, core_min_limited_uV, cpu_uV);
0289         goto update_core;
0290     }
0291
0292     while (cpu_uV != cpu_min_uV || core_uV != core_min_uV) {
0293         if (cpu_uV < cpu_min_uV) {
0294             cpu_target_uV = min(cpu_uV + cpu_max_step, cpu_min_uV);
0295         } else {
0296             cpu_target_uV = max(cpu_uV - cpu_max_step, cpu_min_uV);
0297             cpu_target_uV = max(core_uV - max_spread, cpu_target_uV);
0298         }
0299
0300         if (cpu_uV == cpu_target_uV)
0301             goto update_core;
0302
0303         err = regulator_set_voltage_rdev(cpu_rdev,
0304                          cpu_target_uV,
0305                          cpu_max_uV,
0306                          PM_SUSPEND_ON);
0307         if (err)
0308             return err;
0309
0310         cpu_uV = cpu_target_uV;
0311 update_core:
0312         core_min_limited_uV = tegra30_core_cpu_limit(cpu_uV);
0313         if (core_min_limited_uV < 0)
0314             return core_min_limited_uV;
0315
0316         core_target_uV = max(core_min_limited_uV, core_min_uV);
0317
0318         if (core_uV < core_target_uV) {
0319             core_target_uV = min(core_target_uV, core_uV + core_max_step);
0320             core_target_uV = min(core_target_uV, cpu_uV + max_spread);
0321         } else {
0322             core_target_uV = max(core_target_uV, core_uV - core_max_step);
0323         }
0324
0325         if (core_uV == core_target_uV)
0326             continue;
0327
0328         err = regulator_set_voltage_rdev(core_rdev,
0329                          core_target_uV,
0330                          core_max_uV,
0331                          PM_SUSPEND_ON);
0332         if (err)
0333             return err;
0334
0335         core_uV = core_target_uV;
0336     }
0337
0338     return 0;
0339 }
0340
0341 static int tegra30_regulator_balance_voltage(struct regulator_coupler *coupler,
0342                          struct regulator_dev *rdev,
0343                          suspend_state_t state)
0344 {
0345     struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
0346     struct regulator_dev *core_rdev = tegra->core_rdev;
0347     struct regulator_dev *cpu_rdev = tegra->cpu_rdev;
0348
0349     if ((core_rdev != rdev && cpu_rdev != rdev) || state != PM_SUSPEND_ON) {
0350         pr_err("regulators are not coupled properly\n");
0351         return -EINVAL;
0352     }
0353
0354     tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req);
0355     tegra->sys_suspend_mode = READ_ONCE(tegra->sys_suspend_mode_req);
0356
0357     return tegra30_voltage_update(tegra, cpu_rdev, core_rdev);
0358 }
0359
0360 static int tegra30_regulator_prepare_suspend(struct tegra_regulator_coupler *tegra,
0361                          bool sys_suspend_mode)
0362 {
0363     int err;
0364
0365     if (!tegra->core_rdev || !tegra->cpu_rdev)
0366         return 0;
0367
0368     /*
0369      * All power domains are enabled early during resume from suspend
0370      * by GENPD core.  Domains like VENC may require a higher voltage
0371      * when enabled during resume from suspend.  This also prepares
0372      * hardware for resuming from LP0.
0373      */
0374
0375     WRITE_ONCE(tegra->sys_suspend_mode_req, sys_suspend_mode);
0376
0377     err = regulator_sync_voltage_rdev(tegra->cpu_rdev);
0378     if (err)
0379         return err;
0380
0381     err = regulator_sync_voltage_rdev(tegra->core_rdev);
0382     if (err)
0383         return err;
0384
0385     return 0;
0386 }
0387
0388 static int tegra30_regulator_suspend(struct notifier_block *notifier,
0389                      unsigned long mode, void *arg)
0390 {
0391     struct tegra_regulator_coupler *tegra;
0392     int ret = 0;
0393
0394     tegra = container_of(notifier, struct tegra_regulator_coupler,
0395                  suspend_notifier);
0396
0397     switch (mode) {
0398     case PM_HIBERNATION_PREPARE:
0399     case PM_RESTORE_PREPARE:
0400     case PM_SUSPEND_PREPARE:
0401         ret = tegra30_regulator_prepare_suspend(tegra, true);
0402         break;
0403
0404     case PM_POST_HIBERNATION:
0405     case PM_POST_RESTORE:
0406     case PM_POST_SUSPEND:
0407         ret = tegra30_regulator_prepare_suspend(tegra, false);
0408         break;
0409     }
0410
0411     if (ret)
0412         pr_err("failed to prepare regulators: %d\n", ret);
0413
0414     return notifier_from_errno(ret);
0415 }
0416
0417 static int tegra30_regulator_prepare_reboot(struct tegra_regulator_coupler *tegra,
0418                         bool sys_reboot_mode)
0419 {
0420     int err;
0421
0422     if (!tegra->core_rdev || !tegra->cpu_rdev)
0423         return 0;
0424
0425     WRITE_ONCE(tegra->sys_reboot_mode_req, true);
0426
0427     /*
0428      * Some devices use CPU soft-reboot method and in this case we
0429      * should ensure that voltages are sane for the reboot by restoring
0430      * the minimum boot levels.
0431      */
0432     err = regulator_sync_voltage_rdev(tegra->cpu_rdev);
0433     if (err)
0434         return err;
0435
0436     err = regulator_sync_voltage_rdev(tegra->core_rdev);
0437     if (err)
0438         return err;
0439
0440     WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode);
0441
0442     return 0;
0443 }
0444
0445 static int tegra30_regulator_reboot(struct notifier_block *notifier,
0446                     unsigned long event, void *cmd)
0447 {
0448     struct tegra_regulator_coupler *tegra;
0449     int ret;
0450
0451     if (event != SYS_RESTART)
0452         return NOTIFY_DONE;
0453
0454     tegra = container_of(notifier, struct tegra_regulator_coupler,
0455                  reboot_notifier);
0456
0457     ret = tegra30_regulator_prepare_reboot(tegra, true);
0458
0459     return notifier_from_errno(ret);
0460 }
0461
0462 static int tegra30_regulator_attach(struct regulator_coupler *coupler,
0463                     struct regulator_dev *rdev)
0464 {
0465     struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
0466     struct device_node *np = rdev->dev.of_node;
0467
0468     if (of_property_read_bool(np, "nvidia,tegra-core-regulator") &&
0469         !tegra->core_rdev) {
0470         tegra->core_rdev = rdev;
0471         return 0;
0472     }
0473
0474     if (of_property_read_bool(np, "nvidia,tegra-cpu-regulator") &&
0475         !tegra->cpu_rdev) {
0476         tegra->cpu_rdev = rdev;
0477         return 0;
0478     }
0479
0480     return -EINVAL;
0481 }
0482
0483 static int tegra30_regulator_detach(struct regulator_coupler *coupler,
0484                     struct regulator_dev *rdev)
0485 {
0486     struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
0487
0488     /*
0489      * We don't expect regulators to be decoupled during reboot,
0490      * this may race with the reboot handler and shouldn't ever
0491      * happen in practice.
0492      */
0493     if (WARN_ON_ONCE(system_state > SYSTEM_RUNNING))
0494         return -EPERM;
0495
0496     if (tegra->core_rdev == rdev) {
0497         tegra->core_rdev = NULL;
0498         return 0;
0499     }
0500
0501     if (tegra->cpu_rdev == rdev) {
0502         tegra->cpu_rdev = NULL;
0503         return 0;
0504     }
0505
0506     return -EINVAL;
0507 }
0508
0509 static struct tegra_regulator_coupler tegra30_coupler = {
0510     .coupler = {
0511         .attach_regulator = tegra30_regulator_attach,
0512         .detach_regulator = tegra30_regulator_detach,
0513         .balance_voltage = tegra30_regulator_balance_voltage,
0514     },
0515     .reboot_notifier.notifier_call = tegra30_regulator_reboot,
0516     .suspend_notifier.notifier_call = tegra30_regulator_suspend,
0517 };
0518
0519 static int __init tegra_regulator_coupler_init(void)
0520 {
0521     int err;
0522
0523     if (!of_machine_is_compatible("nvidia,tegra30"))
0524         return 0;
0525
0526     err = register_reboot_notifier(&tegra30_coupler.reboot_notifier);
0527     WARN_ON(err);
0528
0529     err = register_pm_notifier(&tegra30_coupler.suspend_notifier);
0530     WARN_ON(err);
0531
0532     return regulator_coupler_register(&tegra30_coupler.coupler);
0533 }
0534 arch_initcall(tegra_regulator_coupler_init);