tegra/fuse/speedo-tegra210.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013-2015, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #include <linux/device.h>
0007 #include <linux/kernel.h>
0008 #include <linux/bug.h>
0009
0010 #include <soc/tegra/fuse.h>
0011
0012 #include "fuse.h"
0013
0014 #define CPU_PROCESS_CORNERS 2
0015 #define GPU_PROCESS_CORNERS 2
0016 #define SOC_PROCESS_CORNERS 3
0017
0018 #define FUSE_CPU_SPEEDO_0   0x014
0019 #define FUSE_CPU_SPEEDO_1   0x02c
0020 #define FUSE_CPU_SPEEDO_2   0x030
0021 #define FUSE_SOC_SPEEDO_0   0x034
0022 #define FUSE_SOC_SPEEDO_1   0x038
0023 #define FUSE_SOC_SPEEDO_2   0x03c
0024 #define FUSE_CPU_IDDQ       0x018
0025 #define FUSE_SOC_IDDQ       0x040
0026 #define FUSE_GPU_IDDQ       0x128
0027 #define FUSE_FT_REV     0x028
0028
0029 enum {
0030     THRESHOLD_INDEX_0,
0031     THRESHOLD_INDEX_1,
0032     THRESHOLD_INDEX_COUNT,
0033 };
0034
0035 static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
0036     { 2119, UINT_MAX },
0037     { 2119, UINT_MAX },
0038 };
0039
0040 static const u32 __initconst gpu_process_speedos[][GPU_PROCESS_CORNERS] = {
0041     { UINT_MAX, UINT_MAX },
0042     { UINT_MAX, UINT_MAX },
0043 };
0044
0045 static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
0046     { 1950, 2100, UINT_MAX },
0047     { 1950, 2100, UINT_MAX },
0048 };
0049
0050 static u8 __init get_speedo_revision(void)
0051 {
0052     return tegra_fuse_read_spare(4) << 2 |
0053            tegra_fuse_read_spare(3) << 1 |
0054            tegra_fuse_read_spare(2) << 0;
0055 }
0056
0057 static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
0058                      u8 speedo_rev, int *threshold)
0059 {
0060     int sku = sku_info->sku_id;
0061
0062     /* Assign to default */
0063     sku_info->cpu_speedo_id = 0;
0064     sku_info->soc_speedo_id = 0;
0065     sku_info->gpu_speedo_id = 0;
0066     *threshold = THRESHOLD_INDEX_0;
0067
0068     switch (sku) {
0069     case 0x00: /* Engineering SKU */
0070     case 0x01: /* Engineering SKU */
0071     case 0x07:
0072     case 0x17:
0073     case 0x27:
0074         if (speedo_rev >= 2)
0075             sku_info->gpu_speedo_id = 1;
0076         break;
0077
0078     case 0x13:
0079         if (speedo_rev >= 2)
0080             sku_info->gpu_speedo_id = 1;
0081
0082         sku_info->cpu_speedo_id = 1;
0083         break;
0084
0085     default:
0086         pr_err("Tegra210: unknown SKU %#04x\n", sku);
0087         /* Using the default for the error case */
0088         break;
0089     }
0090 }
0091
0092 static int get_process_id(int value, const u32 *speedos, unsigned int num)
0093 {
0094     unsigned int i;
0095
0096     for (i = 0; i < num; i++)
0097         if (value < speedos[i])
0098             return i;
0099
0100     return -EINVAL;
0101 }
0102
0103 void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
0104 {
0105     int cpu_speedo[3], soc_speedo[3];
0106     unsigned int index;
0107     u8 speedo_revision;
0108
0109     BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
0110             THRESHOLD_INDEX_COUNT);
0111     BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
0112             THRESHOLD_INDEX_COUNT);
0113     BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
0114             THRESHOLD_INDEX_COUNT);
0115
0116     /* Read speedo/IDDQ fuses */
0117     cpu_speedo[0] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
0118     cpu_speedo[1] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1);
0119     cpu_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
0120
0121     soc_speedo[0] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
0122     soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1);
0123     soc_speedo[2] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_2);
0124
0125     /*
0126      * Determine CPU, GPU and SoC speedo values depending on speedo fusing
0127      * revision. Note that GPU speedo value is fused in CPU_SPEEDO_2.
0128      */
0129     speedo_revision = get_speedo_revision();
0130     pr_info("Speedo Revision %u\n", speedo_revision);
0131
0132     if (speedo_revision >= 3) {
0133         sku_info->cpu_speedo_value = cpu_speedo[0];
0134         sku_info->gpu_speedo_value = cpu_speedo[2];
0135         sku_info->soc_speedo_value = soc_speedo[0];
0136     } else if (speedo_revision == 2) {
0137         sku_info->cpu_speedo_value = (-1938 + (1095 * cpu_speedo[0] / 100)) / 10;
0138         sku_info->gpu_speedo_value = (-1662 + (1082 * cpu_speedo[2] / 100)) / 10;
0139         sku_info->soc_speedo_value = ( -705 + (1037 * soc_speedo[0] / 100)) / 10;
0140     } else {
0141         sku_info->cpu_speedo_value = 2100;
0142         sku_info->gpu_speedo_value = cpu_speedo[2] - 75;
0143         sku_info->soc_speedo_value = 1900;
0144     }
0145
0146     if ((sku_info->cpu_speedo_value <= 0) ||
0147         (sku_info->gpu_speedo_value <= 0) ||
0148         (sku_info->soc_speedo_value <= 0)) {
0149         WARN(1, "speedo value not fused\n");
0150         return;
0151     }
0152
0153     rev_sku_to_speedo_ids(sku_info, speedo_revision, &index);
0154
0155     sku_info->gpu_process_id = get_process_id(sku_info->gpu_speedo_value,
0156                           gpu_process_speedos[index],
0157                           GPU_PROCESS_CORNERS);
0158
0159     sku_info->cpu_process_id = get_process_id(sku_info->cpu_speedo_value,
0160                           cpu_process_speedos[index],
0161                           CPU_PROCESS_CORNERS);
0162
0163     sku_info->soc_process_id = get_process_id(sku_info->soc_speedo_value,
0164                           soc_process_speedos[index],
0165                           SOC_PROCESS_CORNERS);
0166
0167     pr_debug("Tegra GPU Speedo ID=%d, Speedo Value=%d\n",
0168          sku_info->gpu_speedo_id, sku_info->gpu_speedo_value);
0169 }