tegra/fuse/speedo-tegra114.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #include <linux/bug.h>
0007 #include <linux/device.h>
0008 #include <linux/kernel.h>
0009
0010 #include <soc/tegra/fuse.h>
0011
0012 #include "fuse.h"
0013
0014 #define SOC_PROCESS_CORNERS 2
0015 #define CPU_PROCESS_CORNERS 2
0016
0017 enum {
0018     THRESHOLD_INDEX_0,
0019     THRESHOLD_INDEX_1,
0020     THRESHOLD_INDEX_COUNT,
0021 };
0022
0023 static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
0024     {1123,     UINT_MAX},
0025     {0,        UINT_MAX},
0026 };
0027
0028 static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
0029     {1695,     UINT_MAX},
0030     {0,        UINT_MAX},
0031 };
0032
0033 static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
0034                      int *threshold)
0035 {
0036     u32 tmp;
0037     u32 sku = sku_info->sku_id;
0038     enum tegra_revision rev = sku_info->revision;
0039
0040     switch (sku) {
0041     case 0x00:
0042     case 0x10:
0043     case 0x05:
0044     case 0x06:
0045         sku_info->cpu_speedo_id = 1;
0046         sku_info->soc_speedo_id = 0;
0047         *threshold = THRESHOLD_INDEX_0;
0048         break;
0049
0050     case 0x03:
0051     case 0x04:
0052         sku_info->cpu_speedo_id = 2;
0053         sku_info->soc_speedo_id = 1;
0054         *threshold = THRESHOLD_INDEX_1;
0055         break;
0056
0057     default:
0058         pr_err("Tegra Unknown SKU %d\n", sku);
0059         sku_info->cpu_speedo_id = 0;
0060         sku_info->soc_speedo_id = 0;
0061         *threshold = THRESHOLD_INDEX_0;
0062         break;
0063     }
0064
0065     if (rev == TEGRA_REVISION_A01) {
0066         tmp = tegra_fuse_read_early(0x270) << 1;
0067         tmp |= tegra_fuse_read_early(0x26c);
0068         if (!tmp)
0069             sku_info->cpu_speedo_id = 0;
0070     }
0071 }
0072
0073 void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
0074 {
0075     u32 cpu_speedo_val;
0076     u32 soc_speedo_val;
0077     int threshold;
0078     int i;
0079
0080     BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
0081             THRESHOLD_INDEX_COUNT);
0082     BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
0083             THRESHOLD_INDEX_COUNT);
0084
0085     rev_sku_to_speedo_ids(sku_info, &threshold);
0086
0087     cpu_speedo_val = tegra_fuse_read_early(0x12c) + 1024;
0088     soc_speedo_val = tegra_fuse_read_early(0x134);
0089
0090     for (i = 0; i < CPU_PROCESS_CORNERS; i++)
0091         if (cpu_speedo_val < cpu_process_speedos[threshold][i])
0092             break;
0093     sku_info->cpu_process_id = i;
0094
0095     for (i = 0; i < SOC_PROCESS_CORNERS; i++)
0096         if (soc_speedo_val < soc_process_speedos[threshold][i])
0097             break;
0098     sku_info->soc_process_id = i;
0099 }