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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2013-2022, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/device.h>
0008 #include <linux/kobject.h>
0009 #include <linux/init.h>
0010 #include <linux/io.h>
0011 #include <linux/nvmem-consumer.h>
0012 #include <linux/nvmem-provider.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/reset.h>
0018 #include <linux/slab.h>
0019 #include <linux/sys_soc.h>
0020 
0021 #include <soc/tegra/common.h>
0022 #include <soc/tegra/fuse.h>
0023 
0024 #include "fuse.h"
0025 
0026 struct tegra_sku_info tegra_sku_info;
0027 EXPORT_SYMBOL(tegra_sku_info);
0028 
0029 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
0030     [TEGRA_REVISION_UNKNOWN] = "unknown",
0031     [TEGRA_REVISION_A01]     = "A01",
0032     [TEGRA_REVISION_A02]     = "A02",
0033     [TEGRA_REVISION_A03]     = "A03",
0034     [TEGRA_REVISION_A03p]    = "A03 prime",
0035     [TEGRA_REVISION_A04]     = "A04",
0036 };
0037 
0038 static const struct of_device_id car_match[] __initconst = {
0039     { .compatible = "nvidia,tegra20-car", },
0040     { .compatible = "nvidia,tegra30-car", },
0041     { .compatible = "nvidia,tegra114-car", },
0042     { .compatible = "nvidia,tegra124-car", },
0043     { .compatible = "nvidia,tegra132-car", },
0044     { .compatible = "nvidia,tegra210-car", },
0045     {},
0046 };
0047 
0048 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
0049     .base = NULL,
0050     .soc = NULL,
0051 };
0052 
0053 static const struct of_device_id tegra_fuse_match[] = {
0054 #ifdef CONFIG_ARCH_TEGRA_234_SOC
0055     { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
0056 #endif
0057 #ifdef CONFIG_ARCH_TEGRA_194_SOC
0058     { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
0059 #endif
0060 #ifdef CONFIG_ARCH_TEGRA_186_SOC
0061     { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
0062 #endif
0063 #ifdef CONFIG_ARCH_TEGRA_210_SOC
0064     { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
0065 #endif
0066 #ifdef CONFIG_ARCH_TEGRA_132_SOC
0067     { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
0068 #endif
0069 #ifdef CONFIG_ARCH_TEGRA_124_SOC
0070     { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
0071 #endif
0072 #ifdef CONFIG_ARCH_TEGRA_114_SOC
0073     { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
0074 #endif
0075 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
0076     { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
0077 #endif
0078 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
0079     { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
0080 #endif
0081     { /* sentinel */ }
0082 };
0083 
0084 static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
0085                size_t bytes)
0086 {
0087     unsigned int count = bytes / 4, i;
0088     struct tegra_fuse *fuse = priv;
0089     u32 *buffer = value;
0090 
0091     for (i = 0; i < count; i++)
0092         buffer[i] = fuse->read(fuse, offset + i * 4);
0093 
0094     return 0;
0095 }
0096 
0097 static const struct nvmem_cell_info tegra_fuse_cells[] = {
0098     {
0099         .name = "tsensor-cpu1",
0100         .offset = 0x084,
0101         .bytes = 4,
0102         .bit_offset = 0,
0103         .nbits = 32,
0104     }, {
0105         .name = "tsensor-cpu2",
0106         .offset = 0x088,
0107         .bytes = 4,
0108         .bit_offset = 0,
0109         .nbits = 32,
0110     }, {
0111         .name = "tsensor-cpu0",
0112         .offset = 0x098,
0113         .bytes = 4,
0114         .bit_offset = 0,
0115         .nbits = 32,
0116     }, {
0117         .name = "xusb-pad-calibration",
0118         .offset = 0x0f0,
0119         .bytes = 4,
0120         .bit_offset = 0,
0121         .nbits = 32,
0122     }, {
0123         .name = "tsensor-cpu3",
0124         .offset = 0x12c,
0125         .bytes = 4,
0126         .bit_offset = 0,
0127         .nbits = 32,
0128     }, {
0129         .name = "sata-calibration",
0130         .offset = 0x124,
0131         .bytes = 1,
0132         .bit_offset = 0,
0133         .nbits = 2,
0134     }, {
0135         .name = "tsensor-gpu",
0136         .offset = 0x154,
0137         .bytes = 4,
0138         .bit_offset = 0,
0139         .nbits = 32,
0140     }, {
0141         .name = "tsensor-mem0",
0142         .offset = 0x158,
0143         .bytes = 4,
0144         .bit_offset = 0,
0145         .nbits = 32,
0146     }, {
0147         .name = "tsensor-mem1",
0148         .offset = 0x15c,
0149         .bytes = 4,
0150         .bit_offset = 0,
0151         .nbits = 32,
0152     }, {
0153         .name = "tsensor-pllx",
0154         .offset = 0x160,
0155         .bytes = 4,
0156         .bit_offset = 0,
0157         .nbits = 32,
0158     }, {
0159         .name = "tsensor-common",
0160         .offset = 0x180,
0161         .bytes = 4,
0162         .bit_offset = 0,
0163         .nbits = 32,
0164     }, {
0165         .name = "gpu-gcplex-config-fuse",
0166         .offset = 0x1c8,
0167         .bytes = 4,
0168         .bit_offset = 0,
0169         .nbits = 32,
0170     }, {
0171         .name = "tsensor-realignment",
0172         .offset = 0x1fc,
0173         .bytes = 4,
0174         .bit_offset = 0,
0175         .nbits = 32,
0176     }, {
0177         .name = "gpu-calibration",
0178         .offset = 0x204,
0179         .bytes = 4,
0180         .bit_offset = 0,
0181         .nbits = 32,
0182     }, {
0183         .name = "xusb-pad-calibration-ext",
0184         .offset = 0x250,
0185         .bytes = 4,
0186         .bit_offset = 0,
0187         .nbits = 32,
0188     }, {
0189         .name = "gpu-pdi0",
0190         .offset = 0x300,
0191         .bytes = 4,
0192         .bit_offset = 0,
0193         .nbits = 32,
0194     }, {
0195         .name = "gpu-pdi1",
0196         .offset = 0x304,
0197         .bytes = 4,
0198         .bit_offset = 0,
0199         .nbits = 32,
0200     },
0201 };
0202 
0203 static void tegra_fuse_restore(void *base)
0204 {
0205     fuse->base = (void __iomem *)base;
0206     fuse->clk = NULL;
0207 }
0208 
0209 static int tegra_fuse_probe(struct platform_device *pdev)
0210 {
0211     void __iomem *base = fuse->base;
0212     struct nvmem_config nvmem;
0213     struct resource *res;
0214     int err;
0215 
0216     err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base);
0217     if (err)
0218         return err;
0219 
0220     /* take over the memory region from the early initialization */
0221     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0222     fuse->phys = res->start;
0223     fuse->base = devm_ioremap_resource(&pdev->dev, res);
0224     if (IS_ERR(fuse->base)) {
0225         err = PTR_ERR(fuse->base);
0226         return err;
0227     }
0228 
0229     fuse->clk = devm_clk_get(&pdev->dev, "fuse");
0230     if (IS_ERR(fuse->clk)) {
0231         if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
0232             dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
0233                 PTR_ERR(fuse->clk));
0234 
0235         return PTR_ERR(fuse->clk);
0236     }
0237 
0238     platform_set_drvdata(pdev, fuse);
0239     fuse->dev = &pdev->dev;
0240 
0241     err = devm_pm_runtime_enable(&pdev->dev);
0242     if (err)
0243         return err;
0244 
0245     if (fuse->soc->probe) {
0246         err = fuse->soc->probe(fuse);
0247         if (err < 0)
0248             return err;
0249     }
0250 
0251     memset(&nvmem, 0, sizeof(nvmem));
0252     nvmem.dev = &pdev->dev;
0253     nvmem.name = "fuse";
0254     nvmem.id = -1;
0255     nvmem.owner = THIS_MODULE;
0256     nvmem.cells = tegra_fuse_cells;
0257     nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
0258     nvmem.type = NVMEM_TYPE_OTP;
0259     nvmem.read_only = true;
0260     nvmem.root_only = true;
0261     nvmem.reg_read = tegra_fuse_read;
0262     nvmem.size = fuse->soc->info->size;
0263     nvmem.word_size = 4;
0264     nvmem.stride = 4;
0265     nvmem.priv = fuse;
0266 
0267     fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
0268     if (IS_ERR(fuse->nvmem)) {
0269         err = PTR_ERR(fuse->nvmem);
0270         dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
0271             err);
0272         return err;
0273     }
0274 
0275     fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
0276     if (IS_ERR(fuse->rst)) {
0277         err = PTR_ERR(fuse->rst);
0278         dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n",
0279             fuse->rst);
0280         return err;
0281     }
0282 
0283     /*
0284      * FUSE clock is enabled at a boot time, hence this resume/suspend
0285      * disables the clock besides the h/w resetting.
0286      */
0287     err = pm_runtime_resume_and_get(&pdev->dev);
0288     if (err)
0289         return err;
0290 
0291     err = reset_control_reset(fuse->rst);
0292     pm_runtime_put(&pdev->dev);
0293 
0294     if (err < 0) {
0295         dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
0296         return err;
0297     }
0298 
0299     /* release the early I/O memory mapping */
0300     iounmap(base);
0301 
0302     return 0;
0303 }
0304 
0305 static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)
0306 {
0307     int err;
0308 
0309     err = clk_prepare_enable(fuse->clk);
0310     if (err < 0) {
0311         dev_err(dev, "failed to enable FUSE clock: %d\n", err);
0312         return err;
0313     }
0314 
0315     return 0;
0316 }
0317 
0318 static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev)
0319 {
0320     clk_disable_unprepare(fuse->clk);
0321 
0322     return 0;
0323 }
0324 
0325 static int __maybe_unused tegra_fuse_suspend(struct device *dev)
0326 {
0327     int ret;
0328 
0329     /*
0330      * Critical for RAM re-repair operation, which must occur on resume
0331      * from LP1 system suspend and as part of CCPLEX cluster switching.
0332      */
0333     if (fuse->soc->clk_suspend_on)
0334         ret = pm_runtime_resume_and_get(dev);
0335     else
0336         ret = pm_runtime_force_suspend(dev);
0337 
0338     return ret;
0339 }
0340 
0341 static int __maybe_unused tegra_fuse_resume(struct device *dev)
0342 {
0343     int ret = 0;
0344 
0345     if (fuse->soc->clk_suspend_on)
0346         pm_runtime_put(dev);
0347     else
0348         ret = pm_runtime_force_resume(dev);
0349 
0350     return ret;
0351 }
0352 
0353 static const struct dev_pm_ops tegra_fuse_pm = {
0354     SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume,
0355                NULL)
0356     SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume)
0357 };
0358 
0359 static struct platform_driver tegra_fuse_driver = {
0360     .driver = {
0361         .name = "tegra-fuse",
0362         .of_match_table = tegra_fuse_match,
0363         .pm = &tegra_fuse_pm,
0364         .suppress_bind_attrs = true,
0365     },
0366     .probe = tegra_fuse_probe,
0367 };
0368 builtin_platform_driver(tegra_fuse_driver);
0369 
0370 u32 __init tegra_fuse_read_spare(unsigned int spare)
0371 {
0372     unsigned int offset = fuse->soc->info->spare + spare * 4;
0373 
0374     return fuse->read_early(fuse, offset) & 1;
0375 }
0376 
0377 u32 __init tegra_fuse_read_early(unsigned int offset)
0378 {
0379     return fuse->read_early(fuse, offset);
0380 }
0381 
0382 int tegra_fuse_readl(unsigned long offset, u32 *value)
0383 {
0384     if (!fuse->read || !fuse->clk)
0385         return -EPROBE_DEFER;
0386 
0387     if (IS_ERR(fuse->clk))
0388         return PTR_ERR(fuse->clk);
0389 
0390     *value = fuse->read(fuse, offset);
0391 
0392     return 0;
0393 }
0394 EXPORT_SYMBOL(tegra_fuse_readl);
0395 
0396 static void tegra_enable_fuse_clk(void __iomem *base)
0397 {
0398     u32 reg;
0399 
0400     reg = readl_relaxed(base + 0x48);
0401     reg |= 1 << 28;
0402     writel(reg, base + 0x48);
0403 
0404     /*
0405      * Enable FUSE clock. This needs to be hardcoded because the clock
0406      * subsystem is not active during early boot.
0407      */
0408     reg = readl(base + 0x14);
0409     reg |= 1 << 7;
0410     writel(reg, base + 0x14);
0411 }
0412 
0413 static ssize_t major_show(struct device *dev, struct device_attribute *attr,
0414                  char *buf)
0415 {
0416     return sprintf(buf, "%d\n", tegra_get_major_rev());
0417 }
0418 
0419 static DEVICE_ATTR_RO(major);
0420 
0421 static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
0422                  char *buf)
0423 {
0424     return sprintf(buf, "%d\n", tegra_get_minor_rev());
0425 }
0426 
0427 static DEVICE_ATTR_RO(minor);
0428 
0429 static struct attribute *tegra_soc_attr[] = {
0430     &dev_attr_major.attr,
0431     &dev_attr_minor.attr,
0432     NULL,
0433 };
0434 
0435 const struct attribute_group tegra_soc_attr_group = {
0436     .attrs = tegra_soc_attr,
0437 };
0438 
0439 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
0440     IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
0441 static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
0442                  char *buf)
0443 {
0444     /*
0445      * Displays the value in the 'pre_si_platform' field of the HIDREV
0446      * register for Tegra194 devices. A value of 0 indicates that the
0447      * platform type is silicon and all other non-zero values indicate
0448      * the type of simulation platform is being used.
0449      */
0450     return sprintf(buf, "%d\n", tegra_get_platform());
0451 }
0452 
0453 static DEVICE_ATTR_RO(platform);
0454 
0455 static struct attribute *tegra194_soc_attr[] = {
0456     &dev_attr_major.attr,
0457     &dev_attr_minor.attr,
0458     &dev_attr_platform.attr,
0459     NULL,
0460 };
0461 
0462 const struct attribute_group tegra194_soc_attr_group = {
0463     .attrs = tegra194_soc_attr,
0464 };
0465 #endif
0466 
0467 struct device * __init tegra_soc_device_register(void)
0468 {
0469     struct soc_device_attribute *attr;
0470     struct soc_device *dev;
0471 
0472     attr = kzalloc(sizeof(*attr), GFP_KERNEL);
0473     if (!attr)
0474         return NULL;
0475 
0476     attr->family = kasprintf(GFP_KERNEL, "Tegra");
0477     attr->revision = kasprintf(GFP_KERNEL, "%s",
0478         tegra_revision_name[tegra_sku_info.revision]);
0479     attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
0480     attr->custom_attr_group = fuse->soc->soc_attr_group;
0481 
0482     dev = soc_device_register(attr);
0483     if (IS_ERR(dev)) {
0484         kfree(attr->soc_id);
0485         kfree(attr->revision);
0486         kfree(attr->family);
0487         kfree(attr);
0488         return ERR_CAST(dev);
0489     }
0490 
0491     return soc_device_to_device(dev);
0492 }
0493 
0494 static int __init tegra_init_fuse(void)
0495 {
0496     const struct of_device_id *match;
0497     struct device_node *np;
0498     struct resource regs;
0499 
0500     tegra_init_apbmisc();
0501 
0502     np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
0503     if (!np) {
0504         /*
0505          * Fall back to legacy initialization for 32-bit ARM only. All
0506          * 64-bit ARM device tree files for Tegra are required to have
0507          * a FUSE node.
0508          *
0509          * This is for backwards-compatibility with old device trees
0510          * that didn't contain a FUSE node.
0511          */
0512         if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
0513             u8 chip = tegra_get_chip_id();
0514 
0515             regs.start = 0x7000f800;
0516             regs.end = 0x7000fbff;
0517             regs.flags = IORESOURCE_MEM;
0518 
0519             switch (chip) {
0520 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
0521             case TEGRA20:
0522                 fuse->soc = &tegra20_fuse_soc;
0523                 break;
0524 #endif
0525 
0526 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
0527             case TEGRA30:
0528                 fuse->soc = &tegra30_fuse_soc;
0529                 break;
0530 #endif
0531 
0532 #ifdef CONFIG_ARCH_TEGRA_114_SOC
0533             case TEGRA114:
0534                 fuse->soc = &tegra114_fuse_soc;
0535                 break;
0536 #endif
0537 
0538 #ifdef CONFIG_ARCH_TEGRA_124_SOC
0539             case TEGRA124:
0540                 fuse->soc = &tegra124_fuse_soc;
0541                 break;
0542 #endif
0543 
0544             default:
0545                 pr_warn("Unsupported SoC: %02x\n", chip);
0546                 break;
0547             }
0548         } else {
0549             /*
0550              * At this point we're not running on Tegra, so play
0551              * nice with multi-platform kernels.
0552              */
0553             return 0;
0554         }
0555     } else {
0556         /*
0557          * Extract information from the device tree if we've found a
0558          * matching node.
0559          */
0560         if (of_address_to_resource(np, 0, &regs) < 0) {
0561             pr_err("failed to get FUSE register\n");
0562             return -ENXIO;
0563         }
0564 
0565         fuse->soc = match->data;
0566     }
0567 
0568     np = of_find_matching_node(NULL, car_match);
0569     if (np) {
0570         void __iomem *base = of_iomap(np, 0);
0571         if (base) {
0572             tegra_enable_fuse_clk(base);
0573             iounmap(base);
0574         } else {
0575             pr_err("failed to map clock registers\n");
0576             return -ENXIO;
0577         }
0578     }
0579 
0580     fuse->base = ioremap(regs.start, resource_size(&regs));
0581     if (!fuse->base) {
0582         pr_err("failed to map FUSE registers\n");
0583         return -ENXIO;
0584     }
0585 
0586     fuse->soc->init(fuse);
0587 
0588     pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
0589         tegra_revision_name[tegra_sku_info.revision],
0590         tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
0591         tegra_sku_info.soc_process_id);
0592     pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
0593          tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
0594 
0595     if (fuse->soc->lookups) {
0596         size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
0597 
0598         fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
0599         if (fuse->lookups)
0600             nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
0601     }
0602 
0603     return 0;
0604 }
0605 early_initcall(tegra_init_fuse);
0606 
0607 #ifdef CONFIG_ARM64
0608 static int __init tegra_init_soc(void)
0609 {
0610     struct device_node *np;
0611     struct device *soc;
0612 
0613     /* make sure we're running on Tegra */
0614     np = of_find_matching_node(NULL, tegra_fuse_match);
0615     if (!np)
0616         return 0;
0617 
0618     of_node_put(np);
0619 
0620     soc = tegra_soc_device_register();
0621     if (IS_ERR(soc)) {
0622         pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
0623         return PTR_ERR(soc);
0624     }
0625 
0626     return 0;
0627 }
0628 device_initcall(tegra_init_soc);
0629 #endif
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