soc/tegra/common.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #define dev_fmt(fmt)    "tegra-soc: " fmt
0007
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/export.h>
0011 #include <linux/of.h>
0012 #include <linux/pm_opp.h>
0013 #include <linux/pm_runtime.h>
0014
0015 #include <soc/tegra/common.h>
0016 #include <soc/tegra/fuse.h>
0017
0018 static const struct of_device_id tegra_machine_match[] = {
0019     { .compatible = "nvidia,tegra20", },
0020     { .compatible = "nvidia,tegra30", },
0021     { .compatible = "nvidia,tegra114", },
0022     { .compatible = "nvidia,tegra124", },
0023     { .compatible = "nvidia,tegra132", },
0024     { .compatible = "nvidia,tegra210", },
0025     { }
0026 };
0027
0028 bool soc_is_tegra(void)
0029 {
0030     const struct of_device_id *match;
0031     struct device_node *root;
0032
0033     root = of_find_node_by_path("/");
0034     if (!root)
0035         return false;
0036
0037     match = of_match_node(tegra_machine_match, root);
0038     of_node_put(root);
0039
0040     return match != NULL;
0041 }
0042
0043 static int tegra_core_dev_init_opp_state(struct device *dev)
0044 {
0045     unsigned long rate;
0046     struct clk *clk;
0047     bool rpm_enabled;
0048     int err;
0049
0050     clk = devm_clk_get(dev, NULL);
0051     if (IS_ERR(clk)) {
0052         dev_err(dev, "failed to get clk: %pe\n", clk);
0053         return PTR_ERR(clk);
0054     }
0055
0056     rate = clk_get_rate(clk);
0057     if (!rate) {
0058         dev_err(dev, "failed to get clk rate\n");
0059         return -EINVAL;
0060     }
0061
0062     /*
0063      * Runtime PM of the device must be enabled in order to set up
0064      * GENPD's performance properly because GENPD core checks whether
0065      * device is suspended and this check doesn't work while RPM is
0066      * disabled. This makes sure the OPP vote below gets cached in
0067      * GENPD for the device. Instead, the vote is done the next time
0068      * the device gets runtime resumed.
0069      */
0070     rpm_enabled = pm_runtime_enabled(dev);
0071     if (!rpm_enabled)
0072         pm_runtime_enable(dev);
0073
0074     /* should never happen in practice */
0075     if (!pm_runtime_enabled(dev)) {
0076         dev_WARN(dev, "failed to enable runtime PM\n");
0077         pm_runtime_disable(dev);
0078         return -EINVAL;
0079     }
0080
0081     /* first dummy rate-setting initializes voltage vote */
0082     err = dev_pm_opp_set_rate(dev, rate);
0083
0084     if (!rpm_enabled)
0085         pm_runtime_disable(dev);
0086
0087     if (err) {
0088         dev_err(dev, "failed to initialize OPP clock: %d\n", err);
0089         return err;
0090     }
0091
0092     return 0;
0093 }
0094
0095 /**
0096  * devm_tegra_core_dev_init_opp_table() - initialize OPP table
0097  * @dev: device for which OPP table is initialized
0098  * @params: pointer to the OPP table configuration
0099  *
0100  * This function will initialize OPP table and sync OPP state of a Tegra SoC
0101  * core device.
0102  *
0103  * Return: 0 on success or errorno.
0104  */
0105 int devm_tegra_core_dev_init_opp_table(struct device *dev,
0106                        struct tegra_core_opp_params *params)
0107 {
0108     u32 hw_version;
0109     int err;
0110     /*
0111      * The clk's connection id to set is NULL and this is a NULL terminated
0112      * array, hence two NULL entries.
0113      */
0114     const char *clk_names[] = { NULL, NULL };
0115     struct dev_pm_opp_config config = {
0116         /*
0117          * For some devices we don't have any OPP table in the DT, and
0118          * in order to use the same code path for all the devices, we
0119          * create a dummy OPP table for them via this. The dummy OPP
0120          * table is only capable of doing clk_set_rate() on invocation
0121          * of dev_pm_opp_set_rate() and doesn't provide any other
0122          * functionality.
0123          */
0124         .clk_names = clk_names,
0125     };
0126
0127     if (of_machine_is_compatible("nvidia,tegra20")) {
0128         hw_version = BIT(tegra_sku_info.soc_process_id);
0129         config.supported_hw = &hw_version;
0130         config.supported_hw_count = 1;
0131     } else if (of_machine_is_compatible("nvidia,tegra30")) {
0132         hw_version = BIT(tegra_sku_info.soc_speedo_id);
0133         config.supported_hw = &hw_version;
0134         config.supported_hw_count = 1;
0135     }
0136
0137     err = devm_pm_opp_set_config(dev, &config);
0138     if (err) {
0139         dev_err(dev, "failed to set OPP config: %d\n", err);
0140         return err;
0141     }
0142
0143     /*
0144      * Tegra114+ doesn't support OPP yet, return early for non tegra20/30
0145      * case.
0146      */
0147     if (!config.supported_hw)
0148         return -ENODEV;
0149
0150     /*
0151      * Older device-trees have an empty OPP table, we will get
0152      * -ENODEV from devm_pm_opp_of_add_table() in this case.
0153      */
0154     err = devm_pm_opp_of_add_table(dev);
0155     if (err) {
0156         if (err != -ENODEV)
0157             dev_err(dev, "failed to add OPP table: %d\n", err);
0158
0159         return err;
0160     }
0161
0162     if (params->init_state) {
0163         err = tegra_core_dev_init_opp_state(dev);
0164         if (err)
0165             return err;
0166     }
0167
0168     return 0;
0169 }
0170 EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table);