soc/samsung/exynos5250-pmu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
0004 //      http://www.samsung.com/
0005 //
0006 // Exynos5250 - CPU PMU (Power Management Unit) support
0007
0008 #include <linux/soc/samsung/exynos-regs-pmu.h>
0009 #include <linux/soc/samsung/exynos-pmu.h>
0010
0011 #include "exynos-pmu.h"
0012
0013 static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
0014     /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
0015     { EXYNOS5_ARM_CORE0_SYS_PWR_REG,        { 0x0, 0x0, 0x2} },
0016     { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
0017     { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
0018     { EXYNOS5_ARM_CORE1_SYS_PWR_REG,        { 0x0, 0x0, 0x2} },
0019     { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
0020     { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
0021     { EXYNOS5_FSYS_ARM_SYS_PWR_REG,         { 0x1, 0x0, 0x0} },
0022     { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
0023     { EXYNOS5_ISP_ARM_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
0024     { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },
0025     { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
0026     { EXYNOS5_ARM_COMMON_SYS_PWR_REG,       { 0x0, 0x0, 0x2} },
0027     { EXYNOS5_ARM_L2_SYS_PWR_REG,           { 0x3, 0x3, 0x3} },
0028     { EXYNOS_L2_OPTION(0),              { 0x10, 0x10, 0x0 } },
0029     { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },
0030     { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,     { 0x1, 0x0, 0x1} },
0031     { EXYNOS5_CMU_RESET_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0032     { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,  { 0x1, 0x0, 0x1} },
0033     { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,  { 0x1, 0x0, 0x1} },
0034     { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },
0035     { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },
0036     { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,        { 0x1, 0x1, 0x1} },
0037     { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },
0038     { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0039     { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0040     { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0041     { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
0042     { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0043     { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0044     { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0045     { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0046     { EXYNOS5_TOP_BUS_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },
0047     { EXYNOS5_TOP_RETENTION_SYS_PWR_REG,        { 0x1, 0x0, 0x1} },
0048     { EXYNOS5_TOP_PWR_SYS_PWR_REG,          { 0x3, 0x0, 0x3} },
0049     { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },
0050     { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
0051     { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,       { 0x3, 0x0, 0x3} },
0052     { EXYNOS5_LOGIC_RESET_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
0053     { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,      { 0x1, 0x0, 0x1} },
0054     { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0055     { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,   { 0x1, 0x0, 0x1} },
0056     { EXYNOS5_USBOTG_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },
0057     { EXYNOS5_G2D_MEM_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },
0058     { EXYNOS5_USBDRD_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },
0059     { EXYNOS5_SDMMC_MEM_SYS_PWR_REG,        { 0x3, 0x0, 0x0} },
0060     { EXYNOS5_CSSYS_MEM_SYS_PWR_REG,        { 0x3, 0x0, 0x0} },
0061     { EXYNOS5_SECSS_MEM_SYS_PWR_REG,        { 0x3, 0x0, 0x0} },
0062     { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG,      { 0x3, 0x0, 0x0} },
0063     { EXYNOS5_INTRAM_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },
0064     { EXYNOS5_INTROM_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },
0065     { EXYNOS5_JPEG_MEM_SYS_PWR_REG,         { 0x3, 0x0, 0x0} },
0066     { EXYNOS5_JPEG_MEM_OPTION,          { 0x10, 0x10, 0x0} },
0067     { EXYNOS5_HSI_MEM_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },
0068     { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG,       { 0x3, 0x0, 0x0} },
0069     { EXYNOS5_SATA_MEM_SYS_PWR_REG,         { 0x3, 0x0, 0x0} },
0070     { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0071     { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
0072     { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0073     { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0074     { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0075     { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0076     { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0077     { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0078     { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
0079     { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
0080     { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0081     { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
0082     { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0083     { EXYNOS5_XUSBXTI_SYS_PWR_REG,          { 0x1, 0x1, 0x1} },
0084     { EXYNOS5_XXTI_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
0085     { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0086     { EXYNOS5_GPIO_MODE_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0087     { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
0088     { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0089     { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,        { 0x1, 0x1, 0x1} },
0090     { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,    { 0x1, 0x0, 0x1} },
0091     { EXYNOS5_GSCL_SYS_PWR_REG,         { 0x7, 0x0, 0x0} },
0092     { EXYNOS5_ISP_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0093     { EXYNOS5_MFC_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0094     { EXYNOS5_G3D_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0095     { EXYNOS5_DISP1_SYS_PWR_REG,            { 0x7, 0x0, 0x0} },
0096     { EXYNOS5_MAU_SYS_PWR_REG,          { 0x7, 0x7, 0x0} },
0097     { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
0098     { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0099     { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0100     { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0101     { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG,    { 0x1, 0x0, 0x0} },
0102     { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
0103     { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0104     { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
0105     { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
0106     { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
0107     { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
0108     { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,       { 0x1, 0x1, 0x0} },
0109     { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
0110     { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0111     { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0112     { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0113     { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0114     { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0115     { PMU_TABLE_END,},
0116 };
0117
0118 static unsigned int const exynos5_list_both_cnt_feed[] = {
0119     EXYNOS5_ARM_CORE0_OPTION,
0120     EXYNOS5_ARM_CORE1_OPTION,
0121     EXYNOS5_ARM_COMMON_OPTION,
0122     EXYNOS5_GSCL_OPTION,
0123     EXYNOS5_ISP_OPTION,
0124     EXYNOS5_MFC_OPTION,
0125     EXYNOS5_G3D_OPTION,
0126     EXYNOS5_DISP1_OPTION,
0127     EXYNOS5_MAU_OPTION,
0128     EXYNOS5_TOP_PWR_OPTION,
0129     EXYNOS5_TOP_PWR_SYSMEM_OPTION,
0130 };
0131
0132 static unsigned int const exynos5_list_disable_wfi_wfe[] = {
0133     EXYNOS5_ARM_CORE1_OPTION,
0134     EXYNOS5_FSYS_ARM_OPTION,
0135     EXYNOS5_ISP_ARM_OPTION,
0136 };
0137
0138 static void exynos5250_pmu_init(void)
0139 {
0140     unsigned int value;
0141     /*
0142      * When SYS_WDTRESET is set, watchdog timer reset request
0143      * is ignored by power management unit.
0144      */
0145     value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
0146     value &= ~EXYNOS5_SYS_WDTRESET;
0147     pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
0148
0149     value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
0150     value &= ~EXYNOS5_SYS_WDTRESET;
0151     pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
0152 }
0153
0154 static void exynos5_powerdown_conf(enum sys_powerdown mode)
0155 {
0156     unsigned int i;
0157     unsigned int tmp;
0158
0159     /*
0160      * Enable both SC_FEEDBACK and SC_COUNTER
0161      */
0162     for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) {
0163         tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
0164         tmp |= (EXYNOS5_USE_SC_FEEDBACK |
0165             EXYNOS5_USE_SC_COUNTER);
0166         pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
0167     }
0168
0169     /*
0170      * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
0171      */
0172     tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
0173     tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
0174     pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
0175
0176     /*
0177      * Disable WFI/WFE on XXX_OPTION
0178      */
0179     for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) {
0180         tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]);
0181         tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
0182              EXYNOS5_OPTION_USE_STANDBYWFI);
0183         pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]);
0184     }
0185 }
0186
0187 const struct exynos_pmu_data exynos5250_pmu_data = {
0188     .pmu_config = exynos5250_pmu_config,
0189     .pmu_init   = exynos5250_pmu_init,
0190     .powerdown_conf = exynos5_powerdown_conf,
0191 };