soc/samsung/exynos3250-pmu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
0004 //      http://www.samsung.com/
0005 //
0006 // Exynos3250 - CPU PMU (Power Management Unit) support
0007
0008 #include <linux/soc/samsung/exynos-regs-pmu.h>
0009 #include <linux/soc/samsung/exynos-pmu.h>
0010
0011 #include "exynos-pmu.h"
0012
0013 static const struct exynos_pmu_conf exynos3250_pmu_config[] = {
0014     /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */
0015     { EXYNOS3_ARM_CORE0_SYS_PWR_REG,        { 0x0, 0x0, 0x2} },
0016     { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
0017     { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
0018     { EXYNOS3_ARM_CORE1_SYS_PWR_REG,        { 0x0, 0x0, 0x2} },
0019     { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
0020     { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
0021     { EXYNOS3_ISP_ARM_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
0022     { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,    { 0x0, 0x0, 0x0} },
0023     { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x0, 0x0, 0x0} },
0024     { EXYNOS3_ARM_COMMON_SYS_PWR_REG,       { 0x0, 0x0, 0x2} },
0025     { EXYNOS3_ARM_L2_SYS_PWR_REG,           { 0x0, 0x0, 0x3} },
0026     { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },
0027     { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },
0028     { EXYNOS3_CMU_RESET_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0029     { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG,       { 0x1, 0x1, 0x1} },
0030     { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG,        { 0x1, 0x1, 0x1} },
0031     { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG,   { 0x1, 0x1, 0x1} },
0032     { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
0033     { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
0034     { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
0035     { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0036     { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0037     { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0038     { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
0039     { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0040     { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG,      { 0x1, 0x1, 0x1} },
0041     { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0042     { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0043     { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0044     { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0045     { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0046     { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0047     { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
0048     { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG,      { 0x1, 0x0, 0x0} },
0049     { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,   { 0x1, 0x0, 0x0} },
0050     { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0051     { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0052     { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0053     { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
0054     { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG,        { 0x1, 0x0, 0x0} },
0055     { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG,     { 0x1, 0x0, 0x0} },
0056     { EXYNOS3_TOP_BUS_SYS_PWR_REG,          { 0x3, 0x0, 0x0} },
0057     { EXYNOS3_TOP_RETENTION_SYS_PWR_REG,        { 0x1, 0x1, 0x1} },
0058     { EXYNOS3_TOP_PWR_SYS_PWR_REG,          { 0x3, 0x3, 0x3} },
0059     { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG,      { 0x3, 0x0, 0x0} },
0060     { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x1} },
0061     { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG,      { 0x3, 0x3, 0x3} },
0062     { EXYNOS3_LOGIC_RESET_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
0063     { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG,      { 0x1, 0x1, 0x1} },
0064     { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG,  { 0x1, 0x1, 0x0} },
0065     { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG,  { 0x1, 0x0, 0x1} },
0066     { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0067     { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
0068     { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0069     { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0070     { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0071     { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0072     { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0073     { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
0074     { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0075     { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0076     { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG,   { 0x1, 0x1, 0x0} },
0077     { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0078     { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG,      { 0x1, 0x1, 0x0} },
0079     { EXYNOS3_XUSBXTI_SYS_PWR_REG,          { 0x1, 0x1, 0x0} },
0080     { EXYNOS3_XXTI_SYS_PWR_REG,         { 0x1, 0x1, 0x0} },
0081     { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0082     { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
0083     { EXYNOS3_GPIO_MODE_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0084     { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG,     { 0x1, 0x1, 0x0} },
0085     { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG,        { 0x1, 0x1, 0x0} },
0086     { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
0087     { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG,    { 0x1, 0x1, 0x0} },
0088     { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
0089     { EXYNOS3_CAM_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0090     { EXYNOS3_MFC_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0091     { EXYNOS3_G3D_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0092     { EXYNOS3_LCD0_SYS_PWR_REG,         { 0x7, 0x0, 0x0} },
0093     { EXYNOS3_ISP_SYS_PWR_REG,          { 0x7, 0x0, 0x0} },
0094     { EXYNOS3_MAUDIO_SYS_PWR_REG,           { 0x7, 0x0, 0x0} },
0095     { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG,       { 0x1, 0x0, 0x0} },
0096     { PMU_TABLE_END,},
0097 };
0098
0099 static unsigned int const exynos3250_list_feed[] = {
0100     EXYNOS3_ARM_CORE_OPTION(0),
0101     EXYNOS3_ARM_CORE_OPTION(1),
0102     EXYNOS3_ARM_CORE_OPTION(2),
0103     EXYNOS3_ARM_CORE_OPTION(3),
0104     EXYNOS3_ARM_COMMON_OPTION,
0105     EXYNOS3_TOP_PWR_OPTION,
0106     EXYNOS3_CORE_TOP_PWR_OPTION,
0107     S5P_CAM_OPTION,
0108     S5P_MFC_OPTION,
0109     S5P_G3D_OPTION,
0110     S5P_LCD0_OPTION,
0111     S5P_ISP_OPTION,
0112 };
0113
0114 static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode)
0115 {
0116     unsigned int i;
0117     unsigned int tmp;
0118
0119     /* Enable only SC_FEEDBACK */
0120     for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) {
0121         tmp = pmu_raw_readl(exynos3250_list_feed[i]);
0122         tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER);
0123         tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK;
0124         pmu_raw_writel(tmp, exynos3250_list_feed[i]);
0125     }
0126
0127     if (mode != SYS_SLEEP)
0128         return;
0129
0130     pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION);
0131     pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION);
0132     pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION);
0133     pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION,
0134                EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
0135 }
0136
0137 static void exynos3250_pmu_init(void)
0138 {
0139     unsigned int value;
0140
0141     /*
0142      * To prevent from issuing new bus request form L2 memory system
0143      * If core status is power down, should be set '1' to L2 power down
0144      */
0145     value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION);
0146     value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
0147     pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
0148
0149     /* Enable USE_STANDBY_WFI for all CORE */
0150     pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
0151
0152     /*
0153      * Set PSHOLD port for output high
0154      */
0155     value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
0156     value |= S5P_PS_HOLD_OUTPUT_HIGH;
0157     pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
0158
0159     /*
0160      * Enable signal for PSHOLD port
0161      */
0162     value = pmu_raw_readl(S5P_PS_HOLD_CONTROL);
0163     value |= S5P_PS_HOLD_EN;
0164     pmu_raw_writel(value, S5P_PS_HOLD_CONTROL);
0165 }
0166
0167 const struct exynos_pmu_data exynos3250_pmu_data = {
0168     .pmu_config = exynos3250_pmu_config,
0169     .pmu_init   = exynos3250_pmu_init,
0170     .powerdown_conf_extra   = exynos3250_powerdown_conf_extra,
0171 };