soc/renesas/rcar-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R-Car SYSC Power management support
0004  *
0005  * Copyright (C) 2014  Magnus Damm
0006  * Copyright (C) 2015-2017 Glider bvba
0007  */
0008
0009 #include <linux/clk/renesas.h>
0010 #include <linux/delay.h>
0011 #include <linux/err.h>
0012 #include <linux/mm.h>
0013 #include <linux/of_address.h>
0014 #include <linux/pm_domain.h>
0015 #include <linux/slab.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/io.h>
0018 #include <linux/iopoll.h>
0019 #include <linux/soc/renesas/rcar-sysc.h>
0020
0021 #include "rcar-sysc.h"
0022
0023 /* SYSC Common */
0024 #define SYSCSR          0x00    /* SYSC Status Register */
0025 #define SYSCISR         0x04    /* Interrupt Status Register */
0026 #define SYSCISCR        0x08    /* Interrupt Status Clear Register */
0027 #define SYSCIER         0x0c    /* Interrupt Enable Register */
0028 #define SYSCIMR         0x10    /* Interrupt Mask Register */
0029
0030 /* SYSC Status Register */
0031 #define SYSCSR_PONENB       1   /* Ready for power resume requests */
0032 #define SYSCSR_POFFENB      0   /* Ready for power shutoff requests */
0033
0034 /*
0035  * Power Control Register Offsets inside the register block for each domain
0036  * Note: The "CR" registers for ARM cores exist on H1 only
0037  *   Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
0038  *   Use PSCI on R-Car Gen3
0039  */
0040 #define PWRSR_OFFS      0x00    /* Power Status Register */
0041 #define PWROFFCR_OFFS       0x04    /* Power Shutoff Control Register */
0042 #define PWROFFSR_OFFS       0x08    /* Power Shutoff Status Register */
0043 #define PWRONCR_OFFS        0x0c    /* Power Resume Control Register */
0044 #define PWRONSR_OFFS        0x10    /* Power Resume Status Register */
0045 #define PWRER_OFFS      0x14    /* Power Shutoff/Resume Error */
0046
0047
0048 #define SYSCSR_TIMEOUT      100
0049 #define SYSCSR_DELAY_US     1
0050
0051 #define PWRER_RETRIES       100
0052 #define PWRER_DELAY_US      1
0053
0054 #define SYSCISR_TIMEOUT     1000
0055 #define SYSCISR_DELAY_US    1
0056
0057 #define RCAR_PD_ALWAYS_ON   32  /* Always-on power area */
0058
0059 struct rcar_sysc_ch {
0060     u16 chan_offs;
0061     u8 chan_bit;
0062     u8 isr_bit;
0063 };
0064
0065 static void __iomem *rcar_sysc_base;
0066 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
0067 static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
0068
0069 static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
0070 {
0071     unsigned int sr_bit, reg_offs;
0072     u32 val;
0073     int ret;
0074
0075     if (on) {
0076         sr_bit = SYSCSR_PONENB;
0077         reg_offs = PWRONCR_OFFS;
0078     } else {
0079         sr_bit = SYSCSR_POFFENB;
0080         reg_offs = PWROFFCR_OFFS;
0081     }
0082
0083     /* Wait until SYSC is ready to accept a power request */
0084     ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCSR, val,
0085                     val & BIT(sr_bit), SYSCSR_DELAY_US,
0086                     SYSCSR_TIMEOUT);
0087     if (ret)
0088         return -EAGAIN;
0089
0090     /* Submit power shutoff or power resume request */
0091     iowrite32(BIT(sysc_ch->chan_bit),
0092           rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
0093
0094     return 0;
0095 }
0096
0097 static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
0098 {
0099     unsigned int isr_mask = BIT(sysc_ch->isr_bit);
0100     unsigned int chan_mask = BIT(sysc_ch->chan_bit);
0101     unsigned int status, k;
0102     unsigned long flags;
0103     int ret;
0104
0105     spin_lock_irqsave(&rcar_sysc_lock, flags);
0106
0107     /*
0108      * Mask external power requests for CPU or 3DG domains
0109      */
0110     if (rcar_sysc_extmask_val) {
0111         iowrite32(rcar_sysc_extmask_val,
0112               rcar_sysc_base + rcar_sysc_extmask_offs);
0113     }
0114
0115     /*
0116      * The interrupt source needs to be enabled, but masked, to prevent the
0117      * CPU from receiving it.
0118      */
0119     iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
0120           rcar_sysc_base + SYSCIMR);
0121     iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
0122           rcar_sysc_base + SYSCIER);
0123
0124     iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
0125
0126     /* Submit power shutoff or resume request until it was accepted */
0127     for (k = 0; k < PWRER_RETRIES; k++) {
0128         ret = rcar_sysc_pwr_on_off(sysc_ch, on);
0129         if (ret)
0130             goto out;
0131
0132         status = ioread32(rcar_sysc_base +
0133                   sysc_ch->chan_offs + PWRER_OFFS);
0134         if (!(status & chan_mask))
0135             break;
0136
0137         udelay(PWRER_DELAY_US);
0138     }
0139
0140     if (k == PWRER_RETRIES) {
0141         ret = -EIO;
0142         goto out;
0143     }
0144
0145     /* Wait until the power shutoff or resume request has completed * */
0146     ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCISR, status,
0147                     status & isr_mask, SYSCISR_DELAY_US,
0148                     SYSCISR_TIMEOUT);
0149     if (ret)
0150         ret = -EIO;
0151
0152     iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
0153
0154  out:
0155     if (rcar_sysc_extmask_val)
0156         iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
0157
0158     spin_unlock_irqrestore(&rcar_sysc_lock, flags);
0159
0160     pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
0161          sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
0162     return ret;
0163 }
0164
0165 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
0166 {
0167     unsigned int st;
0168
0169     st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
0170     if (st & BIT(sysc_ch->chan_bit))
0171         return true;
0172
0173     return false;
0174 }
0175
0176 struct rcar_sysc_pd {
0177     struct generic_pm_domain genpd;
0178     struct rcar_sysc_ch ch;
0179     unsigned int flags;
0180     char name[];
0181 };
0182
0183 static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
0184 {
0185     return container_of(d, struct rcar_sysc_pd, genpd);
0186 }
0187
0188 static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
0189 {
0190     struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
0191
0192     pr_debug("%s: %s\n", __func__, genpd->name);
0193     return rcar_sysc_power(&pd->ch, false);
0194 }
0195
0196 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
0197 {
0198     struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
0199
0200     pr_debug("%s: %s\n", __func__, genpd->name);
0201     return rcar_sysc_power(&pd->ch, true);
0202 }
0203
0204 static bool has_cpg_mstp;
0205
0206 static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
0207 {
0208     struct generic_pm_domain *genpd = &pd->genpd;
0209     const char *name = pd->genpd.name;
0210     int error;
0211
0212     if (pd->flags & PD_CPU) {
0213         /*
0214          * This domain contains a CPU core and therefore it should
0215          * only be turned off if the CPU is not in use.
0216          */
0217         pr_debug("PM domain %s contains %s\n", name, "CPU");
0218         genpd->flags |= GENPD_FLAG_ALWAYS_ON;
0219     } else if (pd->flags & PD_SCU) {
0220         /*
0221          * This domain contains an SCU and cache-controller, and
0222          * therefore it should only be turned off if the CPU cores are
0223          * not in use.
0224          */
0225         pr_debug("PM domain %s contains %s\n", name, "SCU");
0226         genpd->flags |= GENPD_FLAG_ALWAYS_ON;
0227     } else if (pd->flags & PD_NO_CR) {
0228         /*
0229          * This domain cannot be turned off.
0230          */
0231         genpd->flags |= GENPD_FLAG_ALWAYS_ON;
0232     }
0233
0234     if (!(pd->flags & (PD_CPU | PD_SCU))) {
0235         /* Enable Clock Domain for I/O devices */
0236         genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
0237         if (has_cpg_mstp) {
0238             genpd->attach_dev = cpg_mstp_attach_dev;
0239             genpd->detach_dev = cpg_mstp_detach_dev;
0240         } else {
0241             genpd->attach_dev = cpg_mssr_attach_dev;
0242             genpd->detach_dev = cpg_mssr_detach_dev;
0243         }
0244     }
0245
0246     genpd->power_off = rcar_sysc_pd_power_off;
0247     genpd->power_on = rcar_sysc_pd_power_on;
0248
0249     if (pd->flags & (PD_CPU | PD_NO_CR)) {
0250         /* Skip CPUs (handled by SMP code) and areas without control */
0251         pr_debug("%s: Not touching %s\n", __func__, genpd->name);
0252         goto finalize;
0253     }
0254
0255     if (!rcar_sysc_power_is_off(&pd->ch)) {
0256         pr_debug("%s: %s is already powered\n", __func__, genpd->name);
0257         goto finalize;
0258     }
0259
0260     rcar_sysc_power(&pd->ch, true);
0261
0262 finalize:
0263     error = pm_genpd_init(genpd, &simple_qos_governor, false);
0264     if (error)
0265         pr_err("Failed to init PM domain %s: %d\n", name, error);
0266
0267     return error;
0268 }
0269
0270 static const struct of_device_id rcar_sysc_matches[] __initconst = {
0271 #ifdef CONFIG_SYSC_R8A7742
0272     { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
0273 #endif
0274 #ifdef CONFIG_SYSC_R8A7743
0275     { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
0276     /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
0277     { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
0278 #endif
0279 #ifdef CONFIG_SYSC_R8A7745
0280     { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
0281 #endif
0282 #ifdef CONFIG_SYSC_R8A77470
0283     { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
0284 #endif
0285 #ifdef CONFIG_SYSC_R8A774A1
0286     { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
0287 #endif
0288 #ifdef CONFIG_SYSC_R8A774B1
0289     { .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
0290 #endif
0291 #ifdef CONFIG_SYSC_R8A774C0
0292     { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
0293 #endif
0294 #ifdef CONFIG_SYSC_R8A774E1
0295     { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
0296 #endif
0297 #ifdef CONFIG_SYSC_R8A7779
0298     { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
0299 #endif
0300 #ifdef CONFIG_SYSC_R8A7790
0301     { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
0302 #endif
0303 #ifdef CONFIG_SYSC_R8A7791
0304     { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
0305     /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
0306     { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
0307 #endif
0308 #ifdef CONFIG_SYSC_R8A7792
0309     { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
0310 #endif
0311 #ifdef CONFIG_SYSC_R8A7794
0312     { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
0313 #endif
0314 #ifdef CONFIG_SYSC_R8A7795
0315     { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
0316 #endif
0317 #ifdef CONFIG_SYSC_R8A77960
0318     { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
0319 #endif
0320 #ifdef CONFIG_SYSC_R8A77961
0321     { .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
0322 #endif
0323 #ifdef CONFIG_SYSC_R8A77965
0324     { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
0325 #endif
0326 #ifdef CONFIG_SYSC_R8A77970
0327     { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
0328 #endif
0329 #ifdef CONFIG_SYSC_R8A77980
0330     { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
0331 #endif
0332 #ifdef CONFIG_SYSC_R8A77990
0333     { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
0334 #endif
0335 #ifdef CONFIG_SYSC_R8A77995
0336     { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
0337 #endif
0338     { /* sentinel */ }
0339 };
0340
0341 struct rcar_pm_domains {
0342     struct genpd_onecell_data onecell_data;
0343     struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
0344 };
0345
0346 static struct genpd_onecell_data *rcar_sysc_onecell_data;
0347
0348 static int __init rcar_sysc_pd_init(void)
0349 {
0350     const struct rcar_sysc_info *info;
0351     const struct of_device_id *match;
0352     struct rcar_pm_domains *domains;
0353     struct device_node *np;
0354     void __iomem *base;
0355     unsigned int i;
0356     int error;
0357
0358     np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
0359     if (!np)
0360         return -ENODEV;
0361
0362     info = match->data;
0363
0364     if (info->init) {
0365         error = info->init();
0366         if (error)
0367             goto out_put;
0368     }
0369
0370     has_cpg_mstp = of_find_compatible_node(NULL, NULL,
0371                            "renesas,cpg-mstp-clocks");
0372
0373     base = of_iomap(np, 0);
0374     if (!base) {
0375         pr_warn("%pOF: Cannot map regs\n", np);
0376         error = -ENOMEM;
0377         goto out_put;
0378     }
0379
0380     rcar_sysc_base = base;
0381
0382     /* Optional External Request Mask Register */
0383     rcar_sysc_extmask_offs = info->extmask_offs;
0384     rcar_sysc_extmask_val = info->extmask_val;
0385
0386     domains = kzalloc(sizeof(*domains), GFP_KERNEL);
0387     if (!domains) {
0388         error = -ENOMEM;
0389         goto out_put;
0390     }
0391
0392     domains->onecell_data.domains = domains->domains;
0393     domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
0394     rcar_sysc_onecell_data = &domains->onecell_data;
0395
0396     for (i = 0; i < info->num_areas; i++) {
0397         const struct rcar_sysc_area *area = &info->areas[i];
0398         struct rcar_sysc_pd *pd;
0399         size_t n;
0400
0401         if (!area->name) {
0402             /* Skip NULLified area */
0403             continue;
0404         }
0405
0406         n = strlen(area->name) + 1;
0407         pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL);
0408         if (!pd) {
0409             error = -ENOMEM;
0410             goto out_put;
0411         }
0412
0413         memcpy(pd->name, area->name, n);
0414         pd->genpd.name = pd->name;
0415         pd->ch.chan_offs = area->chan_offs;
0416         pd->ch.chan_bit = area->chan_bit;
0417         pd->ch.isr_bit = area->isr_bit;
0418         pd->flags = area->flags;
0419
0420         error = rcar_sysc_pd_setup(pd);
0421         if (error)
0422             goto out_put;
0423
0424         domains->domains[area->isr_bit] = &pd->genpd;
0425
0426         if (area->parent < 0)
0427             continue;
0428
0429         error = pm_genpd_add_subdomain(domains->domains[area->parent],
0430                            &pd->genpd);
0431         if (error) {
0432             pr_warn("Failed to add PM subdomain %s to parent %u\n",
0433                 area->name, area->parent);
0434             goto out_put;
0435         }
0436     }
0437
0438     error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
0439     if (!error)
0440         of_node_set_flag(np, OF_POPULATED);
0441
0442 out_put:
0443     of_node_put(np);
0444     return error;
0445 }
0446 early_initcall(rcar_sysc_pd_init);
0447
0448 void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
0449                   unsigned int num_areas, u8 id)
0450 {
0451     unsigned int i;
0452
0453     for (i = 0; i < num_areas; i++)
0454         if (areas[i].isr_bit == id) {
0455             areas[i].name = NULL;
0456             return;
0457         }
0458 }
0459
0460 #ifdef CONFIG_ARCH_R8A7779
0461 static int rcar_sysc_power_cpu(unsigned int idx, bool on)
0462 {
0463     struct generic_pm_domain *genpd;
0464     struct rcar_sysc_pd *pd;
0465     unsigned int i;
0466
0467     if (!rcar_sysc_onecell_data)
0468         return -ENODEV;
0469
0470     for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
0471         genpd = rcar_sysc_onecell_data->domains[i];
0472         if (!genpd)
0473             continue;
0474
0475         pd = to_rcar_pd(genpd);
0476         if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
0477             continue;
0478
0479         return rcar_sysc_power(&pd->ch, on);
0480     }
0481
0482     return -ENOENT;
0483 }
0484
0485 int rcar_sysc_power_down_cpu(unsigned int cpu)
0486 {
0487     return rcar_sysc_power_cpu(cpu, false);
0488 }
0489
0490 int rcar_sysc_power_up_cpu(unsigned int cpu)
0491 {
0492     return rcar_sysc_power_cpu(cpu, true);
0493 }
0494 #endif /* CONFIG_ARCH_R8A7779 */