soc/renesas/r9a06g032-smp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R9A06G032 Second CA7 enabler.
0004  *
0005  * Copyright (C) 2018 Renesas Electronics Europe Limited
0006  *
0007  * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
0008  * Derived from actions,s500-smp
0009  */
0010
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/smp.h>
0015
0016 /*
0017  * The second CPU is parked in ROM at boot time. It requires waking it after
0018  * writing an address into the BOOTADDR register of sysctrl.
0019  *
0020  * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
0021  *
0022  * *However* the BOOTADDR register is not available when the kernel
0023  * starts in NONSEC mode.
0024  *
0025  * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
0026  * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
0027  * which is not restricted.
0028  */
0029
0030 static void __iomem *cpu_bootaddr;
0031
0032 static DEFINE_SPINLOCK(cpu_lock);
0033
0034 static int
0035 r9a06g032_smp_boot_secondary(unsigned int cpu,
0036                  struct task_struct *idle)
0037 {
0038     if (!cpu_bootaddr)
0039         return -ENODEV;
0040
0041     spin_lock(&cpu_lock);
0042
0043     writel(__pa_symbol(secondary_startup), cpu_bootaddr);
0044     arch_send_wakeup_ipi_mask(cpumask_of(cpu));
0045
0046     spin_unlock(&cpu_lock);
0047
0048     return 0;
0049 }
0050
0051 static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
0052 {
0053     struct device_node *dn;
0054     int ret = -EINVAL, dns;
0055     u32 bootaddr;
0056
0057     dn = of_get_cpu_node(1, NULL);
0058     if (!dn) {
0059         pr_err("CPU#1: missing device tree node\n");
0060         return;
0061     }
0062     /*
0063      * Determine the address from which the CPU is polling.
0064      * The bootloader *does* change this property.
0065      * Note: The property can be either 64 or 32 bits, so handle both cases
0066      */
0067     if (of_find_property(dn, "cpu-release-addr", &dns)) {
0068         if (dns == sizeof(u64)) {
0069             u64 temp;
0070
0071             ret = of_property_read_u64(dn,
0072                            "cpu-release-addr", &temp);
0073             bootaddr = temp;
0074         } else {
0075             ret = of_property_read_u32(dn,
0076                            "cpu-release-addr",
0077                            &bootaddr);
0078         }
0079     }
0080     of_node_put(dn);
0081     if (ret) {
0082         pr_err("CPU#1: invalid cpu-release-addr property\n");
0083         return;
0084     }
0085     pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
0086
0087     cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
0088 }
0089
0090 static const struct smp_operations r9a06g032_smp_ops __initconst = {
0091     .smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
0092     .smp_boot_secondary = r9a06g032_smp_boot_secondary,
0093 };
0094
0095 CPU_METHOD_OF_DECLARE(r9a06g032_smp,
0096               "renesas,r9a06g032-smp", &r9a06g032_smp_ops);