soc/renesas/r8a779g0-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas R-Car V4H System Controller
0004  *
0005  * Copyright (C) 2022 Renesas Electronics Corp.
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/clk/renesas.h>
0010 #include <linux/delay.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mm.h>
0016 #include <linux/of_address.h>
0017 #include <linux/pm_domain.h>
0018 #include <linux/slab.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/types.h>
0021
0022 #include <dt-bindings/power/r8a779g0-sysc.h>
0023
0024 #include "rcar-gen4-sysc.h"
0025
0026 static struct rcar_gen4_sysc_area r8a779g0_areas[] __initdata = {
0027     { "always-on",  R8A779G0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
0028     { "a3e0",   R8A779G0_PD_A3E0, R8A779G0_PD_ALWAYS_ON, PD_SCU },
0029     { "a2e0d0", R8A779G0_PD_A2E0D0, R8A779G0_PD_A3E0, PD_SCU },
0030     { "a2e0d1", R8A779G0_PD_A2E0D1, R8A779G0_PD_A3E0, PD_SCU },
0031     { "a1e0d0c0",   R8A779G0_PD_A1E0D0C0, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
0032     { "a1e0d0c1",   R8A779G0_PD_A1E0D0C1, R8A779G0_PD_A2E0D0, PD_CPU_NOCR },
0033     { "a1e0d1c0",   R8A779G0_PD_A1E0D1C0, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
0034     { "a1e0d1c1",   R8A779G0_PD_A1E0D1C1, R8A779G0_PD_A2E0D1, PD_CPU_NOCR },
0035     { "a33dga", R8A779G0_PD_A33DGA, R8A779G0_PD_ALWAYS_ON },
0036     { "a23dgb", R8A779G0_PD_A23DGB, R8A779G0_PD_A33DGA },
0037     { "a3vip0", R8A779G0_PD_A3VIP0, R8A779G0_PD_ALWAYS_ON },
0038     { "a3vip1", R8A779G0_PD_A3VIP1, R8A779G0_PD_ALWAYS_ON },
0039     { "a3vip2", R8A779G0_PD_A3VIP2, R8A779G0_PD_ALWAYS_ON },
0040     { "a3isp0", R8A779G0_PD_A3ISP0, R8A779G0_PD_ALWAYS_ON },
0041     { "a3isp1", R8A779G0_PD_A3ISP1, R8A779G0_PD_ALWAYS_ON },
0042     { "a3ir",   R8A779G0_PD_A3IR, R8A779G0_PD_ALWAYS_ON },
0043     { "a2cn0",  R8A779G0_PD_A2CN0, R8A779G0_PD_A3IR },
0044     { "a1cnn0", R8A779G0_PD_A1CNN0, R8A779G0_PD_A2CN0 },
0045     { "a1dsp0", R8A779G0_PD_A1DSP0, R8A779G0_PD_A2CN0 },
0046     { "a1dsp1", R8A779G0_PD_A1DSP1, R8A779G0_PD_A2CN0 },
0047     { "a1dsp2", R8A779G0_PD_A1DSP2, R8A779G0_PD_A2CN0 },
0048     { "a1dsp3", R8A779G0_PD_A1DSP3, R8A779G0_PD_A2CN0 },
0049     { "a2imp01",    R8A779G0_PD_A2IMP01, R8A779G0_PD_A3IR },
0050     { "a2imp23",    R8A779G0_PD_A2IMP23, R8A779G0_PD_A3IR },
0051     { "a2psc",  R8A779G0_PD_A2PSC, R8A779G0_PD_A3IR },
0052     { "a2dma",  R8A779G0_PD_A2DMA, R8A779G0_PD_A3IR },
0053     { "a2cv0",  R8A779G0_PD_A2CV0, R8A779G0_PD_A3IR },
0054     { "a2cv1",  R8A779G0_PD_A2CV1, R8A779G0_PD_A3IR },
0055     { "a2cv2",  R8A779G0_PD_A2CV2, R8A779G0_PD_A3IR },
0056     { "a2cv3",  R8A779G0_PD_A2CV3, R8A779G0_PD_A3IR },
0057 };
0058
0059 const struct rcar_gen4_sysc_info r8a779g0_sysc_info __initconst = {
0060     .areas = r8a779g0_areas,
0061     .num_areas = ARRAY_SIZE(r8a779g0_areas),
0062 };