soc/renesas/r8a779a0-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas R-Car V3U System Controller
0004  *
0005  * Copyright (C) 2020 Renesas Electronics Corp.
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/clk/renesas.h>
0010 #include <linux/delay.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mm.h>
0016 #include <linux/of_address.h>
0017 #include <linux/pm_domain.h>
0018 #include <linux/slab.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/types.h>
0021
0022 #include <dt-bindings/power/r8a779a0-sysc.h>
0023
0024 #include "rcar-gen4-sysc.h"
0025
0026 static struct rcar_gen4_sysc_area r8a779a0_areas[] __initdata = {
0027     { "always-on",  R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
0028     { "a3e0",   R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
0029     { "a3e1",   R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
0030     { "a2e0d0", R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
0031     { "a2e0d1", R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
0032     { "a2e1d0", R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
0033     { "a2e1d1", R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
0034     { "a1e0d0c0",   R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
0035     { "a1e0d0c1",   R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
0036     { "a1e0d1c0",   R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
0037     { "a1e0d1c1",   R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
0038     { "a1e1d0c0",   R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
0039     { "a1e1d0c1",   R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
0040     { "a1e1d1c0",   R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
0041     { "a1e1d1c1",   R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
0042     { "3dg-a",  R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
0043     { "3dg-b",  R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
0044     { "a3vip0", R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
0045     { "a3vip1", R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
0046     { "a3vip3", R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
0047     { "a3vip2", R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
0048     { "a3isp01",    R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
0049     { "a3isp23",    R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
0050     { "a3ir",   R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
0051     { "a2cn0",  R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
0052     { "a2imp01",    R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
0053     { "a2dp0",  R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
0054     { "a2cv0",  R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
0055     { "a2cv1",  R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
0056     { "a2cv4",  R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
0057     { "a2cv6",  R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
0058     { "a2cn2",  R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
0059     { "a2imp23",    R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
0060     { "a2dp1",  R8A779A0_PD_A2DP1, R8A779A0_PD_A3IR },
0061     { "a2cv2",  R8A779A0_PD_A2CV2, R8A779A0_PD_A3IR },
0062     { "a2cv3",  R8A779A0_PD_A2CV3, R8A779A0_PD_A3IR },
0063     { "a2cv5",  R8A779A0_PD_A2CV5, R8A779A0_PD_A3IR },
0064     { "a2cv7",  R8A779A0_PD_A2CV7, R8A779A0_PD_A3IR },
0065     { "a2cn1",  R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
0066     { "a1cnn0", R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
0067     { "a1cnn2", R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
0068     { "a1dsp0", R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
0069     { "a1cnn1", R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
0070     { "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
0071 };
0072
0073 const struct rcar_gen4_sysc_info r8a779a0_sysc_info __initconst = {
0074     .areas = r8a779a0_areas,
0075     .num_areas = ARRAY_SIZE(r8a779a0_areas),
0076 };