soc/renesas/r8a77980-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas R-Car V3H System Controller
0004  *
0005  * Copyright (C) 2018 Renesas Electronics Corp.
0006  * Copyright (C) 2018 Cogent Embedded, Inc.
0007  */
0008
0009 #include <linux/bits.h>
0010 #include <linux/kernel.h>
0011
0012 #include <dt-bindings/power/r8a77980-sysc.h>
0013
0014 #include "rcar-sysc.h"
0015
0016 static const struct rcar_sysc_area r8a77980_areas[] __initconst = {
0017     { "always-on",      0, 0, R8A77980_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
0018     { "ca53-scu",   0x140, 0, R8A77980_PD_CA53_SCU, R8A77980_PD_ALWAYS_ON,
0019       PD_SCU },
0020     { "ca53-cpu0",  0x200, 0, R8A77980_PD_CA53_CPU0, R8A77980_PD_CA53_SCU,
0021       PD_CPU_NOCR },
0022     { "ca53-cpu1",  0x200, 1, R8A77980_PD_CA53_CPU1, R8A77980_PD_CA53_SCU,
0023       PD_CPU_NOCR },
0024     { "ca53-cpu2",  0x200, 2, R8A77980_PD_CA53_CPU2, R8A77980_PD_CA53_SCU,
0025       PD_CPU_NOCR },
0026     { "ca53-cpu3",  0x200, 3, R8A77980_PD_CA53_CPU3, R8A77980_PD_CA53_SCU,
0027       PD_CPU_NOCR },
0028     { "cr7",    0x240, 0, R8A77980_PD_CR7,  R8A77980_PD_ALWAYS_ON },
0029     { "a3ir",   0x180, 0, R8A77980_PD_A3IR, R8A77980_PD_ALWAYS_ON },
0030     { "a2ir0",  0x400, 0, R8A77980_PD_A2IR0,    R8A77980_PD_A3IR },
0031     { "a2ir1",  0x400, 1, R8A77980_PD_A2IR1,    R8A77980_PD_A3IR },
0032     { "a2ir2",  0x400, 2, R8A77980_PD_A2IR2,    R8A77980_PD_A3IR },
0033     { "a2ir3",  0x400, 3, R8A77980_PD_A2IR3,    R8A77980_PD_A3IR },
0034     { "a2ir4",  0x400, 4, R8A77980_PD_A2IR4,    R8A77980_PD_A3IR },
0035     { "a2ir5",  0x400, 5, R8A77980_PD_A2IR5,    R8A77980_PD_A3IR },
0036     { "a2sc0",  0x400, 6, R8A77980_PD_A2SC0,    R8A77980_PD_A3IR },
0037     { "a2sc1",  0x400, 7, R8A77980_PD_A2SC1,    R8A77980_PD_A3IR },
0038     { "a2sc2",  0x400, 8, R8A77980_PD_A2SC2,    R8A77980_PD_A3IR },
0039     { "a2sc3",  0x400, 9, R8A77980_PD_A2SC3,    R8A77980_PD_A3IR },
0040     { "a2sc4",  0x400, 10, R8A77980_PD_A2SC4,   R8A77980_PD_A3IR },
0041     { "a2dp0",  0x400, 11, R8A77980_PD_A2DP0,   R8A77980_PD_A3IR },
0042     { "a2dp1",  0x400, 12, R8A77980_PD_A2DP1,   R8A77980_PD_A3IR },
0043     { "a2cn",   0x400, 13, R8A77980_PD_A2CN,    R8A77980_PD_A3IR },
0044     { "a3vip0", 0x2c0, 0, R8A77980_PD_A3VIP0,   R8A77980_PD_ALWAYS_ON },
0045     { "a3vip1", 0x300, 0, R8A77980_PD_A3VIP1,   R8A77980_PD_ALWAYS_ON },
0046     { "a3vip2", 0x280, 0, R8A77980_PD_A3VIP2,   R8A77980_PD_ALWAYS_ON },
0047 };
0048
0049 const struct rcar_sysc_info r8a77980_sysc_info __initconst = {
0050     .areas = r8a77980_areas,
0051     .num_areas = ARRAY_SIZE(r8a77980_areas),
0052     .extmask_offs = 0x138,
0053     .extmask_val = BIT(0),
0054 };