soc/renesas/r8a7795-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas R-Car H3 System Controller
0004  *
0005  * Copyright (C) 2016-2017 Glider bvba
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/kernel.h>
0010 #include <linux/sys_soc.h>
0011
0012 #include <dt-bindings/power/r8a7795-sysc.h>
0013
0014 #include "rcar-sysc.h"
0015
0016 static struct rcar_sysc_area r8a7795_areas[] __initdata = {
0017     { "always-on",      0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
0018     { "ca57-scu",   0x1c0, 0, R8A7795_PD_CA57_SCU,  R8A7795_PD_ALWAYS_ON,
0019       PD_SCU },
0020     { "ca57-cpu0",   0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
0021       PD_CPU_NOCR },
0022     { "ca57-cpu1",   0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
0023       PD_CPU_NOCR },
0024     { "ca57-cpu2",   0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
0025       PD_CPU_NOCR },
0026     { "ca57-cpu3",   0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
0027       PD_CPU_NOCR },
0028     { "ca53-scu",   0x140, 0, R8A7795_PD_CA53_SCU,  R8A7795_PD_ALWAYS_ON,
0029       PD_SCU },
0030     { "ca53-cpu0",  0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
0031       PD_CPU_NOCR },
0032     { "ca53-cpu1",  0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
0033       PD_CPU_NOCR },
0034     { "ca53-cpu2",  0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
0035       PD_CPU_NOCR },
0036     { "ca53-cpu3",  0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
0037       PD_CPU_NOCR },
0038     { "a3vp",   0x340, 0, R8A7795_PD_A3VP,  R8A7795_PD_ALWAYS_ON },
0039     { "cr7",    0x240, 0, R8A7795_PD_CR7,   R8A7795_PD_ALWAYS_ON },
0040     { "a3vc",   0x380, 0, R8A7795_PD_A3VC,  R8A7795_PD_ALWAYS_ON },
0041     /* A2VC0 exists on ES1.x only */
0042     { "a2vc0",  0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
0043     { "a2vc1",  0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
0044     { "3dg-a",  0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
0045     { "3dg-b",  0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
0046     { "3dg-c",  0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
0047     { "3dg-d",  0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
0048     { "3dg-e",  0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
0049     { "a3ir",   0x180, 0, R8A7795_PD_A3IR,  R8A7795_PD_ALWAYS_ON },
0050 };
0051
0052
0053     /*
0054      * Fixups for R-Car H3 revisions
0055      */
0056
0057 #define HAS_A2VC0   BIT(0)      /* Power domain A2VC0 is present */
0058 #define NO_EXTMASK  BIT(1)      /* Missing SYSCEXTMASK register */
0059
0060 static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
0061     {
0062         .soc_id = "r8a7795", .revision = "ES1.*",
0063         .data = (void *)(HAS_A2VC0 | NO_EXTMASK),
0064     }, {
0065         .soc_id = "r8a7795", .revision = "ES2.*",
0066         .data = (void *)(NO_EXTMASK),
0067     },
0068     { /* sentinel */ }
0069 };
0070
0071 static int __init r8a7795_sysc_init(void)
0072 {
0073     const struct soc_device_attribute *attr;
0074     u32 quirks = 0;
0075
0076     attr = soc_device_match(r8a7795_quirks_match);
0077     if (attr)
0078         quirks = (uintptr_t)attr->data;
0079
0080     if (!(quirks & HAS_A2VC0))
0081         rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
0082                   R8A7795_PD_A2VC0);
0083
0084     if (quirks & NO_EXTMASK)
0085         r8a7795_sysc_info.extmask_val = 0;
0086
0087     return 0;
0088 }
0089
0090 struct rcar_sysc_info r8a7795_sysc_info __initdata = {
0091     .init = r8a7795_sysc_init,
0092     .areas = r8a7795_areas,
0093     .num_areas = ARRAY_SIZE(r8a7795_areas),
0094     .extmask_offs = 0x2f8,
0095     .extmask_val = BIT(0),
0096 };