soc/renesas/r8a774a1-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RZ/G2M System Controller
0004  * Copyright (C) 2018 Renesas Electronics Corp.
0005  *
0006  * Based on Renesas R-Car M3-W System Controller
0007  * Copyright (C) 2016 Glider bvba
0008  */
0009
0010 #include <linux/kernel.h>
0011
0012 #include <dt-bindings/power/r8a774a1-sysc.h>
0013
0014 #include "rcar-sysc.h"
0015
0016 static const struct rcar_sysc_area r8a774a1_areas[] __initconst = {
0017     { "always-on",      0, 0, R8A774A1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
0018     { "ca57-scu",   0x1c0, 0, R8A774A1_PD_CA57_SCU, R8A774A1_PD_ALWAYS_ON,
0019       PD_SCU },
0020     { "ca57-cpu0",   0x80, 0, R8A774A1_PD_CA57_CPU0, R8A774A1_PD_CA57_SCU,
0021       PD_CPU_NOCR },
0022     { "ca57-cpu1",   0x80, 1, R8A774A1_PD_CA57_CPU1, R8A774A1_PD_CA57_SCU,
0023       PD_CPU_NOCR },
0024     { "ca53-scu",   0x140, 0, R8A774A1_PD_CA53_SCU, R8A774A1_PD_ALWAYS_ON,
0025       PD_SCU },
0026     { "ca53-cpu0",  0x200, 0, R8A774A1_PD_CA53_CPU0, R8A774A1_PD_CA53_SCU,
0027       PD_CPU_NOCR },
0028     { "ca53-cpu1",  0x200, 1, R8A774A1_PD_CA53_CPU1, R8A774A1_PD_CA53_SCU,
0029       PD_CPU_NOCR },
0030     { "ca53-cpu2",  0x200, 2, R8A774A1_PD_CA53_CPU2, R8A774A1_PD_CA53_SCU,
0031       PD_CPU_NOCR },
0032     { "ca53-cpu3",  0x200, 3, R8A774A1_PD_CA53_CPU3, R8A774A1_PD_CA53_SCU,
0033       PD_CPU_NOCR },
0034     { "a3vc",   0x380, 0, R8A774A1_PD_A3VC, R8A774A1_PD_ALWAYS_ON },
0035     { "a2vc0",  0x3c0, 0, R8A774A1_PD_A2VC0,    R8A774A1_PD_A3VC },
0036     { "a2vc1",  0x3c0, 1, R8A774A1_PD_A2VC1,    R8A774A1_PD_A3VC },
0037     { "3dg-a",  0x100, 0, R8A774A1_PD_3DG_A,    R8A774A1_PD_ALWAYS_ON },
0038     { "3dg-b",  0x100, 1, R8A774A1_PD_3DG_B,    R8A774A1_PD_3DG_A },
0039 };
0040
0041 const struct rcar_sysc_info r8a774a1_sysc_info __initconst = {
0042     .areas = r8a774a1_areas,
0043     .num_areas = ARRAY_SIZE(r8a774a1_areas),
0044 };