soc/renesas/r8a7742-sysc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RZ/G1H System Controller
0004  *
0005  * Copyright (C) 2020 Renesas Electronics Corp.
0006  */
0007
0008 #include <linux/kernel.h>
0009
0010 #include <dt-bindings/power/r8a7742-sysc.h>
0011
0012 #include "rcar-sysc.h"
0013
0014 static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
0015     { "always-on",      0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
0016     { "ca15-scu",   0x180, 0, R8A7742_PD_CA15_SCU,  R8A7742_PD_ALWAYS_ON,
0017       PD_SCU },
0018     { "ca15-cpu0",   0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
0019       PD_CPU_NOCR },
0020     { "ca15-cpu1",   0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
0021       PD_CPU_NOCR },
0022     { "ca15-cpu2",   0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
0023       PD_CPU_NOCR },
0024     { "ca15-cpu3",   0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
0025       PD_CPU_NOCR },
0026     { "ca7-scu",    0x100, 0, R8A7742_PD_CA7_SCU,   R8A7742_PD_ALWAYS_ON,
0027       PD_SCU },
0028     { "ca7-cpu0",   0x1c0, 0, R8A7742_PD_CA7_CPU0,  R8A7742_PD_CA7_SCU,
0029       PD_CPU_NOCR },
0030     { "ca7-cpu1",   0x1c0, 1, R8A7742_PD_CA7_CPU1,  R8A7742_PD_CA7_SCU,
0031       PD_CPU_NOCR },
0032     { "ca7-cpu2",   0x1c0, 2, R8A7742_PD_CA7_CPU2,  R8A7742_PD_CA7_SCU,
0033       PD_CPU_NOCR },
0034     { "ca7-cpu3",   0x1c0, 3, R8A7742_PD_CA7_CPU3,  R8A7742_PD_CA7_SCU,
0035       PD_CPU_NOCR },
0036     { "rgx",     0xc0, 0, R8A7742_PD_RGX,   R8A7742_PD_ALWAYS_ON },
0037 };
0038
0039 const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
0040     .areas = r8a7742_areas,
0041     .num_areas = ARRAY_SIZE(r8a7742_areas),
0042 };